CN105789316A - Thin film transistor and fabrication method thereof - Google Patents
Thin film transistor and fabrication method thereof Download PDFInfo
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- CN105789316A CN105789316A CN201410819757.3A CN201410819757A CN105789316A CN 105789316 A CN105789316 A CN 105789316A CN 201410819757 A CN201410819757 A CN 201410819757A CN 105789316 A CN105789316 A CN 105789316A
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Abstract
The invention provides a thin film transistor and a fabrication method thereof. The thin film transistor comprises a gate, a gate insulation layer, an intrinsic amorphous silicon layer, an n-type amorphous silicon layer, a source and a drain, wherein the gate insulation layer is arranged between the gate and the intrinsic amorphous silicon layer, the intrinsic amorphous silicon layer comprises a doping region and a non-doping region, the n-type amorphous silicon layer is arranged on the surface of the non-doping region, and the source and the drain are separately arranged on the two sides of the intrinsic amorphous silicon layer, are both in contact with the n-type amorphous silicon layer and the doping region, and are arranged in a separated way. With the existence of the n-type amorphous silicon layer and the doping region, the electron mobility can be reduced, so that the leakage current can be effectively reduced when the thin film transistor is in a switch-off state, and the electrical characteristic is improved.
Description
Technical field
The present invention relates to a kind of thin film transistor (TFT) and preparation method thereof.
Background technology
Thin film transistor (TFT) is applied to active display, it is common that be used as the switch of storage capacitors charge or discharge.Such thin film transistor (TFT) is formed in substrate of glass, and it includes grid, gate insulator, channel layer, source electrode and drain electrode.Grid is in order to be turned on and off the electron channel in channel layer.Gate insulator cover grid, to avoid grid and channel layer in electrical contact.Channel layer is positioned on gate insulator, it is possible to provide the electron channel of electric transmission.Source electrode and drain electrode may be contained within channel layer to be connected with the data wire of display and pixel electrode respectively.
When the grid applying voltage to thin film transistor (TFT), electron channel can be formed on the bottom of channel layer, and when also drain electrode is applied voltage, electrons passes through the electron channel stream of channel layer to drain electrode from source electrode, makes formation path between source electrode and drain electrode.When stopping that grid is applied voltage, thin film transistor (TFT) is closed, and namely the electron channel bottom channel layer can disappear, and makes to become open circuit between source electrode and drain electrode.
So, there is the phenomenon of leakage current in current thin film transistor (TFT), and when grid not applying voltage or applying negative voltage, the channel layer surface between source electrode and drain electrode has leakage path and produces, thus forming leakage current.The electrical characteristic causing thin film transistor (TFT) is worsened by the generation of leakage current, finally affects the display quality of liquid crystal display, is the phenomenon that need to overcome.
Summary of the invention
In consideration of it, be necessary that providing a kind of reduces or remits the thin film transistor (TFT) that leakage current produces, this thin film transistor (TFT) includes grid, gate insulator, intrinsic amorphous silicon layer, n-type amorphous silicon layer, source electrode and drain electrode.This gate insulator is located between this grid and this intrinsic amorphous silicon layer.This intrinsic amorphous silicon layer includes doped region and undoped region.This n-type amorphous silicon layer is positioned at this undoped region field surface.This source electrode lays respectively at these intrinsic amorphous silicon both sides and all contacts and setting separated from one another with this n-type amorphous silicon layer and this doped region with this drain electrode.
There is a need to provide the manufacture method of a kind of thin film transistor (TFT), utilize the method can produce the thin film transistor (TFT) that leakage current is less.
The method comprises the steps:
Thering is provided substrate, and sequentially form grid and gate insulator on this substrate, this gate insulator covers this grid；
This gate insulator sequentially forms intrinsic amorphous silicon layer and n-type amorphous silicon layer；
The two relative side of this intrinsic amorphous silicon layer not hidden by this n-type amorphous silicon layer is carried out doping treatment, to form doped region；And
This n-type amorphous silicon layer and this doped region are formed source electrode and drain electrode, and removes this n-type amorphous silicon layer between this source electrode and this drain electrode and part intrinsic amorphous silicon layer.
Compared to prior art, thin film transistor (TFT) provided by the present invention and preparation method thereof, due to the existence of this n-type amorphous silicon layer and this doped region, electron mobility can be reduced, make when thin film transistor (TFT) is closed, it is possible to effectively reduce leakage current, thus improving electrical characteristic.Additionally, due to this doped region is that processing technology is simple, saves processing procedure cost by being made directly doping treatment formation on the two side faces of this intrinsic amorphous silicon layer.
Accompanying drawing explanation
Fig. 1 is the section of structure of the thin film transistor (TFT) manufactured by the manufacture method of the thin film transistor (TFT) according to the present invention the first better embodiment；
Fig. 2 is the flow chart of the manufacture method of thin film transistor (TFT) in Fig. 1；
Fig. 3 to 10 is the sectional view of each steps flow chart in Fig. 2；
Figure 11 is the flow chart of the manufacture method of the thin film transistor (TFT) of another better embodiment of the present invention；
Figure 12 to 19 is the sectional view of each steps flow chart in Figure 11.
Main element symbol description
| Thin film transistor (TFT) | 100 |
| Grid | 110 |
| Gate insulator | 120 |
| Intrinsic amorphous silicon layer | 130 |
| Undoped region | 131 |
| Doped region | 132 |
| First semiconductor layer | 133 |
| N-type amorphous silicon layer | 140 |
| Second semiconductor layer | 141 |
| Second metal level | 150 |
| Source electrode | 151 |
| Drain electrode | 152 |
| First photoresist layer pattern | 161 |
| Second photoresist layer | 170 |
| Second photoresist layer pattern | 171 |
| Substrate | 200 |
Following detailed description of the invention will further illustrate the present invention in conjunction with above-mentioned accompanying drawing, and wherein, the present invention illustrates for bottom gate polar form thin film transistor (TFT).
Detailed description of the invention
Refer to Fig. 1, be the section of structure of the thin film transistor (TFT) 100 manufactured by manufacture method of thin film transistor (TFT) 100 according to the present invention the first better embodiment.Described thin film transistor (TFT) 100 is formed in substrate 200, and this thin film transistor (TFT) 100 includes grid 110, gate insulator 120, intrinsic amorphous silicon layer 130, n-type amorphous silicon layer 140, source electrode 151 and drain electrode 152.This grid 110 is positioned in this substrate 200, and this gate insulator 120 is positioned at this grid 110 and away from the side of described substrate 200 and covers this grid 110.This intrinsic amorphous silicon layer 130 is located on this gate insulator 120 and is positioned at the position corresponding with described grid 110, the width of this intrinsic amorphous silicon layer 130 is less than or equal to the width of this grid, and this gate insulator 120 is for separating this grid 110 with mutually insulated with this intrinsic amorphous silicon layer 130.This n-type amorphous silicon layer 140 is positioned in this intrinsic amorphous silicon layer 130 and part covers described intrinsic amorphous silicon layer 130.This source electrode 151 and this drain electrode 152 are formed in side away from described grid 110 of described gate insulator 120, described intrinsic amorphous silicon layer 130 and described n-type amorphous silicon layer 140, and this source electrode 151 with this drain electrode 152 in setting separated from one another.This intrinsic amorphous silicon layer 130 part is revealed between this source electrode 151 and this drain electrode 152.
This trapezoidal structure of intrinsic amorphous silicon layer 130, it includes undoped region 131 and doped region 132, wherein, two opposite flanks that this doped region 132 is this intrinsic amorphous silicon layer 130 process through phosphorus doping or are formed after boron doping treatment, and the thickness of this doped region 132 is equal with the thickness of this n-type amorphous silicon layer 140.This undoped region 131 is formed at the end face of this intrinsic amorphous silicon layer 130, and these two ends, undoped region 131 are located on this undoped region 131 and are covered to this n-type amorphous silicon layer 140.This n-type amorphous silicon layer 140 is covered by this source electrode 151 and this drain electrode 152 respectively with this doped region 132.This n-type amorphous silicon layer 140 and this doped region 132 play reduce this intrinsic amorphous silicon layer 130 and this source electrode 151 and and this drain electrode 152 between the effect of contact impedance, at this thin film transistor (TFT) 100 in off position, when namely described grid 110 not being applied voltage or applies negative voltage, can effectively reduce leakage current.
Refer to the manufacture method flow chart that Fig. 2, Fig. 2 are thin film transistor (TFT)s 100 in Fig. 1.The method comprises the steps:
Step S201, refer to Fig. 3, it is provided that described substrate 200, and sequentially forms described grid 110 and described gate insulator 120 in this substrate 200, makes described gate insulator 120 be covered on this grid 110.Specifically, in this substrate 200, first form the first metal layer, then utilize dry method etch technology that this first metal layer is patterned as described grid 110, form described gate insulator 120 again through Plasma Enhanced Chemical Vapor Deposition (PECVD).
The material of described substrate 200 can be selected from glass, quartz, organic polymer or other transparent material applicatory.The material of described grid 110 is metal or other conductive material, for instance alloy, metal-oxide, metal nitride or metal oxynitride etc..The material of described gate insulator 120 can be selected from inorganic material (such as silicon oxide, silicon boride and boron silicon oxide etc.), organic material or other material applicatory and combination thereof.
Step S202, refer to Fig. 4, after this gate insulator 120 that completes, sequentially forms the first semiconductor layer 133 and the second semiconductor layer 141 on this gate insulator 120.The material of this first semiconductor layer 133 is intrinsic amorphous silicon, and the material of this second semiconductor layer 141 is n-type non-crystalline silicon.
Step S203, refer to Fig. 5, forms the first photoresist layer (non-icon), and pattern this first photoresist layer to form the first photoresist layer pattern 160 on this second semiconductor layer 141, and the position of this first photoresist layer pattern 160 is just to described grid 110.This second semiconductor layer 141 and this first semiconductor layer 133 of not covered by this first photoresist layer pattern 160 is etched by dry etch process, to form this n-type amorphous silicon layer 140 in this second semiconductor layer 141, this intrinsic amorphous silicon layer 130 is formed in this first semiconductor layer 133, wherein, two opposite flanks of this intrinsic amorphous silicon layer 130 are not hidden by this n-type amorphous silicon layer 140.
Step S204, refer to Fig. 6, and two opposite flanks of this intrinsic amorphous silicon layer 130 revealed are carried out doping treatment to form this doped region 132.The present embodiment adopts the mode of ion implanting to carry out phosphorus doping, and the thickness of Doping Phosphorus is suitable with the thickness of this n-type amorphous silicon layer 140.Certainly also this n-type amorphous silicon layer 140 comparable is slightly thick or slightly thin.In other embodiments, the material of doping is not restricted to phosphorus, it is also possible to be boron or other material.Regardless of being which kind of material that adulterates, doping way is not limited to ion implanting mode, it is also possible to be Cement Composite Treated by Plasma mode etc..Owing to this doped region 132 is that processing technology is simple, saves processing procedure cost by being made directly doping treatment formation on two opposite flanks of this intrinsic amorphous silicon layer 130.
Step S205, refer to Fig. 7, after doping treatment completes, removes this first photoresist layer pattern 160.Wherein, this first photoresist layer is positive photoresistance, and its part being irradiated to by light can be dissolved in photoresistance developer solution, and the part do not irradiated by light then will not be dissolved in photoresistance developer solution, in other embodiments, described first photoresist layer can also the contrary negative photoresistance of operating characteristic.
Step S206, refer to Fig. 8, after removing this first photoresist layer pattern 160, described substrate 200 is formed the second metal level 150 covering this gate insulator 120, this n-type amorphous silicon layer 140 and this doped region 132, and on this second metal level 150, forms the second photoresist layer 170.This second metal level 150 and described n-type amorphous silicon layer 140, this doped region 132 and be emerging in the described gate insulator 120 of these intrinsic amorphous silicon layer 130 both sides and contact.The material of this second metal level 150 is metal or other conductive material, for instance alloy, metal-oxide, metal nitride or metal oxynitride etc..In the present embodiment, described second photoresist layer 170 is positive photoresistance, and its part being irradiated to by light can be dissolved in photoresistance developer solution, and the part do not irradiated by light then will not be dissolved in photoresistance developer solution.In other embodiments, described second photoresist layer 170 can also the contrary negative photoresistance of operating characteristic.
Step S207, refer to Fig. 9, patterning this second photoresist layer 170 to form the second photoresistance pattern 171, this second photoresist layer pattern 171 is covered in this second metal level 150 both sides, and makes second metal level 150 corresponding with the mid portion of this n-type amorphous silicon layer 140 reveal.
Step S208, refer to Figure 10, this second metal level 150 that etching is not covered by this second photoresist layer pattern 171 is to form described source electrode 151 and described drain electrode 152, etch away the n-type amorphous silicon layer 140 between described source electrode 151 and described drain electrode 152 and part intrinsic amorphous silicon layer 130 simultaneously, finally remove this second photoresist layer pattern 171.So far, this thin film transistor base plate 100 completes.
Refer to the manufacture method flow chart that Figure 11, Figure 11 are the thin film transistor (TFT)s 100 of another better embodiment of the present invention.The method comprises the steps:
Step S1101, refer to Figure 12, it is provided that described substrate 200, and sequentially forms described grid 110 and described gate insulator 120 in this substrate 200, makes described gate insulator 120 be covered on this grid 110.Specifically, in this substrate 200, first form the first metal layer, then utilize dry method etch technology that this first metal layer is patterned as described grid 110, form described gate insulator 120 again through Plasma Enhanced Chemical Vapor Deposition (PECVD).
The material of described substrate 200 can be selected from glass, quartz, organic polymer or other transparent material applicatory.The material of described grid 110 is metal or other conductive material, for instance alloy, metal-oxide, metal nitride or metal oxynitride etc..The material of described gate insulator 120 can be selected from inorganic material (such as silicon oxide, silicon boride and boron silicon oxide etc.), organic material or other material applicatory and combination thereof.
Step S1102, refer to Figure 13, after this gate insulator 120 that completes, sequentially forms the first semiconductor layer 133 and the second semiconductor layer 141 on this gate insulator 120.The material of this first semiconductor layer 133 is intrinsic amorphous silicon, and the material of this second semiconductor layer 141 is n-type non-crystalline silicon.
Step S1103, refer to Figure 14, forms the first photoresist layer (non-icon), and pattern this first photoresist layer to form the first photoresist layer pattern 160 on this second semiconductor layer 141, and the position of this first photoresist layer pattern 160 is just to described grid 110.This second semiconductor layer 141 and this first semiconductor layer 133 of not covered by this first photoresist layer pattern 160 is etched by dry etch process, to form this n-type amorphous silicon layer 140 in this second semiconductor layer 141, form this intrinsic amorphous silicon layer 130 in this first semiconductor layer 133.Wherein, two opposite flanks of this intrinsic amorphous silicon layer 130 are not hidden by this n-type amorphous silicon layer 140.This first photoresist layer is positive photoresistance, and its part being irradiated to by light can be dissolved in photoresistance developer solution, and the part do not irradiated by light then will not be dissolved in photoresistance developer solution, and in other embodiments, described first photoresist layer can also the contrary negative photoresistance of operating characteristic.
Step S1104, refer to Figure 15, removes this first photoresist layer pattern 160, makes this doped region 132 and this n-type amorphous silicon layer 140 reveal.
Step S1105, refer to Figure 16, and two opposite flanks and this n-type amorphous silicon layer 140 to this intrinsic amorphous silicon layer 130 revealed carry out doping treatment, and two opposite flanks of this intrinsic amorphous silicon layer 130 define this doped region 132 after doping treatment.Owing to not having blocking of this first photoresist layer pattern 160, this n-type amorphous silicon layer 140 also have passed through doping treatment, also contribute to reducing this intrinsic amorphous silicon layer 130 and this source electrode 151 and and this drain electrode 152 between contact impedance, thus reducing leakage current.The present embodiment adopts the mode of ion implanting to carry out phosphorus doping process.In other embodiments, the material of doping is not restricted to phosphorus, it is also possible to be boron or other material.Regardless of being which kind of material that adulterates, doping way is not limited to ion implanting mode, it is also possible to be Cement Composite Treated by Plasma mode etc..Owing to this doped region 132 of the present invention is that processing technology is simple, saves processing procedure cost by being made directly doping treatment formation on the doped region 132 of this intrinsic amorphous silicon layer 130.
Step S1106, refer to Figure 17, after removing this first photoresist layer pattern 160, described substrate 200 is formed the second metal level 150 covering this gate insulator 120, this n-type amorphous silicon layer 140 and this doped region 132, and on this second metal level 150, forms the second photoresist layer 170.This second metal level 150 and described n-type amorphous silicon layer 140, this doped region 132 and be emerging in the described gate insulator 120 of these intrinsic amorphous silicon layer 130 both sides and contact.The material of this second metal level 150 is metal or other conductive material, for instance alloy, metal-oxide, metal nitride or metal oxynitride etc..In the present embodiment, described second photoresist layer 170 is positive photoresistance, and its part being irradiated to by light can be dissolved in photoresistance developer solution, and the part do not irradiated by light then will not be dissolved in photoresistance developer solution.In other embodiments, described second photoresist layer 170 can also the contrary negative photoresistance of operating characteristic.
Step S1107, refer to Figure 18, patterning this second photoresist layer 170 to form the second photoresistance pattern 171, this second photoresist layer pattern 171 is covered in this second metal level 150 both sides, and makes second metal level 150 corresponding with the mid portion of this n-type amorphous silicon layer 140 reveal.
Step S1108, refer to Figure 19, this second metal level 150 that etching is not covered by this second photoresist layer pattern 171 is to form described source electrode 151 and described drain electrode 152, etch away the n-type amorphous silicon layer 140 between described source electrode 151 and described drain electrode 152 and part intrinsic amorphous silicon layer 130 simultaneously, finally remove this second photoresist layer pattern 171.So far, this thin film transistor base plate 100 completes.
Above example is only in order to illustrate technical scheme and unrestricted, although the present invention being described in detail with reference to preferred embodiment, it will be understood by those within the art that, technical scheme can be modified or equivalent replacement, without deviating from the spirit and scope of technical solution of the present invention.
Claims (12)
1. a thin film transistor (TFT), this thin film transistor (TFT) includes grid, gate insulator, intrinsic amorphous silicon layer, n-type amorphous silicon layer, source electrode and drain electrode；This gate insulator is located between this grid and this intrinsic amorphous silicon layer；This intrinsic amorphous silicon layer includes doped region and undoped region；This n-type amorphous silicon layer is positioned at this undoped region field surface；This source electrode lays respectively at these intrinsic amorphous silicon both sides and all contacts and setting separated from one another with this n-type amorphous silicon layer and this doped region with this drain electrode.
2. thin film transistor (TFT) as claimed in claim 1, it is characterized in that, this gate insulator covers this grid, this intrinsic amorphous silicon layer is located at the position corresponding with described grid, this n-type amorphous silicon layer is positioned at this undoped region and away from the side of this grid and covers this two ends, undoped region, and this source electrode and this drain electrode are formed on this gate insulator, this intrinsic amorphous silicon layer and this n-type amorphous silicon layer and cover this gate insulator, this doped region and this n-type amorphous silicon layer.
3. thin film transistor (TFT) as claimed in claim 1, it is characterised in that the material that this doped region adulterates includes phosphorus or boron.
4. thin film transistor (TFT) as claimed in claim 1, it is characterised in that the two relative side of this intrinsic amorphous silicon layer forms this doped region through doping treatment.
5. thin film transistor (TFT) as claimed in claim 4, it is characterised in that the trapezoidal structure of this intrinsic amorphous silicon layer, this n-type amorphous silicon layer is positioned at the end face of this intrinsic amorphous silicon layer.
6. thin film transistor (TFT) as claimed in claim 1, it is characterised in that this doping treatment mode includes ion implanting mode or Cement Composite Treated by Plasma mode.
7. thin film transistor (TFT) as claimed in claim 1, it is characterised in that the thickness of this doped region is suitable with this n-type amorphous silicon layer thickness.
8. a manufacture method for thin film transistor (TFT), the method draws together following steps:
Thering is provided substrate, and sequentially form grid and gate insulator on this substrate, this gate insulator covers this grid；
This gate insulator sequentially forms intrinsic amorphous silicon layer and n-type amorphous silicon layer；
The two relative side of this intrinsic amorphous silicon layer not hidden by this n-type amorphous silicon layer is carried out doping treatment, to form doped region；And
This n-type amorphous silicon layer and this doped region are formed source electrode and drain electrode, and removes this n-type amorphous silicon layer between this source electrode and this drain electrode and part intrinsic amorphous silicon layer.
9. the manufacture method of thin film transistor (TFT) as claimed in claim 8, it is characterised in that the method forming this doped region includes:
This gate insulator sequentially forms the first semiconductor layer, the second semiconductor layer；
This second conductor layer is formed the first photoresist layer and patterns this first photoresist layer to form the first photoresist layer pattern；
Etching is not by described first semiconductor layer of this first photoresist layer pattern covers and described second semiconductor layer, to form this intrinsic amorphous silicon layer and this n-type amorphous silicon layer respectively；
The two relative side of this intrinsic amorphous silicon layer is carried out doping treatment to form this doped region；And
Remove this first photoresist layer pattern.
10. the manufacture method of thin film transistor (TFT) as claimed in claim 8, it is characterised in that the method forming this doped region includes:
This gate insulator sequentially forms the first semiconductor layer, the second semiconductor layer；
This second conductor layer is formed and patterns this first photoresist layer to form the first photoresist layer pattern；
Etching is not by described first semiconductor layer of this first photoresist layer pattern covers and described second semiconductor layer, to form this intrinsic amorphous silicon layer and this n-type amorphous silicon layer respectively；
Remove this first photoresist layer pattern；And
Two opposite flanks and this n-type amorphous silicon layer to this intrinsic amorphous silicon layer carry out doping treatment, form this doped region through two opposite flanks of this intrinsic amorphous silicon layer of doping treatment.
11. the manufacture method of the thin film transistor (TFT) as described in one of claim 9 or 10, it is characterised in that this doping treatment includes phosphorus doping and processes or boron doping treatment.
12. the manufacture method of thin film transistor (TFT) as claimed in claim 8, it is characterised in that this doping treatment mode includes ion implanting mode or Cement Composite Treated by Plasma mode.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410819757.3A CN105789316A (en) | 2014-12-25 | 2014-12-25 | Thin film transistor and fabrication method thereof |
| TW103146463A TWI599050B (en) | 2014-12-25 | 2014-12-31 | Thin film transistor and method of manufacturing the same |
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| CN201410819757.3A CN105789316A (en) | 2014-12-25 | 2014-12-25 | Thin film transistor and fabrication method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109545751A (en) * | 2018-10-15 | 2019-03-29 | 深圳市华星光电技术有限公司 | Method for manufacturing thin film transistor array substrate |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1440080A (en) * | 2002-02-22 | 2003-09-03 | 日本电气株式会社 | Channel etching film transistor |
| CN1624933A (en) * | 2004-12-21 | 2005-06-08 | 友达光电股份有限公司 | Thin film transistor and manufacturing method thereof |
| CN1630097A (en) * | 2004-08-27 | 2005-06-22 | 友达光电股份有限公司 | Structure of thin-film transistor and method of manufacturing same |
| US20050219435A1 (en) * | 2004-04-06 | 2005-10-06 | Lg.Philips Lcd Co., Ltd. | Liquid crystal display device including driving circuit and method of fabricating the same |
| CN102136498A (en) * | 2009-12-21 | 2011-07-27 | 株式会社半导体能源研究所 | Thin film transistor |
-
2014
- 2014-12-25 CN CN201410819757.3A patent/CN105789316A/en active Pending
- 2014-12-31 TW TW103146463A patent/TWI599050B/en active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1440080A (en) * | 2002-02-22 | 2003-09-03 | 日本电气株式会社 | Channel etching film transistor |
| US20050219435A1 (en) * | 2004-04-06 | 2005-10-06 | Lg.Philips Lcd Co., Ltd. | Liquid crystal display device including driving circuit and method of fabricating the same |
| CN1630097A (en) * | 2004-08-27 | 2005-06-22 | 友达光电股份有限公司 | Structure of thin-film transistor and method of manufacturing same |
| CN1624933A (en) * | 2004-12-21 | 2005-06-08 | 友达光电股份有限公司 | Thin film transistor and manufacturing method thereof |
| CN102136498A (en) * | 2009-12-21 | 2011-07-27 | 株式会社半导体能源研究所 | Thin film transistor |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109545751A (en) * | 2018-10-15 | 2019-03-29 | 深圳市华星光电技术有限公司 | Method for manufacturing thin film transistor array substrate |
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| TW201624724A (en) | 2016-07-01 |
| TWI599050B (en) | 2017-09-11 |
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