CN105788644B - Shift register, scanner driver and organic light emitting display - Google Patents
Shift register, scanner driver and organic light emitting display Download PDFInfo
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- CN105788644B CN105788644B CN201410811968.2A CN201410811968A CN105788644B CN 105788644 B CN105788644 B CN 105788644B CN 201410811968 A CN201410811968 A CN 201410811968A CN 105788644 B CN105788644 B CN 105788644B
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Abstract
In shift register provided by the invention, scanner driver and organic light emitting display, by a feedback loop being arranged in a shift register to stablize the voltage of first node, to reduce influence of the coupling to first node of parasitic capacitance, improve the stability of scanner driver output, and then improve the display quality of organic light emitting display, and circuit structure is simple, strong antijamming capability.
Description
Technical field
The present invention relates to technical field of flat panel display, in particular to a kind of shift register, scanner driver and organic hair
Optical display unit.
Background technique
Organic light emitting display utilizes Organic Light Emitting Diode (full name in English Organic Lighting Emitting
Diode, abbreviation OLED) display image is a kind of display that active is luminous, display mode and traditional thin film transistor (TFT) liquid
Crystal display (full name in English Thin Film Transistor liquid crystal display, abbreviation TFT-LCD) display
Mode is different, is not necessarily to backlight, moreover, have contrast height, fast response time, it is frivolous many advantages, such as.Therefore, organic light emission
Display is known as that the display of a new generation of Thin Film Transistor-LCD can be replaced.
Referring to FIG. 1, its structural schematic diagram for the organic light emitting display of the prior art.As shown in Figure 1, existing have
Machine active display 100 includes: the pixel array 120 connecting with data line and scan line；To the data line, (D1 to Dm) is mentioned
For the data driver 140 of data-signal；To the scan line (scanner driver 160 of S1 to Sn) offer scanning signal；To
The scanner driver 100 provides the sequence drivers 180 of clock signal.
Wherein, existing scanner driver 160 generally includes multiple transistors, initial signal line IN, clock cable
CLK1, CLK2, power supply high level VGH and power supply low level VGL, since there are parasitic capacitance, the scanner drivers for transistor
160 by clock cable CLK1, CLK2 receive clock signal when, if the received clock signal of clock cable CLK1, CLK2
It jumps, especially the received clock signal of clock cable CLK2 is low level, the coupling of parasitic capacitance by high level jump
Cooperation, which is used, can not only make the stability of the scanner driver 160 decline, and can weaken its anti-interference ability.
Base this, how to solve existing scanner driver influences its stability and anti-dry because of the coupling of parasitic capacitance
The problem of disturbing ability, at those skilled in the art's technical problem urgently to be resolved.
Summary of the invention
The purpose of the present invention is to provide a kind of shift register, scanner driver and organic light emitting displays, to solve
Existing active matrix/organic light emitting display influences contrast because there is dark-state leakage current.
To solve the above problems, the present invention provides a kind of shift register, the shift register includes:
The first transistor is connected between first node and initial signal line, and grid is connected with the first clock cable；
Second transistor is connected between second clock signal wire and scanning output end, and grid is connected to first node；
Third transistor is connected between power supply high level and third node, and grid is connected to scanning output end；
4th transistor is connected between third node and power supply low level, and grid is connected with the first clock cable；
5th transistor is connected between power supply high level and scanning output end, and grid is connected to third node；
6th transistor is connected between second node and initial signal line, and grid is connected with the first clock cable；
7th transistor, is connected between first node and second node, and grid is connected with second clock signal wire；
First capacitor device, is connected between first node and scanning output end；
Second capacitor is connected between power supply high level and second node.
Optionally, in the shift register, first clock cable is for providing the first clock signal, institute
Second clock signal wire is stated for providing second clock signal, the phase phase of first clock signal and second clock signal
Instead.
Optionally, in the shift register, the first film transistor to the 7th thin film transistor (TFT) is p-type
Thin film transistor (TFT).
Optionally, in the shift register, the first film transistor to the 7th thin film transistor (TFT) is two-way
PMOS tube or two-way P-type thin film transistor.
Optionally, in the shift register, the scanning output end is connect with scanning output line, and the displacement is posted
Scanning signal is transmitted to scanning output line by scanning output end by storage.
Correspondingly, the scanner driver includes: multiple as described above the present invention also provides a kind of scanner driver
Shift register, the multiple shift register are in turn connected to form multilevel structure, and the multilevel structure is swept for being sequentially generated
Retouch signal.
Optionally, in the scanner driver, the scanning output end of the every level-one of multilevel structure respectively with sweep
Output line connection is retouched, for successively providing the scanning signal to the scanning output line.
Optionally, in the scanner driver, the input terminal and initial signal line of the multilevel structure first order connect
It connects, for receiving initial signal；The input terminal of the second level to N grades is connect with the scanning output line of previous stage respectively, for connecing
Receive the scanning signal of previous stage output.
Optionally, in the scanner driver, when the scanner driver passes through the first clock cable and second
Clock signal wire receives the first clock signal and second clock signal, the phase of first clock signal and second clock signal respectively
Position is opposite.
Correspondingly, the organic light emitting display includes institute as above the present invention also provides a kind of organic light emitting display
The scanner driver stated.
In shift register provided by the invention, scanner driver and organic light emitting display, by shift LD
One feedback loop is set to stablize the voltage of first node, to reduce the coupling of parasitic capacitance to first node in device
Influence, improve the stability of scanner driver output, and then improve the display quality of organic light emitting display, Er Qie electricity
Line structure is simple, strong antijamming capability.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of the organic light emitting display of the prior art；
Fig. 2 is the circuit diagram of the shift register of the embodiment of the present invention；
Fig. 3 is timing diagram of the shift register of the embodiment of the present invention in a frame；
Fig. 4 is the structural schematic diagram of the scanner driver of the embodiment of the present invention.
Specific embodiment
Below in conjunction with the drawings and specific embodiments to a kind of shift register proposed by the present invention, scanner driver and organic
Active display is described in further detail.According to following explanation and claims, advantages and features of the invention will be more clear
Chu.It should be noted that attached drawing is all made of very simplified form and using non-accurate ratio, only to conveniently, lucidly
Aid in illustrating the purpose of the embodiment of the present invention.
Referring to FIG. 2, its structural schematic diagram for the shift register of the embodiment of the present invention.As shown in Fig. 2, the displacement
Register 20 includes: the first transistor M1, is connected between first node N1 and initial signal line IN, grid and the first clock
Signal wire CLK1 is connected；Second transistor M2 is connected between second clock signal wire CLK2 and scanning output end OUT, grid
Pole is connected to first node N1；Third transistor M3 is connected between power supply high level VGH and third node N3, and grid connects
It is connected to scanning output end OUT；4th transistor M4 is connected between third node N3 and power supply low level VGL, grid and
One clock cable CLK1 is connected；5th transistor M5 is connected between power supply high level VGH and scanning output end OUT, grid
Pole is connected to third node N3；6th transistor M6 is connected between second node N2 and initial signal line IN, grid and
One clock cable CLK1 is connected；7th transistor M7 is connected between first node N1 and second node N2, grid and
Two clock cable CLK2 are connected；First capacitor device C1, is connected between first node N1 and scanning output end OUT；Second electricity
Container C2 is connected between power supply high level VGH and second node N2.
Specifically, the shift register 20 is believed with initial signal line IN, the first clock cable CLK1 and second clock
Number line CLK2 connection, the first clock cable CLK1 are used to provide the first clock signal, institute for the shift register 20
Second clock signal wire CLK2 is stated for providing second clock signal, first clock cable for the shift register 20
The first clock signal that CLK1 is provided is opposite with the second clock signal phase that second clock signal wire CLK2 is provided.The starting
Signal wire IN is used to provide initial signal for the shift register 20.The shift register 20 passes through scanning output end OUT
Export scanning signal.
With continued reference to FIG. 2, the shift register 20 includes 7 transistors and two capacitors, 7 transistors are
P-type transistor.Wherein, the drain electrode (or source electrode) of the first transistor M1, the grid of second transistor M2, the 7th transistor M7
Drain electrode (or source electrode) and one end of first capacitor device C1 be connected to first node N1, the other end of the first capacitor device C1
Be connected to scanning output end OUT, the drain electrode (or source electrode) of the 6th transistor M6, the 7th transistor M7 source electrode (or drain electrode)
It is connected to second node N2 with one end of the second capacitor C2, the other end of the second capacitor C2 is connected to the high electricity of power supply
The drain electrode (or source electrode) of flat VGH, the third transistor M3, the drain electrode (or source electrode) of the 4th transistor M4 and the 5th transistor M5
Grid be connected to third node N3.
Preferably, the first transistor M1 to the 7th transistor M7 is brilliant using two-way PMOS tube or two-way P-type thin film field-effect
Body pipe, source electrode and drain electrode are interchangeable.
Referring to FIG. 3, it is timing diagram of the shift register of the embodiment of the present invention in a frame.As shown in figure 3, IN is
The timing diagram for the initial signal that initial signal line provides, initial signal line IN keeps high level in a frame, when CLK1 is first
The timing diagram for the first clock signal that clock signal wire provides, CLK2 be the second clock signal that provides of second clock signal wire when
The phase of sequence figure, the first clock signal and second clock signal is just on the contrary, when the first clock signal being high level second
Clock signal is low level, and when the first clock signal is low level, second clock signal is high level, and OUT is that scanning output end is defeated
The timing diagram of scanning signal out.The working principle of the shift register 20 are as follows:
When the first clock signal that the initial signal line IN initial signal provided and the first clock cable CLK1 are provided is equal
When becoming high level from low level from the second clock signal that high level becomes low level, second clock signal wire CLK2 is provided,
4th transistor M4 is connected and exports the grid of low level to the 5th transistor M5, is also switched on so as to cause the 5th transistor M5,
Thus the 5th transistor M5 exports high level VGH to scanning output end OUT.
In the process, since the first clock cable CLK1 the first clock signal transitions provided are low level, so that
The first transistor M1, the 4th transistor M4 and the 6th transistor M6 are connected, at this time drain electrode (the i.e. first node of the first transistor M1
N1) and the drain electrode (i.e. second node N2) of the 6th transistor M6 is low level.Due to the source electrode and power supply of the 4th transistor M4
Low level VGL connection, therefore the drain electrode (i.e. the grid of the 5th transistor M5) of the 4th transistor M4 is also low level, so that
5th transistor M5 conducting, since the source electrode of the 5th transistor M5 is connect with power supply high level VGH, the 5th transistor M5's
Drain electrode becomes high level, since the drain electrode of the 5th transistor M5 is connect with scanning output end OUT, the 5th transistor M5 output
High level VGH to scanning output end OUT.
When initial signal line IN provide initial signal and the first clock cable CLK1 provide the first clock signal by
When the second clock signal that low level becomes high level, second clock signal wire CLK2 is provided becomes low level from high level, the
Seven transistor M7 conducting, is transmitted to first node N1 for the low level signal of second node N2, meanwhile, second transistor M2 conducting
And low level is exported to scanning output end OUT.
In the process, due to the first clock cable CLK1 provide the first clock signal transitions be high level, first
Transistor M1, the 4th transistor M4 and the 6th transistor M6 cut-off, and the grid (i.e. first node N1) of second transistor M2 is
Low level, therefore second transistor M2 is connected, the drain electrode of second transistor M2 provided with second clock signal wire CLK2 the
Two clock signals are low level by high level jump, and thus scanning output end OUT becomes low level from high level, to realize
The purpose of output.
Simultaneously as the second clock signal jump that second clock signal wire CLK2 is provided is low level, the 7th transistor
M7 conducting, so that the low level signal of second node N2 is transmitted to first node N1.Due to the first capacitor device C1 and
The coupling of the parasitic capacitance of two capacitor C2, the grid voltage of second transistor M2 with second transistor M2 drain electrode electricity
Pressure is synchronous to be reduced, and the voltage of first node N1 is by VGL+ | Vth | drop to 2GL+ | and Vth | (threshold voltage that Vth is transistor),
Second transistor M2 is tended to remain on and is exported low level to scanning output end OUT terminal.As it can be seen that by by second node N2's
Low level signal is transmitted to first node N1, can prevent influence of other coupled signals to first node N1, so that second is brilliant
Body pipe M2 exports stable low level to scanning output end OUT.
When initial signal line IN provide initial signal keep high level, the first clock cable CLK1 provide first when
Clock signal becomes high electricity from low level from the second clock signal that high level becomes low level, second clock signal wire CLK2 is provided
Usually, the first transistor M1, the 4th transistor M4 and the 6th transistor M6 conducting, the grid (first node of second transistor M2
N1) voltage is increased to VGH by low level, while the voltage of second node N2 is increased to VGH, and second transistor M2 is become from being connected
Cut-off, the 5th transistor M5 grid voltage become VGL+Vth, therefore the 5th transistor M5 is connected and exports high level VGH to sweeping
Retouch output end OUT.
When initial signal line IN provide initial signal keep high level, the first clock cable CLK1 provide first when
Clock signal becomes low electricity from high level from the second clock signal that low level becomes high level, second clock signal wire CLK2 is provided
Usually, the 7th transistor M7 is connected, and the high level signal of second node N2 is transmitted to first node N1, meanwhile, the second crystal
Pipe M2 cut-off, scanning output end OUT keep high level.
During the second clock signal that second clock signal wire CLK2 is provided is low level by high level jump, by
In second transistor M2 grid and source level there are parasitic capacitance, the second clock signal that is connected with the source level of second transistor M2
Second clock signal provided by line CLK2 can drag down the voltage of first node N1.But since the 7th transistor M7 at this time is led
Logical, the high level signal of second node N2 is transferred to first node N1, so that second transistor M2 can not be connected, scanning output end
OUT remains as high level.The interference to first node N1 is reduced as a result,.
And so on, when initial signal line IN keeps high level in a frame, scanning output end OUT persistently exports high electricity
It is flat.
In the present embodiment, by be arranged be made of the 6th transistor M6, the 7th transistor M7 and the second capacitor C2 it is anti-
Road is fed back to stablize the voltage of first node N1, to improve the anti-interference ability of the shift register 20, guarantees output
Stability.
If the initial signal that initial signal line IN is provided is high level, when the first of the first clock cable CLK1 offer
When clock signal by high level jump is low level, the 6th transistor M6 and the first transistor M1 conducting, first node N1 are high electricity
It is flat, while second node N2 is high level.Subsequent time, when the second clock signal that second clock signal wire CLK2 is provided is by height
When level jump is low level, since the source level that the grid of second transistor M2 is connect with second clock signal wire CLK2 exists
Parasitic capacitance can drag down the current potential of first node N1, so that second transistor M2 is connected, therefore scanning output end OUT output
High level can be pulled low.Since second node N2 is high level transistor, the 7th transistor M7 conducting, so that first node N1 is steady
It is scheduled on that high level is constant, so that influence of the coupling of parasitic capacitance to first node N1 is reduced, so that scanning output end
OUT keeps high level.
Referring to FIG. 4, its structural schematic diagram for the scanner driver of the embodiment of the present invention.As shown in figure 4, the scanning
Driver 200 includes: multiple shift registers as described above 20, and the multiple shift register 20 is in turn connected to form multistage
Structure, the multilevel structure is for being sequentially generated scanning signal.
Specifically, the multiple shift register 20 is in turn connected to form multilevel structure, the scanning output end OUT of every level-one
It is connect with a scanning output line, for successively providing the scanning signal to the scanning output line, previous stage shift LD
The scanning output line that device 20 is connected is connect with the input terminal of rear stage shift register 20.Wherein, the shift LD of the first order
The input terminal of device 20 is connect with initial signal line IN, for receiving initial signal, the shift register 20 to N grades of the second level
The input terminal of shift register 20 is connected respectively at the scanning output line of previous stage, successively receives 20 institute of previous stage shift register
Connection scanning output line output scanning signal, the multiple shift register 20 be sequentially generated scanning signal to scan output
Line S1 to SN.
As shown in figure 4, each shift register 20 with the first clock cable CLK1 and second clock signal wire CLK2
Connection, the first clock signal and second clock signal wire CLK2 that the first clock cable CLK1 is provided provide second when
Clock signal phase is opposite.
In the present embodiment, 20 circuit structure of shift register that the scanner driver 200 uses is simple, anti-interference ability
By force, and there is the feedback loop for stablizing first node N1 voltage can reduce parasitism when second clock signal jumps
Influence of the coupling of capacitor to first node N1, to improve the stability of the scanner driver 200.
Correspondingly, the present invention also provides a kind of organic light emitting displays.Organic light emitting display includes as described above
Scanner driver 200.It specifically please refers to above, details are not described herein again.
To sum up, in shift register provided by the invention, scanner driver and organic light emitting display, by shifting
One feedback loop is set to stablize the voltage of first node, to reduce the coupling of parasitic capacitance to first in register
The influence of node, improves the stability of scanner driver output, and then improves the display quality of organic light emitting display, and
And circuit structure is simple, strong antijamming capability.
Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of the scope of the invention, this hair
Any change, the modification that the those of ordinary skill in bright field does according to the disclosure above content, belong to the protection of claims
Range.
Claims (10)
1. a kind of shift register characterized by comprising
The first transistor is connected between first node and initial signal line, and grid is connected with the first clock cable；
Second transistor is connected between second clock signal wire and scanning output end, and grid is connected to first node；
Third transistor is connected between power supply high level and third node, and grid is connected to scanning output end；
4th transistor is connected between third node and power supply low level, and grid is connected with the first clock cable；
5th transistor is connected between power supply high level and scanning output end, and grid is connected to third node；
6th transistor is connected between second node and initial signal line, and grid is connected with the first clock cable；
7th transistor, is connected between first node and second node, and grid is connected with second clock signal wire；
First capacitor device, is connected between first node and scanning output end；
Second capacitor is connected between power supply high level and second node.
2. shift register as described in claim 1, which is characterized in that when first clock cable is for providing first
Clock signal, the second clock signal wire is for providing second clock signal, first clock signal and second clock signal
Opposite in phase.
3. shift register as described in claim 1, which is characterized in that the first transistor to the 7th transistor is P
Type thin film transistor (TFT).
4. shift register as claimed in claim 3, which is characterized in that the first transistor to the 7th transistor is two-way
PMOS tube or two-way P-type thin film transistor.
5. shift register as claimed in claim 4, which is characterized in that the scanning output end is connect with scanning output line,
Scanning signal is transmitted to scanning output line by scanning output end by the shift register.
6. a kind of scanner driver characterized by comprising multiple shift LDs as described in any one of claims 1 to 5
Device, the multiple shift register are in turn connected to form multilevel structure, and the multilevel structure is for being sequentially generated scanning signal.
7. scanner driver as claimed in claim 6, which is characterized in that in the multilevel structure, the scanning of every level-one is exported
End is connect with a scanning output line respectively, for successively providing the scanning signal to the scanning output line.
8. scanner driver as claimed in claim 7, which is characterized in that in the multilevel structure, the input terminal of the first order with
Initial signal line connection, for receiving initial signal；The input terminal of the second level to N grades respectively with the scanning output line of previous stage
Connection, for receiving the scanning signal of previous stage output.
9. scanner driver as claimed in claim 6, which is characterized in that the scanner driver passes through the first clock cable
The first clock signal and second clock signal, first clock signal and second clock are received respectively with second clock signal wire
The opposite in phase of signal.
10. a kind of organic light emitting display characterized by comprising the scanner driver as described in claim 6 to 9 is any.
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| CN201410811968.2A CN105788644B (en) | 2014-12-23 | 2014-12-23 | Shift register, scanner driver and organic light emitting display |
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| CN201410811968.2A CN105788644B (en) | 2014-12-23 | 2014-12-23 | Shift register, scanner driver and organic light emitting display |
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| CN105788644B true CN105788644B (en) | 2019-08-23 |
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108346397A (en) * | 2017-01-23 | 2018-07-31 | 昆山工研院新型平板显示技术中心有限公司 | Shift register, scanner driver and organic light emitting display |
| CN108665837B (en) * | 2017-03-27 | 2021-07-30 | 昆山工研院新型平板显示技术中心有限公司 | Scanning driving circuit, driving method thereof and flat panel display device |
| CN108665838A (en) * | 2017-03-27 | 2018-10-16 | 昆山工研院新型平板显示技术中心有限公司 | Scan drive circuit and its driving method and panel display apparatus |
| CN108806590B (en) * | 2017-04-28 | 2023-11-24 | 昆山国显光电有限公司 | Emission control driver and display device thereof |
| US10839751B2 (en) | 2018-01-19 | 2020-11-17 | Kunshan Go-Visionox Opto-Electronics Co., Ltd. | Scan driving circuit, scan driver and display device |
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