CN108346397A - Shift register, scanner driver and organic light emitting display - Google Patents
Shift register, scanner driver and organic light emitting display Download PDFInfo
- Publication number
- CN108346397A CN108346397A CN201710052133.7A CN201710052133A CN108346397A CN 108346397 A CN108346397 A CN 108346397A CN 201710052133 A CN201710052133 A CN 201710052133A CN 108346397 A CN108346397 A CN 108346397A
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- Prior art keywords
- transistor
- node
- high level
- shift register
- clock signal
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
Abstract
The present invention discloses a kind of shift register, scanner driver and organic light emitting display, register：The first transistor, is connected to first node and initial signal input terminal, and grid is connected with the first clock cable；Second transistor, is connected to second clock signal wire and scanning output end, and grid connects first node；Third transistor, is connected to power supply high level and second node, and grid connects first node；4th transistor, is connected to second node and power supply low level, and grid is connected with the first clock cable；5th transistor, is connected to power supply high level and scanning output end, and grid connects second node；6th transistor, is connected to third transistor and power supply high level, and grid is connected with second clock signal wire；First capacitor, is connected to first node and scanning output end；Second capacitor is connected to first node and power supply high level.In shift register when the threshold voltage negative sense drift of transistor, shift register remains to output low level.
Description
Technical field
The present invention relates to field of display devices, more particularly to a kind of shift register, scanner driver and organic light emission are aobvious
Show device.
Background technology
Organic light emitting display utilizes Organic Light Emitting Diode (full name in English Organic Lighting Emitting
Diode, abbreviation OLED) display image, it is a kind of display that active is luminous, is not necessarily to backlight, moreover, has contrast
Height, fast response time, it is frivolous many advantages, such as.Therefore, organic light emitting display is known as that tft liquid crystal can be replaced
The display of a new generation of display.
Existing organic light emitting display includes：The pel array being connect with data line and scan line；To the data line
The data driver of data-signal is provided；The scanner driver of scanning signal is provided to the scan line；To the turntable driving
Device provides the sequence drivers of clock signal.
Wherein, existing scanner driver generally includes multiple transistors, initial signal input terminal IN, clock cable
CLK1, CLK2, power supply high level VGH and power supply low level VGL lead to transistor due to the limitation of transistor fabrication processes
Threshold voltage variation is partially negative, this can make scanner driver that can not export normal low level, can not output a signal to pixel
The scanner driver of unit and next line, the final body that shields can not normally be shown.
Invention content
The purpose of the embodiment of the present invention is to provide a kind of shift register, scanner driver and organic light emitting display, with
It solves the above problems.
In order to solve the above technical problems, the embodiment of the present invention provides a kind of shift register, including：
The first transistor is connected between first node and initial signal input terminal, grid and the first clock cable
It is connected；
Second transistor is connected between second clock signal wire and scanning output end, and grid is connected to first node；
Third transistor is connected between power supply high level and second node, and grid is connected to the first node；
4th transistor is connected between the second node and power supply low level, and grid is believed with first clock
Number line is connected；
5th transistor is connected between power supply high level and scanning output end, and grid is connected to the second node；
6th transistor is connected between the third transistor and power supply high level, grid and second clock signal
Line is connected；
First capacitor is connected between the first node and scanning output end；
Second capacitor is connected between the first node and power supply high level.
Preferably, what the first clock signal and second clock signal wire that first clock cable is provided were provided
The opposite in phase of second clock signal.
Preferably, high level, second clock signal are become from low level in the initial signal and the first clock signal
When becoming low level from high level, the scanning output end exports low level.
Preferably, low level, second clock signal are become by low from high level in initial signal and the first clock signal
Level becomes high level, and the scanning output end exports high level.
Preferably, the first transistor to the 6th transistor is P-type TFT.
Preferably, the first transistor to the 6th transistor is that two-way PMOS tube or two-way P-type thin film field-effect are brilliant
Body pipe.
Preferably, the quantity of the shift register is multiple, and the multiple shift register is in turn connected into multistage knot
Structure, the multilevel hierarchy can be sequentially generated scanning signal.
In order to solve the above technical problems, the embodiment of the present invention provides a kind of scanner driver, including：Such as foregoing summary
The shift register.
In order to solve the above technical problems, the embodiment of the present invention provides a kind of organic light emitting display, including：Such as aforementioned invention
Scanner driver described in content.
By the above technical solution provided in an embodiment of the present invention as it can be seen that the embodiment of the present invention provided shift register,
Using the organic light emitting display of the scanner driver and application of the shift register scanner driver, by being posted in displacement
6th transistor M6 is set in storage between third transistor M3 and power supply high level VGH, before second transistor M2 is switched on,
So that second node N2 is raised into high level, when effectively solving the threshold voltage negative sense drift of transistor in shift register,
Shift register can not stablize the low level problem of output.
Description of the drawings
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technology description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments described in invention, for those of ordinary skill in the art, in the premise of not making the creative labor property
Under, other drawings may also be obtained based on these drawings.
Fig. 1 is the circuit diagram of shift register in the embodiment of the present invention.
Fig. 2 is sequence diagram of the shift register in a frame in the embodiment of the present invention.
Specific implementation mode
In order to make those skilled in the art more fully understand the technical solution in the present invention, below in conjunction with of the invention real
The attached drawing in example is applied, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described implementation
Example is only a part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, this field is common
The every other embodiment that technical staff is obtained without making creative work, should all belong to protection of the present invention
Range.
Fig. 1 is the circuit diagram of shift register in the embodiment of the present invention.Join shown in Fig. 1, the shift register 10 includes
Initial signal input terminal IN, scanning output end OUT, the first clock cable CLK1 and second clock signal wire CLK2.
In practical applications, multilevel hierarchy can be formed by several aforementioned shift registers, which can be according to
Secondary generation scanning signal, the multilevel hierarchy can be applied in the scanner driver in organic light emitting display.
In the embodiment of the present invention, initial signal input terminal IN is for receiving initial signal, scanning output end OUT and display
Interior scan line connection, scan line is transmitted to by scanning signal.First clock cable CLK1 and second clock signal wire CLK2
For receiving clock signal, and on the first clock cable CLK1 and second clock signal wire CLK2 clock signal phase phase
Instead.
Wherein, shift register further includes the first transistor M1 to the 6th transistor M6 and the first capacitance C1 and the second electricity
Hold C2.The first transistor M1 to the 6th transistor M6 is P-type TFT, it is preferred that these transistors are two-way
PMOS tube or two-way P-type thin film field effect transistor.
First capacitor C1 is connected between first node N1 and scanning output end OUT；Second capacitor C2 is connected to
Between one node N1 and power supply high level VGH.
The first transistor M1 is connected between first node N1 and initial signal input terminal IN, the source electrode of the first transistor M1
First node N1 is connected with one in drain electrode, another in the source electrode and drain electrode of the first transistor M1 connects initial signal input terminal
IN, the grid of the first transistor M1 are connected with the first clock cable.
Second transistor M2 is connected between second clock signal wire CLK2 and scanning output end OUT, second transistor M2
Source electrode and drain electrode in a connection second clock signal wire CLK2, another in the source electrode and drain electrode of second transistor M2 connect
The grid of scanning output end OUT, second transistor M2 are connected to first node N1.
Third transistor M3 is connected between power supply high level VGH and second node N2, the source electrode of third transistor M3 and
One connects power supply high level VGH in drain electrode, another in the source electrode and drain electrode of third transistor M3 connects second node N2, the
The grid of three transistor M3 is connected to the first node N1.
4th transistor M4 is connected between the second node N2 and power supply low level VGL, the source of the 4th transistor M4
One connects second node N2 in pole and drain electrode, another in the source electrode and drain electrode of the 4th transistor M4 connects power supply low level
VGL, the grid of the 4th transistor M4 are connected with the first clock cable CLK1.
5th transistor M5 is connected between power supply high level VGH and scanning output end OUT, the source electrode of the 5th transistor M5
Power supply high level VGH is connected with one in drain electrode, another in the source electrode and drain electrode of the 5th transistor M5 connects scanning output end
The grid of OUT, the 5th transistor M5 are connected to the second node N2.
6th transistor M6 is connected between the third transistor M3 and power supply high level VGH, the 6th transistor M6's
The source electrode of connection third transistor M3 or drain electrode in source electrode and drain electrode, another in the source electrode and drain electrode of the 6th transistor M6
The grid of power supply high level VGH, the 6th transistor M6 are connected with second clock signal wire CLK2.
Fig. 2 is sequence diagram of the shift register in a frame in the embodiment of the present invention.Join shown in Fig. 2, packet in the sequence diagram
Include the sequence diagram of initial signal in initial signal input terminal IN, the first clock signal that the first clock cable CLK1 is provided and
The scanning letter that the sequence diagram and scanning output end OUT for the second clock signal that second clock signal wire CLK2 is provided are exported
Number sequence diagram.
Wherein, the initial signal that initial signal input terminal IN is provided keeps high level, the first clock signal in a frame
The phase for the second clock signal that the first clock signal and second clock signal wire CLK2 that line CLK1 is provided are provided is just
On the contrary, when i.e. the first clock signal is high level, second clock signal is then low level or the first clock signal is low level
When, second clock signal is then high level.
The operation principle and its technology of shift register shown in FIG. 1 are described in detail below in conjunction with sequence diagram shown in Fig. 2
Effect.
First stage：Initial signal and the first clock signal become low level, second clock signal by low from high level
Level becomes high level.At this point, the first transistor M1 and the 4th transistor M4 is switched on, the 6th transistor M6 is ended.
Within this stage, since the 6th transistor M6 is ended and the conducting of the 4th transistor M4, second node N2 will not
It is influenced by power supply high level VGH, the low level signal of power supply low level VGL can be transmitted to second node N2 so that the 5th
Transistor M5 be switched on, and then power supply high level VGH on high level signal can be also transmitted to by the 5th transistor M5 scan it is defeated
Outlet OUT.
Simultaneously as the conducting of the first transistor M1, low level signal is transmitted to first segment in initial signal input terminal IN
Point N1 so that second transistor M2 is switched on, and the clock signal of high level can pass through the second crystalline substance on second clock signal wire CLK2
Body pipe M2 is transmitted to scanning output end OUT, it is made to maintain high level.
Second stage：Initial signal and the first clock signal become high level, second clock signal by height from low level
Level becomes low level.At this point, the first transistor M1 and the 4th transistor M4 are ended, the 6th transistor M6 is switched on.
In this stage, since the first transistor M1 ends, low level signal can be simultaneously so that second is brilliant on first node N1
Body pipe M2 and third transistor M3 is switched on, and high level signal can pass through the 6th transistor M6 and third on power supply high level VGH
Transistor M3 is transferred to second node N2 so that second node N2 is raised, so that the 5th transistor M5 is ended in advance；
Subsequently, after second clock signal wire CLK2 becomes low level, low level signal can be transmitted to scanning output end OUT.
By the way that the 6th transistor M6 is arranged so that scanning output end OUT can export low level, in the prior art will avoid
Second node N2 is connected to following problem caused by the grid of scanning output end OUT：Second node N2 delays, which are drawn high, makes the 5th crystalline substance
Body pipe M5 conductings so that scanning output end OUT there is also high level of interference, influence low level output effect.
In this stage, pass through the coupling of the first capacitance C1 and the second capacitance C2, the electricity of the grid of second transistor M2
Pressure is reduced with the voltage synchronous of the drain electrode of second transistor M2 so that second transistor M2 can be tended to remain on and be stablized
Low level signal is exported to scanning output end, to realize output purpose.
Phase III：Initial signal maintains high level, the first clock signal to become low level, second clock letter from high level
Number high level is become from low level.At this point, the first transistor M1 and the 4th transistor M4 is switched on, the 6th transistor M6 is cut
Only.
This stage is consistent with the operation principle of first stage, and the 6th transistor M6 is ended and the 4th transistor M4 is led
Logical, second node N2 will not be influenced by power supply high level VGH, and the low level signal of power supply low level VGL can be transmitted to the
Two node N2 so that the 5th transistor M5 is switched on, and then high level signal can also pass through the 5th crystal on power supply high level VGH
Pipe M5 is transmitted to scanning output end OUT.
Simultaneously as the conducting of the first transistor M1, low level signal is transmitted to first segment in initial signal input terminal IN
Point N1 so that second transistor M2 is switched on, and the clock signal of high level can pass through the second crystalline substance on second clock signal wire CLK2
Body pipe M2 is transmitted to scanning output end OUT, it is made to maintain high level.
To sum up, the embodiment of the present invention is provided shift register, using the shift register scanner driver and
Using the organic light emitting display of the scanner driver, pass through the third transistor M3 in shift register and power supply high level
6th transistor M6 is set between VGH, before second transistor M2 is switched on so that second node N2 is raised into high level,
When effectively solving the threshold voltage negative sense drift of transistor in shift register, it is low level that shift register can not stablize output
Problem so that display can normally be shown.
Each embodiment in this specification is described in a progressive manner, identical similar portion between each embodiment
Point just to refer each other, and each embodiment focuses on the differences from other embodiments.Especially for system reality
For applying example, since it is substantially similar to the method embodiment, so description is fairly simple, related place is referring to embodiment of the method
Part explanation.
Example the above is only the implementation of the present invention is not intended to restrict the invention.For those skilled in the art
For, the invention may be variously modified and varied.It is all within spirit and principles of the present invention made by any modification, equivalent
Replace, improve etc., it should be included within scope of the presently claimed invention.
Claims (9)
1. a kind of shift register, which is characterized in that including：
The first transistor is connected between first node and initial signal input terminal, and grid is connected with the first clock cable；
Second transistor is connected between second clock signal wire and scanning output end, and grid is connected to first node；
Third transistor is connected between power supply high level and second node, and grid is connected to the first node；
4th transistor is connected between the second node and power supply low level, grid and first clock cable
It is connected；
5th transistor is connected between power supply high level and scanning output end, and grid is connected to the second node；
6th transistor is connected between the third transistor and power supply high level, grid and second clock signal wire phase
Even；
First capacitor is connected between the first node and scanning output end；
Second capacitor is connected between the first node and power supply high level.
2. shift register as described in claim 1, which is characterized in that first clock cable provided first when
The opposite in phase for the second clock signal that clock signal and second clock signal wire are provided.
3. shift register as claimed in claim 2, which is characterized in that the initial signal and the first clock signal by
When low level becomes high level, second clock signal becomes low level from high level, the scanning output end exports low level.
4. shift register as claimed in claim 3, which is characterized in that in initial signal and the first clock signal by high electricity
It is flat become low level, second clock signal becomes high level from low level, the scanning output end exports high level.
5. shift register as described in claim 1, which is characterized in that the first transistor to the 6th transistor is P
Type thin film transistor (TFT).
6. shift register as described in claim 1, which is characterized in that the first transistor to the 6th transistor is double
To PMOS tube or two-way P-type thin film field effect transistor.
7. a kind of scanner driver, which is characterized in that the scanner driver includes as described in any one of claim 1 to 6
Shift register.
8. scanner driver as claimed in claim 7, which is characterized in that the quantity of the shift register be it is multiple, it is described
Multiple shift registers are in turn connected into multilevel hierarchy, which can be sequentially generated scanning signal.
9. a kind of organic light emitting display, which is characterized in that the organic light emitting display includes sweeping as claimed in claim 8
Retouch driver.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710052133.7A CN108346397A (en) | 2017-01-23 | 2017-01-23 | Shift register, scanner driver and organic light emitting display |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710052133.7A CN108346397A (en) | 2017-01-23 | 2017-01-23 | Shift register, scanner driver and organic light emitting display |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108346397A true CN108346397A (en) | 2018-07-31 |
Family
ID=62974657
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710052133.7A Pending CN108346397A (en) | 2017-01-23 | 2017-01-23 | Shift register, scanner driver and organic light emitting display |
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| Country | Link |
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| CN (1) | CN108346397A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020038346A1 (en) * | 2018-08-21 | 2020-02-27 | 京东方科技集团股份有限公司 | Shift register unit and drive method therefor, gate drive circuit, and display apparatus |
| CN114333684A (en) * | 2021-12-28 | 2022-04-12 | 昆山国显光电有限公司 | Shift register, gate drive circuit and drive method of shift register |
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| CN102831861A (en) * | 2012-09-05 | 2012-12-19 | 京东方科技集团股份有限公司 | Shifting register, drive method thereof, gate driver and display device |
| CN104751776A (en) * | 2013-12-27 | 2015-07-01 | 昆山工研院新型平板显示技术中心有限公司 | Grid scanning circuit, scanning driver and organic light emitting display |
| CN204680361U (en) * | 2015-02-15 | 2015-09-30 | 信利（惠州）智能显示有限公司 | A kind of GOA array base palte horizontal drive circuit |
| CN105788644A (en) * | 2014-12-23 | 2016-07-20 | 昆山工研院新型平板显示技术中心有限公司 | Shift register, scan driver and organic light-emitting display |
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2017
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Patent Citations (4)
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| CN102831861A (en) * | 2012-09-05 | 2012-12-19 | 京东方科技集团股份有限公司 | Shifting register, drive method thereof, gate driver and display device |
| CN104751776A (en) * | 2013-12-27 | 2015-07-01 | 昆山工研院新型平板显示技术中心有限公司 | Grid scanning circuit, scanning driver and organic light emitting display |
| CN105788644A (en) * | 2014-12-23 | 2016-07-20 | 昆山工研院新型平板显示技术中心有限公司 | Shift register, scan driver and organic light-emitting display |
| CN204680361U (en) * | 2015-02-15 | 2015-09-30 | 信利（惠州）智能显示有限公司 | A kind of GOA array base palte horizontal drive circuit |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020038346A1 (en) * | 2018-08-21 | 2020-02-27 | 京东方科技集团股份有限公司 | Shift register unit and drive method therefor, gate drive circuit, and display apparatus |
| US11127326B2 (en) | 2018-08-21 | 2021-09-21 | Hefei Xinsheng Optoelectronics Technology Co., Ltd. | Shift register unit, method for driving shift register unit, gate drive circuit, and display device |
| CN114333684A (en) * | 2021-12-28 | 2022-04-12 | 昆山国显光电有限公司 | Shift register, gate drive circuit and drive method of shift register |
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