CN105786722A - NVM erasing and writing control method and system based on heterogeneous hybrid memory - Google Patents
NVM erasing and writing control method and system based on heterogeneous hybrid memory Download PDFInfo
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Abstract
The invention provides a NVM erasing and writing control method based on a heterogeneous hybrid memory. The method comprises the following steps of: obtaining a NVM page erasing and writing time recording table, wherein the page serial number of a NVM and the corresponding erasing and writing time are recorded in the NVM page erasing and writing time recording table; according to the NVM page erasing and writing time recording table, operating the erasing and writing time corresponding to the page serial number of the NVM by adopting a balancing algorithm so as to obtain the operation value of the erasing and writing time; and writing data in the NVM according to the page of the NVM, the page serial number of which is the operation value. Because the balancing algorithm can ensure that the selection times of all pages of the NVM are relatively random and average, the erasing and writing times of different storage units of the NVM are controlled; the service lives of various storage units are relatively average; and the invention further provides a NVM erasing and writing control system based on the heterogeneous hybrid memory.
Description
Technical field
The present invention relates to field of computer technology, particularly relate to a kind of erasable control method of NVM internal memory based on isomery mixing internal memory and system.
Background technology
Along with the emerging non-volatile random storage medium (Non-VolatileMemory that Memister, ferroelectric memory, phase transition storage etc. are representative, NVM) development of technology, advancing the development of memory technology, the generation for novel internal memory Yu storage architecture is laid a good foundation.By novel NVM and dynamic RAM (DynamicRandomAccessMemory, DRAM) are combined, build mixing memory architecture, form isomery mixing internal memory.Isomery mixing internal memory has the feature of NVM and DRAM simultaneously, not only possesses the function of conventional memory, is stored in the data in DRAM and can disappear immediately after a loss of power, is volatibility；Can also play NVM can also preserve the advantage of data after a loss of power simultaneously, gives full play to the non-volatile feature of NVM, is a kind of Novel internal memory mixing use.
Isomery mixing internal memory meets the conventional memory interface of existing industrial control equipment, it is not necessary to introduces new industrial control equipment or adds new auxiliary equipment, becoming a study hotspot.
NVM and DRAM characteristic in isomery mixing internal memory is different, there is the conditional birth defect of erasable total degree in NVM, after reaching certain erasable number of times, NVM will lose efficacy, so the service life of NVM is limited, service life is determined by maximum erasable number of times, having exceeded maximum erasable number of times, this erasable unit just becomes bad block, it is impossible to normally employ.Conventional erasable control method is for DRAM internal memory, owing to DRAM does not have the restriction of erasable total degree, so the erasable control method of routine is not suitable for the NVM internal memory in isomery mixing internal memory.
Summary of the invention
Based on this, it is necessary to for the problems referred to above, it is provided that a kind of erasable control method of NVM internal memory based on isomery mixing internal memory and system, controlling the erasable number of times between NVM difference memory element, so as to relatively balanced, the life-span making each memory element is average.
A kind of erasable control method of NVM internal memory based on isomery mixing internal memory, described method includes:
Obtain the erasable number of times log of the NVM page, the described NVM page erasable number of times log have recorded the page sequence number of NVM internal memory and corresponding erasable number of times；
According to the erasable number of times log of the NVM page, adopt equalization algorithm that the erasable number of times that the page sequence number of described NVM internal memory is corresponding is carried out computing, obtain the operation values of described erasable number of times；
The page according to the NVM internal memory that described page sequence number is described operation values, writes data in NVM internal memory.
Wherein in an embodiment, described method also includes:
When start powers on, copy the erasable number of times log of the described NVM page in NVM internal memory to DRAM relief area；
Whenever having after in data write NVM internal memory, erasable for the NVM page of described DRAM relief area number of times log is updated；
Before shutdown or power down, erasable for the NVM page of described renewal number of times log is saved in NVM internal memory.
Wherein in an embodiment, after the described step that erasable for the NVM page in NVM internal memory number of times log is copied to DRAM relief area, also include:
Erasable for the NVM page in DRAM relief area number of times log is copied in DRAM internal memory.
Wherein in an embodiment, the described step obtaining the erasable number of times log of the NVM page includes:
Obtain the address mapping relation of the erasable number of times log of the NVM page；
The storage position of the erasable number of times log of the NVM page is obtained according to described address mapping relation；
The erasable number of times log of the described NVM page is read from described storage position.
Wherein in an embodiment, described according to the erasable number of times log of the NVM page, adopt equalization algorithm that the erasable number of times that the page sequence number of described NVM internal memory is corresponding is carried out computing, the step of the operation values obtaining described erasable number of times is:
Carry out Hash operation after being weighted by erasable number of times corresponding for the page sequence number of described NVM internal memory, obtain cryptographic Hash；
Obtain the page number that the available storage of NVM internal memory is corresponding；
Described cryptographic Hash is carried out complementation with described corresponding page number, obtains the operation values of described erasable number of times.
Wherein in an embodiment, the described page according to the NVM internal memory that described page sequence number is described operation values, the step write data in NVM internal memory includes:
Judge whether the page of the NVM internal memory that page sequence number is described operation values exists free space, if it is, write data into described free space, otherwise described operation values is added with default value, obtains intermediate value；
S1: judge whether the page of the NVM internal memory that page sequence number is described intermediate value exists free space, if it is, write data into described free space；Otherwise, determining whether whether described intermediate value exceedes maximum page sequence number, if not having, then continuing to be added with described default value by described intermediate value, repeated execution of steps S1；
S2: if described intermediate value exceedes maximum page sequence number, then judge whether the page corresponding to described maximum page sequence number exists free space, if existed, then write data into the free space of the page corresponding to described maximum page sequence number, otherwise obtain the page that there is free space in NVM internal memory, write data in the described page.
A kind of erasable control system of the NVM internal memory based on isomery mixing internal memory, described system includes:
Acquisition module, is used for obtaining the erasable number of times log of the NVM page, have recorded the page sequence number of NVM internal memory and corresponding erasable number of times in the described NVM page erasable number of times log；
Computing module, for according to the erasable number of times log of the NVM page, adopting equalization algorithm that the erasable number of times that the page sequence number of described NVM internal memory is corresponding is carried out computing, obtain the operation values of described erasable number of times；
Writing module, for the page according to the NVM internal memory that described page sequence number is described operation values, writes data in NVM internal memory.
Wherein in an embodiment, described system also includes:
First copy module, for when start powers on, copying the erasable number of times log of the described NVM page in NVM internal memory to DRAM relief area；
More new module, for whenever having after in data write NVM internal memory, updating erasable for the NVM page of described DRAM relief area number of times log；
Preserve module, for, before shutdown or power down, being saved in NVM internal memory by erasable for the NVM page of described renewal number of times log.
Wherein in an embodiment, described system also includes:
Second copy module, for copying to erasable for the NVM page in DRAM relief area number of times log in DRAM internal memory.
Wherein in an embodiment, described acquisition module is additionally operable to obtain the address mapping relation of the erasable number of times log of the NVM page；The storage position of the erasable number of times log of the NVM page is obtained according to described address mapping relation；The erasable number of times log of the described NVM page is read from described storage position.
Wherein in an embodiment, described computing module includes:
Hash operation unit, for carrying out Hash operation after being weighted by erasable number of times corresponding for the page sequence number of described NVM internal memory, obtains cryptographic Hash；
Acquiring unit, the page number corresponding for obtaining the available storage of NVM internal memory；
Complementation unit, for described cryptographic Hash is carried out complementation with described corresponding page number, obtains the operation values of described erasable number of times.
Wherein in an embodiment, whether the page of the NVM internal memory that said write module is additionally operable to judge that page sequence number is described operation values exists free space, if it is, write data into described free space, otherwise described operation values is added with default value, obtains intermediate value；And perform:
S1: judge whether the page of the NVM internal memory that page sequence number is described intermediate value exists free space, if it is, write data into described free space；Otherwise, determine whether whether described intermediate value exceedes maximum page sequence number, if not having, then continue to be added with described default value by described intermediate value, repeat S1；
S2: if described intermediate value exceedes maximum page sequence number, then judge whether the page corresponding to described maximum page sequence number exists free space, if existed, then write data into the free space of the page corresponding to described maximum page sequence number, otherwise obtain the page that there is free space in NVM internal memory, write data in the described page.
The above-mentioned erasable control method of NVM internal memory based on isomery mixing internal memory and system, by obtaining the erasable number of times log of the NVM page, have recorded the page sequence number of NVM internal memory and corresponding erasable number of times in described log；With employing equalization algorithm, the erasable number of times that the page sequence number of NVM internal memory is corresponding is carried out computing according to the NVM page erasable number of times log, obtain the operation values of erasable number of times；The page according to the NVM internal memory that described page sequence number is described operation values, writes data in NVM internal memory.Owing to equalization algorithm can ensure that the selected number of times of all pages of NVM is relatively random on average, thus the erasable number of times controlled between NVM difference memory element, so as to relatively balanced, the life-span making each memory element is average.
Accompanying drawing explanation
Fig. 1 is the flow chart of the erasable control method of NVM internal memory in an embodiment based on isomery mixing internal memory；
Fig. 2 is the schematic diagram of the erasable number of times log of the NVM page in an embodiment；
Fig. 3 is the flow chart preserving the erasable number of times log of the NVM page in another embodiment；
Fig. 4 is the structural representation of isomery mixing internal memory in an embodiment；
Fig. 5 is the schematic diagram of the erasable number of times log of the NVM page updated in an embodiment；
Fig. 6 is the flow chart obtaining the erasable number of times log of the NVM page in an embodiment；
Fig. 7 is the flow chart that erasable number of times carries out in an embodiment computing；
Fig. 8 is the schematic diagram of the erasable number of times log of the NVM page in another embodiment；
Fig. 9 is the flow chart writing data into NVM internal memory in an embodiment；
Figure 10 is the structured flowchart in an embodiment based on the erasable control system of the NVM internal memory of isomery mixing internal memory；
Figure 11 is the structured flowchart in another embodiment based on the erasable control system of the NVM internal memory of isomery mixing internal memory；
Figure 12 is the structured flowchart in further embodiment based on the erasable control system of the NVM internal memory of isomery mixing internal memory；
Figure 13 is the structured flowchart of computing module in an embodiment.
Detailed description of the invention
In order to make the purpose of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein is only in order to explain the present invention, is not intended to limit the present invention.
In one embodiment, as shown in Figure 1, it is provided that a kind of erasable control method of NVM internal memory based on isomery mixing internal memory, the method includes:
Step S110, obtains the erasable number of times log of the NVM page, have recorded the page sequence number of NVM internal memory and corresponding erasable number of times in this NVM page erasable number of times log.
In the present embodiment, it is that unit carries out paging by NVM internal memory according to default physical page, a page sequence number is distributed for each page after paging, the page corresponding to page sequence number has data to write, then erasable number of times corresponding for page sequence number is updated, the NVM page erasable number of times log have recorded all page sequence numbers of NVM internal memory and corresponding erasable number of times.Size such as each physical page is defaulted as 4KB, NVM total amount of memory is 1M, then there are 256 pages after paging, a page sequence number 0-255 is distributed for each page, and record the erasable number of times that each page sequence number is corresponding, the erasable number of times of the page of original NVM internal memory is labeled as 0, often writes the page of a NVM internal memory, and corresponding erasable number of times adds 1.As in figure 2 it is shown, be an erasable number of times log of the NVM page.
Step S120, according to the erasable number of times log of the NVM page, adopts equalization algorithm that the erasable number of times that the page sequence number of NVM internal memory is corresponding is carried out computing, obtains the operation values of described erasable number of times.
In the present embodiment, equalization algorithm refers to the algorithm making result of calculation stochastic averagina as far as possible be distributed, it is possible to select suitable equalization algorithm as required, then based on equalization algorithm, erasable number of times corresponding for the page sequence number of NVM internal memory is carried out computing.As the combining form of Roundrobin (polling dispatching) algorithm, Hash (Hash) algorithm, CARP (CommonAccessRedundancyProtocol, shared address redundancy protocol) algorithm, Consistenthash (concordance Hash) algorithm etc. or several algorithm can be adopted to realize equalization algorithm.It is understood that before carrying out computing, first erasable for NVM page number of times log can be sorted from small to large or from big to small according to erasable number of times, the page sequence number of easy-to-look-up maximum erasable number of times and minimum erasable number of times and its correspondence.
Concrete, when adopting Roundrobin algorithm, find page sequence number that minimum erasable number of times is corresponding as the operation values of erasable number of times.When adopting hash algorithm, it is possible to all or part of erasable number of times in the NVM page erasable number of times log is carried out Hash operation, obtains cryptographic Hash, then by cryptographic Hash and page sum remainder, using operation values as erasable number of times of the value that obtains after remainder.When adopting CARP algorithm, the data of the page corresponding to erasable number of times corresponding for the page sequence number of NVM internal memory and same page sequence number being write mark and is added, the value after will add up carries out MD5 (message digest algorithm) computing, obtains the value after computing.If the erasable number of times needing the page sequence number carrying out the NVM internal memory of computing corresponding has multiple, then carry out above-mentioned computing respectively and obtain multiple operation result, using the page sequence number of NVM internal memory corresponding for value maximum in the operation result operation values as erasable number of times.It is understood that wherein data write mark can be self-defined, as represented no data write with " 0 ", indicate that data write with " 1 ".When adopting Consistenthash algorithm, it is possible to first obtain the cryptographic Hash of erasable number of times corresponding to the page sequence number of each NVM internal memory, and be configured on the circle of 0～2^32.Then the cryptographic Hash of available storage corresponding to the page sequence number of each NVM internal memory is obtained by same method, and it is mapped on circle, then the position being mapped to from data starts lookup clockwise, using the page sequence number corresponding for first the erasable number of times the found operation values as erasable number of times, if it exceeds 2^32 still can not find erasable number of times, then using the page sequence number of the minimum NVM internal memory operation values as erasable number of times.
Step S130, the page according to the NVM internal memory that page sequence number is described operation values, write data in NVM internal memory.
In the present embodiment, the actual storage situation of the page according to the NVM internal memory that page sequence number is operation values, high priority data is write the page of the NVM internal memory that page sequence number is operation values, when the page of the NVM internal memory that page sequence number is operation values is absent from free space, then detect whether other page adjacent with this page exists free space one by one according to the order of page sequence number, and write data in the page that there is free space.It is understood that before write data, the residual capacity of NVM internal memory has been added up, corresponding data write request when only NVM internal memory existing free space, just can be sent.
In the present embodiment, by obtaining the erasable number of times log of the NVM page, described log have recorded the page sequence number of NVM internal memory and corresponding erasable number of times；With employing equalization algorithm, the erasable number of times that the page sequence number of NVM internal memory is corresponding is carried out computing according to the NVM page erasable number of times log, obtain the operation values of erasable number of times；The page according to the NVM internal memory that page sequence number is operation values, writes data in NVM internal memory.Owing to equalization algorithm can ensure that the selected number of times of all pages of NVM is relatively random on average, thus the erasable number of times controlled between NVM difference memory element, so as to relatively balanced, the life-span making each memory element is average.
In one embodiment, as it is shown on figure 3, described method also includes:
Step S210, when start powers on, copies erasable for the NVM page in NVM internal memory number of times log to DRAM relief area.
In the present embodiment, isomery mixing internal memory can be made up of structure as shown in Figure 4, and including NVM-DRAM mixing module 410 and DRAM internal memory 420, wherein NVM-DRAM mixing module 410 includes NVM internal memory 411 and DRAM relief area 412.Wherein the read or write speed of DRAM relief area 412 is faster than the read or write speed of NVM internal memory 411, when start powers on, copy erasable for the NVM page in NVM internal memory 411 number of times log to DRAM relief area 412, read-write efficiency can be improved on the one hand, on the other hand will not the erasable number of times of loss NVM internal memory 411 too much.
Step S220, whenever having after in data write NVM internal memory, updates erasable for the NVM page of DRAM relief area number of times log.
In the present embodiment, all of erasable number of times amendment action is all performed in DRAM relief area 412 by controller, often writes NVM page area specified, and the corresponding erasable number of times that page sequence number is corresponding page area is updated.Controller is a control unit within NVM-DRAM mixing module 410, it is possible to controls NVM-DRAM mixing module 410, and communicates with other module outside.As updated the erasable number of times log of the front NVM page as in figure 2 it is shown, data are written with the page that page sequence number is 1, then corresponding erasable number of times adds 1, and the erasable number of times log of the NVM page after renewal is as shown in Figure 5.
Step S230, before shutdown or power down, is saved in erasable for the NVM page of renewal number of times log in NVM internal memory.
In the present embodiment, owing to DRAM relief area 412 is the internal memory of DRAM medium, it is stored in the data in DRAM and can disappear immediately after a loss of power, be volatibility, and NVM internal memory is non-volatile, data can also be preserved after a loss of power.So before shutdown or power down, the erasable number of times log of the NVM page updated in DRAM relief area is written back in NVM internal memory by NVM controller, and data will not be lost, in order to the erasable number of times log of the NVM page of renewal can be used after start next time.
In one embodiment, after erasable for the NVM page in NVM internal memory number of times log is copied to the step of DRAM relief area, also include: erasable for the NVM page in DRAM relief area number of times log is copied in DRAM internal memory.
In the present embodiment, although DRAM relief area and DRAM internal memory are all belonging to DRAM granule, same class DRAM granule read or write speed is the same or close, but owing to external logic design difference result in a certain main controller, their access speed, time delay is had any different.Such as it is divided into the DDR3 interface exchange data of two timeslices, one of them timeslice and CPU end, the swapping data of another timeslice and NVM during the work of DRAM relief area；And DRAM internal memory All Time all can exchange data with CPU, and CPU accesses the DRAM relief area in NVM-DRAM mixing module and also needs to through controller unit dereference (can not directly access), therefore the speed of CPU access DRAM internal memory is than accessing DRAM relief area faster.In order to improve work efficiency, system drive layer can regularly give an order when management and be copied in DRAM internal memory by erasable for the NVM page in DRAM relief area number of times log to CPU, CPU.The time of timing can be self-defined, such as 10 minutes copies once.Wherein system drive layer refers to system drive code, is a part for operation system image, and CPU calling system drives layer that isomery mixing internal memory is managed.When system drive layer copies erasable for NVM page number of times log after in DRAM internal memory to, just can directly read from DRAM internal memory if other program needs to use the erasable number of times log of the NVM page.System drive layer and other program only read the authority of the erasable number of times log of the NVM page in DRAM internal memory, without the authority rewritten.
In one embodiment, as shown in Figure 6, step S110 includes:
Step S111, obtains the address mapping relation of the erasable number of times log of the NVM page.
In the present embodiment, address mapping relation is stored in isomery mixing internal memory as the information of controller, as isomery mixing internal storage structure be as shown in Figure 4 time, it is possible to be stored in the first 4K address space of NVM-DRAM mixing module 410.When the first 4K address space of the corresponding isomery mixing memory bar of system drive layer read-write, controller by first 4K Address space mappinD to control command region, just directly can obtain the information of controller from control command region after so.Wherein control command region is one piece of region in virtual address space, whether whether the information of controller refers to the work state information of NVM-DRAM mixing module 410, busy including controller, allow to read data, whether allow the address mapping relation etc. of the erasable number of times log of write data, the NVM page.Address mapping relation refers to the mapping relations of virtual address space and physical address space, it is possible to find the actual storage locations of the erasable number of times log of the NVM page according to address mapping relation.
Step S112, obtains the storage position of the erasable number of times log of the NVM page according to described address mapping relation.
In the present embodiment, when CPU calling system drives layer that isomery mixing internal memory is managed or other program needs the erasable number of times log of the use NVM page, first obtain the address mapping relation of the erasable number of times log of the NVM page, then the physical address space corresponding with virtual address space is found according to address mapping relation, thus finding the actual storage locations of the erasable number of times log of the NVM page.
Step S113, reads the erasable number of times log of the NVM page from described storage position.
In the present embodiment, have found the actual storage locations of the erasable number of times log of the NVM page, it is possible to directly read the erasable number of times log of the NVM page from described storage position.In one embodiment, as it is shown in fig. 7, describe the process that erasable number of times carries out computing in detail with hash algorithm, then step S120 includes:
Step S121, carries out Hash operation after being weighted by erasable number of times corresponding for the page sequence number of NVM internal memory, obtains cryptographic Hash.
In the present embodiment, it is possible to erasable number of times corresponding for the page sequence number of all or part of NVM internal memory is carried out computing, the coefficient of weighting can be self-defined as required, and the algorithm of Hash operation can also be free as required.Preferably, weight coefficient be defined as erasable number of times summation corresponding to all page sequence numbers and the maximum erasable number of times of all pages and ratio.Method of weighting and the actual erasable number of times of each page are multiplied by weight coefficient.As shown in Figure 8, NVM internal memory one has 3 pages to number of times log as erasable in the NVM page, page sequence number respectively 0,1,2, and corresponding erasable number of times is 8,2,5, it is assumed that the maximum erasable number of times of each page is 20.Then weight coefficient is (8+2+5)/(20+20+20)=1/4.Actual for each page erasable number of times is multiplied by weight coefficient, namely 8 × 1/4=2,2 × 1/4=1,5 × 1/4=1.25.Using 2,1,1.25 as input, carry out Hash operation and obtain cryptographic Hash.Preferably, it is possible to use random number hash algorithm.
Step S122, obtains the page number that the available storage of NVM internal memory is corresponding.
In the present embodiment, the available storage of NVM internal memory is exactly the remaining total capacity that can store data in NVM internal memory, if NVM total amount of memory is 1G (1048576K), employ 128M (131702K), then the available storage of NVM internal memory is exactly 896M (917504K).Assume every 4K be unit as a page, then the page number that the available storage of NVM internal memory is corresponding is 917504K/4K=229376.Because the page number of the described correspondence page number that to be the available storage of NVM internal memory corresponding, so not over total page number of NVM internal memory.
Step S123, carries out complementation by cryptographic Hash with described corresponding page number, obtains the operation values of described erasable number of times.
In the present embodiment, cryptographic Hash is carried out complementation with described corresponding page number, because the page number of described correspondence is not over total page number of NVM internal memory, after carrying out complementation, operation values would is that one of them of total page number of NVM internal memory, thus by hash algorithm be data write have selected a page, owing to the operation result of hash algorithm has very strong random distribution, it is ensured that select the page harmony.
In one embodiment, as it is shown in figure 9, step S130 includes:
Step S131, it is judged that page sequence number be the NVM internal memory of operation values the page in whether there is free space, if yes then enter step S132, otherwise enter step S133.
In the present embodiment, if the residual capacity of the page of the NVM internal memory that page sequence number is operation values is not enough to write data, then it is judged as being absent from free space, is otherwise judged as there is free space.It is understood that free space is likely to continuously or discontinuously, as long as data to be written can enough be preserved.
Step S132, writes data into described free space.
In the present embodiment, it is possible to by data one-time write continuous print free space, it is also possible to when free space is discontinuous, divide and write free space several times.
Step S133, is added described operation values with default value, obtains intermediate value.
In the present embodiment, when the page of the NVM internal memory that page sequence number is described operation values is absent from free space, in the corresponding page sequence number page after described operation values, find free space.Concrete, default value can customize, and preferential may be defined as 1.If operation values is 2, then it is added with default value 1 that to obtain intermediate value be 3.
Step S134, it is judged that whether the page that page sequence number is the NVM internal memory of intermediate value exists free space, if it is, enter step S135, otherwise enters step S136.
In the present embodiment, the page corresponding to being, using page sequence number, the intermediate value obtained in previous step is as the page needing write data, but whether writable data, to first judge whether it exists free space.If the residual capacity of the described page is not enough to write data, then it is judged as being absent from free space, is otherwise judged as there is free space.It is understood that free space is likely to continuously or discontinuously, as long as data to be written can enough be preserved.
Step S135, writes data into described free space.
In the present embodiment, it is possible to by data one-time write continuous print free space, it is also possible to when free space is discontinuous, divide and write free space several times.
Step S136, it is judged that whether described intermediate value exceedes maximum page sequence number, if not having, enters step S137, otherwise enters step S138.
In the present embodiment, if the page of the NVM internal memory that page sequence number is intermediate value is also without free space, then need the further page sequence number in the correspondence page after above-mentioned intermediate value finds free space.Before searching, to first judging whether that oneself reaches last page, namely judges whether described intermediate value exceedes maximum page sequence number, if not having, entering step S137, otherwise enter step S138.
Step S137, continues to be added with default value by intermediate value, starts to repeat from step S134.
In the present embodiment, continue to be added with default value by intermediate value, start to repeat from step S134, further find the page that there is free space.
Step S138, it is judged that whether the page corresponding to maximum page sequence number exists free space, if it is present enter step S139, otherwise enters step S140.
In the present embodiment, it is judged that whether the page corresponding to maximum page sequence number exists free space, if the residual capacity of the described page is not enough to write data, then is judged as being absent from free space, is otherwise judged as there is free space.It is understood that free space is likely to continuously or discontinuously, as long as data to be written can enough be preserved.
Step S139, writes data into the free space of the page corresponding to described maximum page sequence number.
In the present embodiment, it is possible to by data one-time write continuous print free space, it is also possible to when free space is discontinuous, divide and write free space several times.
Step S140, obtains the page that there is free space in NVM internal memory, writes data in the page.
In the present embodiment, if until the page corresponding to maximum page sequence number is also without free space, then whether the detection page sequence number page before above-mentioned operation values exists free space one by one, and writes data in the page that there is free space.
In the present embodiment, by operation values is added with default value, the page after the page of the NVM internal memory that page sequence number is operation values constantly finds free space, until finding free space, when can be absent from free space in the page that first time selects, further select the free space of other page, thus write data.
In one embodiment, as shown in Figure 10, it is provided that a kind of erasable control system of the NVM internal memory based on isomery mixing internal memory, including:
Acquisition module 510, is used for obtaining the erasable number of times log of the NVM page, have recorded the page sequence number of NVM internal memory and corresponding erasable number of times in this NVM page erasable number of times log.
Computing module 520, for according to the erasable number of times log of the NVM page, adopting equalization algorithm that the erasable number of times that the page sequence number of NVM internal memory is corresponding is carried out computing, obtain the operation values of described erasable number of times.
Writing module 530, for the page according to the NVM internal memory that described page sequence number is described operation values, writes data in NVM internal memory.
In another embodiment, as shown in figure 11, on the basis of above-described embodiment, described system also includes:
First copy module 540, for when start powers on, copying erasable for the NVM page in NVM internal memory number of times log to DRAM relief area.
More new module 550, for whenever having after in data write NVM internal memory, updating erasable for the NVM page of DRAM relief area number of times log.
Preserve module 560, for, before shutdown or power down, being saved in NVM internal memory by erasable for the NVM page of renewal number of times log.
In yet another embodiment, as shown in figure 12, on the basis of above-described embodiment, described system also includes:
Second copy module 570, for copying to erasable for the NVM page in DRAM relief area number of times log in DRAM internal memory.
In one embodiment, described acquisition module 510 is additionally operable to obtain the address mapping relation of the erasable number of times log of the NVM page；The storage position of the erasable number of times log of the NVM page is obtained according to address mapping relation；The erasable number of times log of the NVM page is read from storage position.
In one embodiment, as shown in figure 13, described computing module 520 includes:
Hash operation unit 521, for carrying out Hash operation after being weighted by erasable number of times corresponding for the page sequence number of NVM internal memory, obtains cryptographic Hash.
Acquiring unit 522, the page number corresponding for obtaining the available storage of NVM internal memory.
Complementation unit 523, for cryptographic Hash is carried out complementation with described corresponding page number, obtains the operation values of erasable number of times.
In one embodiment, whether the page of the NVM internal memory that writing module 530 is additionally operable to judge that page sequence number is described operation values exists free space, if, then write data into described free space, otherwise described operation values is added with default value, obtains intermediate value, and perform:
S1: judge whether the page of the NVM internal memory that page sequence number is intermediate value exists free space, if it is, write data into described free space；Otherwise, determine whether whether intermediate value exceedes maximum page sequence number, if not having, then continue to be added with default value by intermediate value, repeat S1；
S2: if intermediate value exceedes maximum page sequence number, then judge whether the page corresponding to maximum page sequence number exists free space, if existed, then write data into the free space of the page corresponding to maximum page sequence number, otherwise obtain the page that there is free space in NVM internal memory, write data in the described page.
Embodiment described above only have expressed the several embodiments of the present invention, and it describes comparatively concrete and detailed, but therefore can not be interpreted as the restriction to the scope of the claims of the present invention.It should be pointed out that, for the person of ordinary skill of the art, without departing from the inventive concept of the premise, it is also possible to making some deformation and improvement, these broadly fall into protection scope of the present invention.Therefore, the protection domain of patent of the present invention should be as the criterion with claims.
Claims (12)
1., based on the erasable control method of NVM internal memory of isomery mixing internal memory, described method includes:
Obtain the erasable number of times log of the NVM page, the described NVM page erasable number of times log have recorded the page sequence number of NVM internal memory and corresponding erasable number of times；
According to the erasable number of times log of the NVM page, adopt equalization algorithm that the erasable number of times that the page sequence number of described NVM internal memory is corresponding is carried out computing, obtain the operation values of described erasable number of times；
The page according to the NVM internal memory that described page sequence number is described operation values, writes data in NVM internal memory.
2. method according to claim 1, it is characterised in that described method also includes:
When start powers on, copy the erasable number of times log of the described NVM page in NVM internal memory to DRAM relief area；
Whenever having after in data write NVM internal memory, erasable for the NVM page of described DRAM relief area number of times log is updated；
Before shutdown or power down, erasable for the NVM page of described renewal number of times log is saved in NVM internal memory.
3. method according to claim 2, it is characterised in that after the described step that erasable for the NVM page in NVM internal memory number of times log is copied to DRAM relief area, also include:
Erasable for the NVM page in DRAM relief area number of times log is copied in DRAM internal memory.
4. method according to claim 1, it is characterised in that the step of the described erasable number of times log of the acquisition NVM page includes:
Obtain the address mapping relation of the erasable number of times log of the NVM page；
The storage position of the erasable number of times log of the NVM page is obtained according to described address mapping relation；
The erasable number of times log of the described NVM page is read from described storage position.
5. method according to claim 1, it is characterised in that described according to the erasable number of times log of the NVM page, adopts equalization algorithm that the erasable number of times that the page sequence number of described NVM internal memory is corresponding is carried out computing, and the step of the operation values obtaining described erasable number of times is:
Carry out Hash operation after being weighted by erasable number of times corresponding for the page sequence number of described NVM internal memory, obtain cryptographic Hash；
Obtain the page number that the available storage of NVM internal memory is corresponding；
Described cryptographic Hash is carried out complementation with described corresponding page number, obtains the operation values of described erasable number of times.
6. method according to claim 1, it is characterised in that the described page according to the NVM internal memory that described page sequence number is described operation values, the step write data in NVM internal memory includes:
Judge whether the page of the NVM internal memory that page sequence number is described operation values exists free space, if it is, write data into described free space, otherwise described operation values is added with default value, obtains intermediate value；
S1: judge whether the page of the NVM internal memory that page sequence number is described intermediate value exists free space, if it is, write data into described free space；Otherwise, determining whether whether described intermediate value exceedes maximum page sequence number, if not having, then continuing to be added with described default value by described intermediate value, repeated execution of steps S1；
S2: if described intermediate value exceedes maximum page sequence number, then judge whether the page corresponding to described maximum page sequence number exists free space, if existed, then write data into the free space of the page corresponding to described maximum page sequence number, otherwise obtain the page that there is free space in NVM internal memory, write data in the described page.
7. the erasable control system of the NVM internal memory based on isomery mixing internal memory, it is characterised in that described system includes:
Acquisition module, is used for obtaining the erasable number of times log of the NVM page, have recorded the page sequence number of NVM internal memory and corresponding erasable number of times in the described NVM page erasable number of times log；
Computing module, for according to the erasable number of times log of the NVM page, adopting equalization algorithm that the erasable number of times that the page sequence number of described NVM internal memory is corresponding is carried out computing, obtain the operation values of described erasable number of times；
Writing module, for the page according to the NVM internal memory that described page sequence number is described operation values, writes data in NVM internal memory.
8. system according to claim 7, it is characterised in that described system also includes:
First copy module, for when start powers on, copying the erasable number of times log of the described NVM page in NVM internal memory to DRAM relief area；
More new module, for whenever having after in data write NVM internal memory, updating erasable for the NVM page of described DRAM relief area number of times log；
Preserve module, for, before shutdown or power down, being saved in NVM internal memory by erasable for the NVM page of described renewal number of times log.
9. system according to claim 8, it is characterised in that described system also includes:
Second copy module, for copying to erasable for the NVM page in DRAM relief area number of times log in DRAM internal memory.
10. system according to claim 7, it is characterised in that described acquisition module is additionally operable to obtain the address mapping relation of the erasable number of times log of the NVM page；The storage position of the erasable number of times log of the NVM page is obtained according to described address mapping relation；The erasable number of times log of the described NVM page is read from described storage position.
11. system according to claim 7, it is characterised in that described computing module includes:
Hash operation unit, for carrying out Hash operation after being weighted by erasable number of times corresponding for the page sequence number of described NVM internal memory, obtains cryptographic Hash；
Acquiring unit, the page number corresponding for obtaining the available storage of NVM internal memory；
Complementation unit, for described cryptographic Hash is carried out complementation with described corresponding page number, obtains the operation values of described erasable number of times.
12. system according to claim 7, it is characterized in that, whether the page of the NVM internal memory that said write module is additionally operable to judge that page sequence number is described operation values exists free space, if, then write data into described free space, otherwise described operation values is added with default value, obtains intermediate value；And perform:
S1: judge whether the page of the NVM internal memory that page sequence number is described intermediate value exists free space, if it is, write data into described free space；Otherwise, determine whether whether described intermediate value exceedes maximum page sequence number, if not having, then continue to be added with described default value by described intermediate value, repeat S1；
S2: if described intermediate value exceedes maximum page sequence number, then judge whether the page corresponding to described maximum page sequence number exists free space, if existed, then write data into the free space of the page corresponding to described maximum page sequence number, otherwise obtain the page that there is free space in NVM internal memory, write data in the described page.
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