CN105786722B

CN105786722B - NVM (non-volatile memory) erasing control method and system based on heterogeneous hybrid memory

Info

Publication number: CN105786722B
Application number: CN201410830327.1A
Authority: CN
Inventors: 薛英仪; 马先明; 庞观士; 陈志列; 王志远; 沈航; 梁艳妮; 徐成泽
Original assignee: EVOC Intelligent Technology Co Ltd
Current assignee: Yanxiang Smart Iot Technology Co ltd
Priority date: 2014-12-25
Filing date: 2014-12-25
Publication date: 2020-10-27
Anticipated expiration: 2034-12-25
Also published as: CN105786722A

Abstract

The invention provides an NVM (non volatile memory) erasing control method based on a heterogeneous hybrid memory, which comprises the following steps: acquiring an NVM page erasing frequency recording table, wherein the NVM page erasing frequency recording table records the page number of an NVM and the corresponding erasing frequency; according to the NVM page erasing frequency recording table, adopting a balance algorithm to calculate erasing frequencies corresponding to the page sequence number of the NVM memory to obtain a calculation value of the erasing frequencies; and writing data into the NVM according to the page of the NVM with the page sequence number as the operation value. The balancing algorithm can ensure that the selected times of all the pages of the NVM are relatively random and average, thereby controlling the erasing times among different memory units of the NVM and ensuring that the service life of each memory unit is relatively average. In addition, an NVM memory erasing control system based on the heterogeneous hybrid memory is also provided.

Description

NVM (non-volatile memory) erasing control method and system based on heterogeneous hybrid memory

Technical Field

The invention relates to the technical field of computers, in particular to a method and a system for controlling erasing and writing of an NVM (non-volatile memory) based on a heterogeneous hybrid memory.

Background

With the development of Non-Volatile random access Memory (NVM) technology represented by resistive Memory, ferroelectric Memory, phase change Memory, etc., the development of storage technology is promoted, and a good foundation is laid for the generation of a novel Memory and storage architecture. By combining a novel NVM and a Dynamic Random Access Memory (DRAM), a hybrid Memory architecture is built to form a heterogeneous hybrid Memory. The heterogeneous hybrid memory has the characteristics of both NVM and DRAM, not only has the function of a conventional memory, but also is volatile, and data stored in the DRAM can disappear immediately after power failure; meanwhile, the advantage that the NVM can store data after power failure can be exerted, the nonvolatile characteristic of the NVM is fully exerted, and the memory is a novel memory which is used in a mixed mode.

The heterogeneous hybrid memory meets the conventional memory interface of the existing industrial control equipment, and a new industrial control equipment does not need to be introduced or a new auxiliary equipment does not need to be added, so that the heterogeneous hybrid memory becomes a research hotspot.

The NVM in the heterogeneous hybrid memory is different from the DRAM in characteristics, the NVM has the inherent defect of limited total erasing times, and the NVM fails after reaching a certain erasing times, so the service life of the NVM is limited, the service life is determined by the maximum erasing times and exceeds the maximum erasing times, and the erasable unit becomes a bad block and cannot be normally used. The conventional erasing control method is specific to the DRAM, and the conventional erasing control method is not suitable for the NVM in the heterogeneous hybrid memory because the DRAM has no limit of the total erasing times.

Disclosure of Invention

Therefore, it is necessary to provide an NVM memory erasing and writing control method and system based on heterogeneous hybrid memory to control the erasing and writing times between different NVM memory cells, so as to make them more balanced and make the life of each memory cell more average.

A heterogeneous hybrid memory-based NVM (non volatile memory) erasing control method comprises the following steps:

acquiring an NVM page erasing frequency recording table, wherein the NVM page erasing frequency recording table records the page number of an NVM and the corresponding erasing frequency;

according to an NVM page erasing frequency recording table, adopting a balance algorithm to calculate erasing frequencies corresponding to the page sequence number of the NVM memory, and obtaining a calculation value of the erasing frequencies;

and writing data into the NVM according to the page of the NVM with the page sequence number as the operation value.

In one embodiment, the method further comprises:

copying the NVM page erasing frequency recording table in the NVM memory to a DRAM buffer area when starting up and powering on;

updating the NVM page erasing times recording table of the DRAM buffer area after data are written into the NVM memory;

and before shutdown or power failure, storing the updated NVM page erasing frequency record table into an NVM memory.

In one embodiment, after the step of copying the NVM page erase/write count table in the NVM memory to the DRAM buffer, the method further includes:

and copying the NVM page erasing times recording table in the DRAM buffer area into a DRAM memory.

In one embodiment, the step of obtaining the NVM page erase count record table includes:

acquiring an address mapping relation of an NVM page erasing frequency recording table;

obtaining the storage position of an NVM page erasing frequency recording table according to the address mapping relation;

and reading the NVM page erasing times recording table from the storage position.

In one embodiment, the step of calculating, by using a balancing algorithm, the erasing times corresponding to the page number of the NVM memory according to the NVM page erasing times recording table to obtain the calculated value of the erasing times includes:

weighting the erasing times corresponding to the page sequence number of the NVM, and then performing hash operation to obtain a hash value;

acquiring the page number corresponding to the available storage capacity of the NVM;

and performing remainder operation on the hash value and the corresponding page number to obtain an operation value of the erasing times.

In one embodiment, the step of writing data into the NVM memory according to the page of the NVM memory with the page number as the operation value includes:

judging whether an available space exists in a page of the NVM with the page sequence number being the operation value, if so, writing data into the available space, otherwise, adding the operation value and a preset numerical value to obtain an intermediate value;

s1: judging whether the page of the NVM with the page sequence number of the intermediate value has available space, if so, writing data into the available space; otherwise, further judging whether the intermediate value exceeds the maximum page sequence number, if not, continuing to add the intermediate value to the preset numerical value, and repeatedly executing the step S1;

s2: if the intermediate value exceeds the maximum page sequence number, judging whether the page corresponding to the maximum page sequence number has an available space, if so, writing the data into the available space of the page corresponding to the maximum page sequence number, otherwise, acquiring the page with the available space in the NVM memory, and writing the data into the page.

A heterogeneous hybrid memory-based NVM memory erasure control system, the system comprising:

the acquiring module is used for acquiring an NVM page erasing frequency recording table, and the NVM page erasing frequency recording table records the page number of an NVM memory and the corresponding erasing frequency;

the operation module is used for operating the erasing times corresponding to the page sequence number of the NVM by adopting a balance algorithm according to the NVM page erasing times recording table to obtain an operation value of the erasing times;

and the writing module is used for writing data into the NVM according to the page of the NVM with the page sequence number as the operation value.

In one embodiment, the system further comprises:

the first copying module is used for copying the NVM page erasing and writing frequency recording table in the NVM memory to a DRAM buffer area when the starting is powered on;

the updating module is used for updating the NVM page erasing and writing frequency recording table of the DRAM buffer area after data are written into the NVM memory;

and the storage module is used for storing the updated NVM page erasing and writing frequency recording table into an NVM memory before shutdown or power failure.

In one embodiment, the system further comprises:

and the second copying module is used for copying the NVM page erasing times recording table in the DRAM buffer area into the DRAM memory.

In one embodiment, the obtaining module is further configured to obtain an address mapping relationship of an NVM page erasing number recording table; obtaining the storage position of an NVM page erasing frequency recording table according to the address mapping relation; and reading the NVM page erasing times recording table from the storage position.

In one embodiment, the operation module includes:

the hash operation unit is used for weighting the erasing times corresponding to the page sequence number of the NVM and then carrying out hash operation to obtain a hash value;

the device comprises an acquisition unit, a storage unit and a processing unit, wherein the acquisition unit is used for acquiring the number of pages corresponding to the available storage capacity of the NVM;

and the residue taking operation unit is used for carrying out residue taking operation on the hash value and the corresponding page number to obtain an operation value of the erasing times.

In one embodiment, the writing module is further configured to determine whether an available space exists in a page of the NVM memory having a page sequence number of the operation value, if so, write data into the available space, otherwise, add the operation value to a preset value to obtain an intermediate value; and executing:

s1: judging whether the page of the NVM with the page sequence number of the intermediate value has available space, if so, writing data into the available space; otherwise, further judging whether the intermediate value exceeds the maximum page sequence number, if not, continuing to add the intermediate value to the preset numerical value, and repeatedly executing S1;

According to the NVM memory erasing control method and system based on the heterogeneous hybrid memory, the NVM page erasing frequency recording table is obtained, and the page sequence number and the corresponding erasing frequency of the NVM memory are recorded in the recording table; calculating the erasing times corresponding to the page sequence number of the NVM according to the NVM page erasing times recording table and by adopting a balance algorithm to obtain a calculation value of the erasing times; and writing data into the NVM according to the page of the NVM with the page sequence number as the operation value. The balancing algorithm can ensure that the selected times of all the pages of the NVM are relatively random and average, thereby controlling the erasing times among different memory units of the NVM, balancing the erasing times and the erasing times, and enabling the service life of each memory unit to be relatively average.

Drawings

FIG. 1 is a flowchart of an embodiment of a heterogeneous hybrid memory-based NVM erasure control method;

FIG. 2 is a diagram of an NVM page erase count table according to one embodiment;

FIG. 3 is a flowchart of another embodiment of storing a table of records of erase times for NVM pages;

FIG. 4 is a diagram illustrating an exemplary heterogeneous hybrid memory;

FIG. 5 is a diagram of an embodiment of a table of records of erase times for updated NVM pages;

FIG. 6 is a flowchart illustrating obtaining a table of records of erase times for NVM pages in one embodiment;

FIG. 7 is a flow diagram illustrating operation of erase counts in one embodiment;

FIG. 8 is a diagram of a table of NVM page erase count records in another embodiment;

FIG. 9 is a flow diagram of writing data to NVM memory in one embodiment;

FIG. 10 is a block diagram of an embodiment of an NVM erasure control system based on heterogeneous hybrid memory;

FIG. 11 is a block diagram of an NVM erasure control system based on heterogeneous hybrid memory in another embodiment;

FIG. 12 is a block diagram of an NVM erasure control system based on a heterogeneous hybrid memory in yet another embodiment;

FIG. 13 is a block diagram of an operation module in one embodiment.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

In one embodiment, as shown in fig. 1, a method for controlling erasing and writing of an NVM memory based on a heterogeneous hybrid memory is provided, the method comprising:

step S110, obtaining an NVM page erasing times recording table, wherein the NVM page erasing times recording table records the page number of the NVM and the corresponding erasing times.

In this embodiment, paging is performed on the NVM memory according to a preset physical page as a unit, a page number is allocated to each paged page, data is written into the page corresponding to the page number, the erasing times corresponding to the page number are updated, and all the page numbers and the corresponding erasing times of the NVM memory are recorded in the NVM page erasing times recording table. If the size of each physical page is 4KB by default and the total capacity of the NVM is 1M, 256 pages are available after paging, a page sequence number of 0-255 is allocated to each page, the erasing frequency corresponding to each page sequence number is recorded, the page erasing frequency of the unused NVM is marked as 0, and 1 is added to the corresponding erasing frequency every time the page of the NVM is written once. FIG. 2 shows a table of the number of erasing times of an NVM page.

And step S120, according to the NVM page erasing times recording table, adopting a balance algorithm to calculate the erasing times corresponding to the page sequence number of the NVM memory, and obtaining the calculated value of the erasing times.

In this embodiment, the equalization algorithm is an algorithm that can distribute the calculation results as randomly and evenly as possible, and a suitable equalization algorithm may be selected as needed, and then the number of times of erasing and writing corresponding to the page number of the NVM memory is calculated based on the equalization algorithm. For example, Round robin algorithm, Hash algorithm, card (Common access redundancy Protocol), Consistent Hash algorithm, or a combination of several algorithms may be used to implement the equalization algorithm. It can be understood that, before the operation is performed, the NVM page erase/write times recording table may be sorted from small to large or from large to small according to the erase/write times, so as to conveniently search the maximum erase/write times, the minimum erase/write times, and the corresponding page sequence numbers.

Specifically, when the Round robin algorithm is adopted, the page number corresponding to the minimum erasing frequency is found out and used as the calculation value of the erasing frequency. When the Hash algorithm is adopted, all or part of erasing times in the NVM page erasing and writing time recording table can be subjected to Hash operation to obtain a Hash value, then the Hash value is added to the total number of the page, and the value obtained after adding is used as the operation value of the erasing and writing times. When the CARP algorithm is adopted, the erasing times corresponding to the page number of the NVM and the data writing marks of the page corresponding to the same page number are added, and the added value is subjected to MD5 (information summary algorithm) operation to obtain an operated value. If the number of times of erasing and writing corresponding to the page number of the NVM needing to be operated is multiple, the operation is respectively carried out to obtain multiple operation results, and the page number of the NVM corresponding to the maximum value in the operation results is used as the operation value of the number of times of erasing and writing. It will be appreciated that the data write flag can be customized, such as "0" for no data write and "1" for data write. When the constraint hash algorithm is adopted, the hash value of the erasing times corresponding to the page number of each NVM memory can be firstly obtained and configured on a circle of 0-2 ^ 32. And then, calculating the hash value of the available storage capacity corresponding to the page number of each NVM by the same method, mapping the hash value to a circle, clockwise searching from the position where the data is mapped, taking the page number corresponding to the found first erasing frequency as the operation value of the erasing frequency, and if the erasing frequency is not found even if the data exceeds 2^32, taking the page number of the smallest NVM as the operation value of the erasing frequency.

Step S130, writing the data into the NVM memory according to the page of the NVM memory whose page number is the operation value.

In this embodiment, according to the actual storage condition of the page of the NVM memory whose page sequence number is an operation value, data is preferentially written into the page of the NVM memory whose page sequence number is an operation value, and when there is no available space in the page of the NVM memory whose page sequence number is an operation value, whether there is available space in other pages adjacent to the page is detected one by one according to the sequence of the page sequence numbers, and the data is written into the page in which there is available space. It can be understood that, before writing data, statistics are performed on the remaining capacity of the NVM memory, and a corresponding data write request is issued only if there is available space in the NVM memory.

In the embodiment, a NVM page erasing frequency recording table is obtained, and the page sequence number and the corresponding erasing frequency of the NVM memory are recorded in the recording table; calculating the erasing times corresponding to the page sequence number of the NVM according to the NVM page erasing times recording table and by adopting a balance algorithm to obtain a calculation value of the erasing times; and writing the data into the NVM according to the page of the NVM with the page sequence number as the operation value. The balancing algorithm can ensure that the selected times of all the pages of the NVM are relatively random and average, thereby controlling the erasing times among different memory units of the NVM, balancing the erasing times and the erasing times, and enabling the service life of each memory unit to be relatively average.

In one embodiment, as shown in fig. 3, the method further comprises:

in step S210, when the device is powered on, the NVM page erasing times recording table in the NVM memory is copied to the DRAM buffer.

In this embodiment, the heterogeneous hybrid memory may be composed of the structure shown in fig. 4, and includes an NVM-DRAM hybrid module 410 and a DRAM memory 420, where the NVM-DRAM hybrid module 410 includes an NVM memory 411 and a DRAM buffer 412. The read-write speed of the DRAM buffer 412 is faster than the read-write speed of the NVM memory 411, and when the device is powered on, the NVM page erase/write frequency recording table in the NVM memory 411 is copied to the DRAM buffer 412, so that on one hand, the read-write efficiency can be improved, and on the other hand, the erase/write frequency of the NVM memory 411 cannot be excessively consumed.

In step S220, the NVM page erase/write frequency record table of the DRAM buffer is updated every time data is written into the NVM memory.

In this embodiment, all the erasing times modification actions are executed by the controller in the DRAM buffer 412, and the page sequence number is updated for the corresponding erasing times of the corresponding page area every time the page area specified by the NVM is written once. The controller is a control unit inside the NVM-DRAM hybrid module 410 that can control the NVM-DRAM hybrid module 410 and communicate with other modules outside. If the NVM page erase count table before updating is shown in fig. 2, if data is written into the page with the page number of 1, the corresponding erase count is increased by 1, and the NVM page erase count table after updating is shown in fig. 5.

Step S230, before shutdown or power failure, the updated NVM page erasing frequency record table is saved in the NVM memory.

In this embodiment, since the DRAM buffer 412 is a memory of a DRAM medium, data stored in the DRAM will disappear immediately after power is turned off and is volatile, whereas the NVM memory is non-volatile and can store data after power is turned off. Therefore, before shutdown or power failure, the NVM controller writes back the updated NVM page erasing times recording table in the DRAM buffer to the NVM memory, and data is not lost, so that the updated NVM page erasing times recording table can be used after next startup.

In one embodiment, after the step of copying the NVM page erase count table in the NVM memory to the DRAM buffer, the method further comprises: and copying the NVM page erasing times recording table in the DRAM buffer area into a DRAM memory.

In this embodiment, although the DRAM buffer and the DRAM memory both belong to DRAM grains, and the read/write speeds of the same type of DRAM grains are the same or similar, the access speeds and the delay times of a certain master to the DRAM buffer and the DRAM memory are different due to different external logic designs. For example, when the DRAM buffer works, the DRAM buffer is divided into two time slices, wherein one time slice exchanges data with a DDR3 interface at a CPU end, and the other time slice exchanges data with the NVM; the DRAM memory can exchange data with the CPU all the time, and the CPU accesses the DRAM buffer in the NVM-DRAM hybrid module indirectly (cannot be accessed directly) through the controller unit, so the CPU accesses the DRAM memory faster than the DRAM buffer. In order to improve the working efficiency, the system driving layer gives instructions to the CPU at regular time during management, and the CPU copies the NVM page erasing times recording table in the DRAM buffer area into the DRAM memory. The timing can be customized, such as one copy in 10 minutes. The system driver layer refers to a system driver code and is a part of an operating system image, and the CPU calls the system driver layer to manage the heterogeneous hybrid memory. After the system driving layer copies the NVM page erasing times recording table to the DRAM, other programs can be directly read from the DRAM if the NVM page erasing times recording table is needed. The system driving layer and other programs only read the authority of the erasing and writing times record table of the NVM page in the DRAM, but have no authority of rewriting.

In one embodiment, as shown in fig. 6, step S110 includes:

step S111, obtaining the address mapping relation of the NVM page erasing frequency recording table.

In this embodiment, the address mapping relationship is stored in the heterogeneous hybrid memory as the information of the controller, and if the structure of the heterogeneous hybrid memory is as shown in fig. 4, the address mapping relationship may be stored in the first 4K address space of the NVM-DRAM hybrid module 410. When the system driving layer reads and writes the first 4K address space corresponding to the heterogeneous hybrid memory bank, the controller maps the first 4K address space to the control command area, so that the information of the controller can be directly obtained from the control command area. The control command area is an area in the virtual address space, and the information of the controller refers to the working state information of the NVM-DRAM hybrid module 410, including whether the controller is busy, whether data reading is allowed, whether data writing is allowed, the address mapping relationship of the NVM page erasing times recording table, and the like. The address mapping relation refers to the mapping relation between a virtual address space and a physical address space, and the actual storage position of the NVM page erasing frequency recording table can be found according to the address mapping relation.

Step S112, obtaining the storage position of the NVM page erasing frequency recording table according to the address mapping relation.

In this embodiment, when the CPU calls the system driver layer to manage the heterogeneous hybrid memory or other programs need to use the NVM page erase count record table, the address mapping relationship of the NVM page erase count record table is obtained first, and then the physical address space corresponding to the virtual address space is found according to the address mapping relationship, so as to find the actual storage location of the NVM page erase count record table.

In step S113, the NVM page erase/write count recording table is read from the storage location.

In this embodiment, the actual storage location of the NVM page erasure count table is found, and the NVM page erasure count table can be directly read from the storage location. In an embodiment, as shown in fig. 7, the process of operating the erasure count is described in detail by using a hash algorithm, and step S120 includes:

step S121, weighting the erasing times corresponding to the page sequence number of the NVM, and then performing hash operation to obtain a hash value.

In this embodiment, the erasing times corresponding to the page sequence numbers of all or part of the NVM memories may be calculated, the weighting coefficients may be customized as needed, and the hash algorithm may also be selected as needed. Preferably, the weighting factor is defined as the ratio of the sum of the erasing times corresponding to all the page numbers to the maximum sum of the erasing times of all the pages. The weighting method is that the actual erasing times of each page are multiplied by a weighting coefficient. For example, as shown in fig. 8, the NVM page erase count table has 3 pages, the page numbers are 0, 1 and 2, respectively, and the corresponding erase counts are 8, 2 and 5, assuming that the maximum erase count of each page is 20. The weighting coefficient is (8+2+5)/(20+20+20) ═ 1/4. The actual number of times of erasing each page is multiplied by a weighting factor, i.e., 8 × 1/4 ═ 2, 2 × 1/4 ═ 1, and 5 × 1/4 ═ 1.25. Taking 2, 1 and 1.25 as input, carrying out hash operation to obtain a hash value. Preferably, a random number hashing algorithm may be used.

In step S122, the number of pages corresponding to the available storage capacity of the NVM memory is obtained.

In this embodiment, the available storage capacity of the NVM memory is the total capacity of the NVM memory for storing data, for example, the total capacity of the NVM memory is 1G (1048576K), 128M (131702K) is used, and the available storage capacity of the NVM memory is 896M (917504K). Assuming that every 4K is a unit as a page, the number of pages corresponding to the available storage capacity of the NVM memory is 917504K/4K-229376. Because the corresponding page number is the page number corresponding to the available storage capacity of the NVM memory, the total page number of the NVM memory is not exceeded.

And S123, performing remainder operation on the hash value and the corresponding page number to obtain an operation value of the erasing times.

In this embodiment, the hash value and the corresponding page number are subjected to the remainder operation, because the corresponding page number does not exceed the total page number of the NVM memory, after the remainder operation is performed, the operation value will be one of the total page numbers of the NVM memory, so that a page is selected for data writing through the hash algorithm, and the balance of page selection is ensured because the operation result of the hash algorithm has strong random distribution.

In one embodiment, as shown in fig. 9, step S130 includes:

in step S131, it is determined whether there is an available space in the page of the NVM memory with the page sequence number as the operation value, if so, step S132 is performed, otherwise, step S133 is performed.

In this embodiment, if the remaining capacity of the page of the NVM memory with the page sequence number as the operation value is not enough to write data, it is determined that there is no available space, otherwise, it is determined that there is an available space. It will be appreciated that the available space may be continuous or discontinuous, as long as it is sufficient to hold the data to be written.

Step S132, writing the data into the available space.

In this embodiment, data may be written into a continuous available space at one time, or may be written into an available space several times when the available space is not continuous.

Step S133, adding the operation value to a preset value to obtain an intermediate value.

In this embodiment, when there is no available space in the page of the NVM memory whose page sequence number is the operation value, an available space is searched for in the page after the operation value corresponding to the page sequence number. Specifically, the preset value can be customized, and preferably can be defined as 1. If the operation value is 2, the intermediate value is 3 by adding the preset value 1.

In step S134, it is determined whether there is an available space in the page of the NVM memory with the page sequence number being the middle value, if so, step S135 is performed, otherwise, step S136 is performed.

In this embodiment, the page with the page sequence number corresponding to the intermediate value obtained in the previous step is taken as the page to which data needs to be written, but if data can be written, it is determined whether there is available space. And if the residual capacity of the page is not enough for writing data, judging that no available space exists, otherwise, judging that the available space exists. It will be appreciated that the available space may be continuous or discontinuous, as long as it is sufficient to hold the data to be written.

Step S135, writing the data into the available space.

Step S136, determining whether the intermediate value exceeds the maximum page number, if not, going to step S137, otherwise, going to step S138.

In this embodiment, if the page of the NVM memory having the page sequence number as the middle value does not have an available space, the available space needs to be further searched for in the page having the corresponding page sequence number after the middle value. Before searching, it is determined whether the last page is reached, that is, whether the intermediate value exceeds the maximum page number, if not, the step S137 is performed, otherwise, the step S138 is performed.

And step S137, continuing to add the intermediate value to the preset value, and repeating the step S134.

In this embodiment, the intermediate value is continuously added to the preset value, and the step S134 is repeated to further search for a page having an available space.

Step S138, determining whether the page corresponding to the maximum page sequence number has an available space, if so, going to step S139, otherwise, going to step S140.

In this embodiment, it is determined whether an available space exists in the page corresponding to the maximum page sequence number, and if the remaining capacity of the page is not sufficient for writing data, it is determined that the available space does not exist, otherwise, it is determined that the available space exists. It will be appreciated that the available space may be continuous or discontinuous, as long as it is sufficient to hold the data to be written.

And step S139, writing the data into the available space of the page corresponding to the maximum page sequence number.

Step S140, obtain a page having an available space in the NVM memory, and write data into the page.

In this embodiment, if there is no available space in the pages corresponding to the maximum page sequence number, whether there is available space in the pages with the page sequence numbers before the operation value is detected one by one, and data is written into the page with the available space.

In this embodiment, by adding the operation value to the preset value, an available space is continuously searched for in a page following a page of the NVM memory whose page number is the operation value until the available space is found, and when there is no available space in the first selected page, an available space in another page is further selected, so as to write data.

In one embodiment, as shown in fig. 10, there is provided a NVM memory erasure control system based on heterogeneous hybrid memory, including:

the obtaining module 510 is configured to obtain an NVM page erasing frequency record table, where the NVM page erasing frequency record table records a page number of the NVM memory and corresponding erasing frequency.

The operation module 520 is configured to perform operation on the erasing times corresponding to the page sequence number of the NVM memory by using a balancing algorithm according to the NVM page erasing times recording table to obtain an operation value of the erasing times.

A writing module 530, configured to write data into the NVM memory according to the page of the NVM memory whose page sequence number is the operation value.

In another embodiment, as shown in fig. 11, on the basis of the above embodiment, the system further includes:

the first copying module 540 is configured to copy the NVM page erase/write count record table in the NVM memory to the DRAM buffer when the device is powered on.

The updating module 550 is configured to update the NVM page erasing and writing frequency record table of the DRAM buffer every time when there is data written in the NVM memory.

The storing module 560 is configured to store the updated NVM page erasing and writing frequency record table into the NVM memory before shutdown or power failure.

In another embodiment, as shown in fig. 12, on the basis of the above embodiment, the system further includes:

the second copying module 570 is configured to copy the NVM page erase/write count table in the DRAM buffer to the DRAM memory.

In one embodiment, the obtaining module 510 is further configured to obtain an address mapping relationship of an NVM page erasing count record table; obtaining the storage position of an NVM page erasing frequency recording table according to the address mapping relation; reading the NVM page erasing times recording table from the storage position.

In one embodiment, as shown in fig. 13, the operation module 520 includes:

the hash operation unit 521 is configured to perform hash operation after weighting the erasing times corresponding to the page number of the NVM memory, so as to obtain a hash value.

The obtaining unit 522 is configured to obtain the number of pages corresponding to the available storage capacity of the NVM memory.

A remainder operation unit 523, configured to perform a remainder operation on the hash value and the corresponding page number to obtain an operation value of the erasing frequency.

In one embodiment, the writing module 530 is further configured to determine whether an available space exists in a page of the NVM memory with a page sequence number being the operation value, if so, write data into the available space, otherwise, add the operation value to a preset value to obtain an intermediate value, and perform:

s1: judging whether the page of the NVM with the page sequence number as the middle value has available space, if so, writing the data into the available space; otherwise, further judging whether the intermediate value exceeds the maximum page sequence number, if not, continuing to add the intermediate value to a preset numerical value, and repeatedly executing S1;

The above examples are merely illustrative of several embodiments of the present invention, and the description thereof is more specific and detailed, but not to be construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the appended claims.

Claims

1. A heterogeneous hybrid memory-based NVM (non volatile memory) erasing control method comprises the following steps:

judging whether an available space exists in a page of the NVM with the page sequence number being the operation value, if so, writing data into the available space, otherwise, adding the operation value and a preset numerical value to obtain an intermediate value; and executing:

2. The method of claim 1, further comprising:

3. The method of claim 2, further comprising, after the step of copying the NVM page erase count table in the NVM memory to a DRAM buffer:

4. The method of claim 1, wherein the step of obtaining the NVM page erase count table comprises:

5. The method according to claim 1, wherein the step of calculating the erasing times corresponding to the page sequence number of the NVM memory by using a balancing algorithm according to the NVM page erasing times record table to obtain the calculated value of the erasing times comprises:

6. An NVM memory erasure control system based on heterogeneous hybrid memory, the system comprising:

the writing module is used for judging whether an available space exists in a page of the NVM with the page sequence number being the operation value, if so, writing data into the available space, otherwise, adding the operation value and a preset numerical value to obtain a middle value; and executing:

7. The system of claim 6, further comprising:

8. The system of claim 7, further comprising:

9. The system according to claim 6, wherein the obtaining module is further configured to obtain an address mapping relationship of the NVM page erase/write count record table; obtaining the storage position of an NVM page erasing frequency recording table according to the address mapping relation; and reading the NVM page erasing times recording table from the storage position.

10. The system of claim 6, wherein the operation module comprises: