CN105786406A - CE NAND Flash page model establishing method supporting multi-channel main control concurrence and page model - Google Patents

CE NAND Flash page model establishing method supporting multi-channel main control concurrence and page model Download PDF

Info

Publication number
CN105786406A
CN105786406A CN201610104857.7A CN201610104857A CN105786406A CN 105786406 A CN105786406 A CN 105786406A CN 201610104857 A CN201610104857 A CN 201610104857A CN 105786406 A CN105786406 A CN 105786406A
Authority
CN
China
Prior art keywords
page
lpage
fpagetempy
road
logical page
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201610104857.7A
Other languages
Chinese (zh)
Inventor
黄雪峰
马翼
田达海
彭鹏
杨万云
向平
周士兵
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hunan Goke Microelectronics Co Ltd
Original Assignee
Hunan Goke Microelectronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hunan Goke Microelectronics Co Ltd filed Critical Hunan Goke Microelectronics Co Ltd
Priority to CN201610104857.7A priority Critical patent/CN105786406A/en
Publication of CN105786406A publication Critical patent/CN105786406A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G06F3/0613—Improving I/O performance in relation to throughput
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G06F3/0611—Improving I/O performance in relation to response time
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Read Only Memory (AREA)

Abstract

The invention discloses a CE NAND Flash page model establishing method supporting multi-channel main control concurrence and a page model.The page model is established according to the relations including FPageTempS=FPage\TCC, FPageTempY=FPage-FPageTempS*TCC, ACe= FPageTempY\TCh and ACh= FPageTempY-ACe*TCh, wherein FPageTempY is a middle variable, ACe represents a chip selection channel of current operation, ACh represents a channel of current operation, FPageTempS represents a physical page of current operation, FPage is a logical page of current operation, TCC is the chip selection channel total number of all channels, TCh is the number of the channels, and \ represents division.Reading, writing and wiping in all the channels can be processed in a concurrence mode, reading, writing and wiping can be conducted on all physical pages, operation time is greatly saved, and the throughput of main control and the read-write speed of a storage device are effectively increased.

Description

Support the concurrent CE NAND Flash of multichannel master control page model building method and Page model
Technical field
The present invention relates to storage medium, a kind of page mould supporting the concurrent CE NAND Flash of multichannel master control Type construction method and page model.
Background technology
Existing storage medium space requirement is increasing, it is desirable to the speed of service is increasingly faster, multichannel master control and many CE The appearance of storage medium be the certainty in epoch.Under multichannel complications, the erasing of NAND Flash, program, read to grasp also Non-moment just completes, and is required for the regular hour, and prior art be first processed a passage reading and writing, wipe operation after, The reading and writing of the next passage of reprocessing, wiping operation, waste the waiting time in processing procedure, reduce the handling capacity of master control Read or write speed with storage device.
Summary of the invention
The technical problem to be solved is, not enough for prior art, it is provided that a kind of support multichannel master control is also The page model building method of the CE NAND Flash sent out and page model.
For solving above-mentioned technical problem, the technical solution adopted in the present invention is: a kind of support that multichannel master control is concurrent The page model building method of CE NAND Flash, utilize following relational expression build page model:
FPageTempS = FPage \ TCC；
FPageTempY = FPage - FPageTempS * TCC；
ACe = FPageTempY \ TCh；
ACh = FPageTempY - ACe * TCh；
Wherein, FPageTempY is intermediate variable；ACe represents the sheet gating road of current operation；ACh represents the logical of current operation Road；FPageTempS represents the Physical Page of current operation；FPage is the logical page (LPAGE) of current operation；TCC is the sheet choosing of all passages Total number of channels；TCh is number of channels；Represent and take business.
Present invention also offers the CE NAND Flash that a kind of support multichannel master control utilizing said method to build is concurrent Page model, including multiple passages and multiple Physical Page；Multiple gating roads are included in each passage；For the first Physical Page, The first of first passage gates logical page (LPAGE) corresponding to road, the first of second channel gates the logical page (LPAGE) that road is corresponding ... n-th leads to The logical page (LPAGE) sequence number that the first gating road in road is corresponding is arranged in order from small to large, and respectively 0,1,2 ... n-1；First passage Logical page (LPAGE) that second gating road is corresponding, the logical page (LPAGE) that second gating road of second channel is corresponding ... second of the n-th passage The logical page (LPAGE) sequence number that gating road is corresponding is arranged in order from small to large, respectively n, n+1 ... n+n-1；The rest may be inferred, the first Physical Page The sequence number of remaining all logical page (LPAGE) is according to above-mentioned regularly arranged；If serial number i of first last logical page (LPAGE) of Physical Page, the most right In the second Physical Page, starting according to above-mentioned regularly arranged from sequence number i+1 of its all logical page (LPAGE)s；The rest may be inferred, determines last The sequence number of last logical page (LPAGE) of individual Physical Page.
Compared with prior art, the had the beneficial effect that present invention of the present invention can to the reading in each passage, Write, wipe and carry out concurrent processing, each Physical Page read and write simultaneously, wipe operation, thus be greatly saved the operating time, have Effect improves the handling capacity of master control and the read or write speed of storage device.
Accompanying drawing explanation
Fig. 1 is the concurrent sequential chart of one embodiment of the invention；
Fig. 2 is one embodiment of the invention page illustraton of model.
Detailed description of the invention
The erasing of NAND Flash, programming, read operation are not the most just to complete moment, need the regular hour, and existing Operating process slatterned during this period of time, it is contemplated that utilize during this period of time.Concrete flow process is, at passage 0, data occur During reading and writing wiping event and also being not fully complete operation, event is wiped in the read-write of trigger port 1, equally at passage 0 and 1, passage Life triggers the read-write of next passage again and wipes event when of reading and writing wiping event and be also not fully complete, the rest may be inferred.Fig. 1 is the present invention Sequential chart during concurrent processing.
What Fig. 1 represented is the concurrent process of the master control having 4 passages, in order to preferably express concurrent process, here only Depict the pin of RB(Ready/BusyNAND Flash on NAND Flash, if RB=0 represents NAND Flash Busy, RB=1 represent NAND Flash ready), it is intended to highlight and enter read-write wiping operation at the NAND Flash of a passage After time, the concurrent process of other passages.Utilize this characteristic, the speed of the storage devices such as SSD can be improved.
Utilize know-why above, set up the page model of the concurrent many CE NAND Flash of multichannel here.
If master control has 4 passages, having 4CE, FPage under a passage is page model.
Have: TCh(Total Channel)=4；
TCe(Total CE)=4；
TCC(Total Channel CE)= TCh* TCe =16；
Then page model expression is as follows:
FPageTempS = FPage \ TCC
FPageTempY = FPage - FPageTempS * TCC
ACe = FPageTempY \ TCh
ACh = FPageTempY - ACe * TCh
Wherein FPageTempY is intermediate variable, and ACe represents the CE(sheet gating road of current operation), ACh represents current operation CH(passage), what FPageTempS represented is the Physical Page of current operation.
The page model in concrete NAND Flash is corresponded to as shown in Figure 2 by above-mentioned expression formula.It is 4 passages shown in Fig. 2 4CE, leftmost PhyPage are physical page number, from Fig. 2 it is known that the arrangement mode of this model is to be come together by 4 passages Arrangement, thus can utilize 4 passages concurrently and is simultaneously written and read operation to 4 pages, substantially increases gulping down of master control The amount of telling, improves the read-write speed of storage device.

Claims (2)

1. the page model building method supporting the concurrent CE NAND Flash of multichannel master control, it is characterised in that under utilization State relational expression build page model:
FPageTempS = FPage \ TCC；
FPageTempY = FPage - FPageTempS * TCC；
ACe = FPageTempY \ TCh；
ACh = FPageTempY - ACe * TCh；
Wherein, FPageTempY is intermediate variable；ACe represents the sheet gating road of current operation；ACh represents the logical of current operation Road；FPageTempS represents the Physical Page of current operation；FPage is the logical page (LPAGE) of current operation；TCC is the sheet choosing of all passages Total number of channels；TCh is number of channels；Represent and take business.
2. the page mould of the CE NAND Flash that the support multichannel master control utilizing method described in claim 1 to build is concurrent Type, it is characterised in that include multiple passage and multiple Physical Page；Multiple gating roads are included in each passage；For the first thing Reason page, the first of first passage gates logical page (LPAGE) corresponding to road, the first of second channel gates the logical page (LPAGE) that road is corresponding ... The logical page (LPAGE) sequence number that the first gating road of the n-th passage is corresponding is arranged in order from small to large, and respectively 0,1,2 ... n-1；First leads to Logical page (LPAGE) that second gating road in road is corresponding, the logical page (LPAGE) that second gating road of second channel is corresponding ... the of the n-th passage The logical page (LPAGE) sequence number that two gating roads are corresponding is arranged in order from small to large, respectively n, n+1 ... n+n-1；The rest may be inferred, the first thing The sequence number of reason remaining all logical page (LPAGE) of page is according to above-mentioned regularly arranged；If serial number i of first last logical page (LPAGE) of Physical Page, Then for the second Physical Page, starting according to above-mentioned regularly arranged from sequence number i+1 of its all logical page (LPAGE)s；The rest may be inferred, determines The sequence number of last logical page (LPAGE) of later Physical Page.
CN201610104857.7A 2016-02-26 2016-02-26 CE NAND Flash page model establishing method supporting multi-channel main control concurrence and page model Pending CN105786406A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201610104857.7A CN105786406A (en) 2016-02-26 2016-02-26 CE NAND Flash page model establishing method supporting multi-channel main control concurrence and page model

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201610104857.7A CN105786406A (en) 2016-02-26 2016-02-26 CE NAND Flash page model establishing method supporting multi-channel main control concurrence and page model

Publications (1)

Publication Number Publication Date
CN105786406A true CN105786406A (en) 2016-07-20

Family

ID=56403599

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610104857.7A Pending CN105786406A (en) 2016-02-26 2016-02-26 CE NAND Flash page model establishing method supporting multi-channel main control concurrence and page model

Country Status (1)

Country Link
CN (1) CN105786406A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109992212A (en) * 2019-04-10 2019-07-09 苏州浪潮智能科技有限公司 A kind of method for writing data and a kind of method for reading data

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060044934A1 (en) * 2004-09-02 2006-03-02 Micron Technology, Inc. Cluster based non-volatile memory translation layer
CN102177556A (en) * 2008-10-13 2011-09-07 美光科技公司 Translation layer in a solid state storage device
CN102567257A (en) * 2011-12-26 2012-07-11 华中科技大学 Method for controlling data reading and writing of multi-channel solid-state disc

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060044934A1 (en) * 2004-09-02 2006-03-02 Micron Technology, Inc. Cluster based non-volatile memory translation layer
CN102177556A (en) * 2008-10-13 2011-09-07 美光科技公司 Translation layer in a solid state storage device
CN102567257A (en) * 2011-12-26 2012-07-11 华中科技大学 Method for controlling data reading and writing of multi-channel solid-state disc

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109992212A (en) * 2019-04-10 2019-07-09 苏州浪潮智能科技有限公司 A kind of method for writing data and a kind of method for reading data

Similar Documents

Publication Publication Date Title
CN105912307A (en) Data processing method and device of Flash controller
CN101187896B (en) On-spot programmable gate array data cache management method
JP2008529130A5 (en)
CN103902475B (en) Solid state disk concurrent access method and device based on queue management mechanism
TWI467574B (en) Memory storage device, memory controller thereof, and data transmission method thereof
CN105867840A (en) Flash memory assembly and nonvolatile semiconductor memory assembly
DE112010002663T5 (en) Write-erase endurance life of memory devices
DE112010003762B4 (en) Flash memory controller
CN106502586B (en) A method of improving solid state hard disk sequence reading performance
CN105183378A (en) Adaptive cache mixed reading/writing method
CN105204783B (en) A kind of solid-state disk rubbish recovering method based on data lifetime
CN101515221A (en) Method, device and system for reading data
CN104021094B (en) Data storage device and flash memory control method
CN107797755A (en) The atom wiring method of solid state hard disk system and the device using this method
CN103106155A (en) Storage storing device, storage controller and data transmission method thereof
TWI588652B (en) Methods for scheduling read and write commands and apparatuses using the same
CN106155572B (en) Data storage device and data access method
US20150261448A1 (en) Memory system, memory controller and control method of non-volatile memory
CN105786406A (en) CE NAND Flash page model establishing method supporting multi-channel main control concurrence and page model
CN104714892B (en) Data access command execution method and flash memory device using the same
DE102021121608A1 (en) METHOD OF WRITING DATA TO A NON-VOLATILE STORAGE DEVICE AND NON-VOLATILE STORAGE DEVICE EXECUTING THESE
CN101894077B (en) Data storage method and system
CN110134333B (en) Method and system for improving SSD read splicing rate by rearranging write data stream
CN106527962B (en) Internal data transfer method and device using the same
CN105320466A (en) Method for arranging operation of SSD (solid state drive)

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20160720

RJ01 Rejection of invention patent application after publication