CN101187896B - On-spot programmable gate array data cache management method - Google Patents

Abstract

The invention discloses a managing method for gate array data cache which can be programmed on site, when data is written, firstly, a writing operating module writes slicing data into a data memory, and records the length of the slicing data and gains the starting address in the data memory of the slicing data, and secondly, the writing operating module writes the length of the slicing data and the staring address in the data memory into the a storing controller. When data is read, firstly, a reading operating module reads the length of the slicing data which is gained by the storing controller and the staring address in the data memory, and secondly, the reading operating module reads the slicing data after giving the reading address of the data memory according to the staring address. The position of each massage slicing in the data memory is led to gain explicit mark by the technical proposal of the invention.

Description

A kind of management method of on-spot programmable gate array data cache

Technical field

The present invention relates to a kind of management method of metadata cache, the management method of especially a kind of FPGA (FieldProgrammable Gate Array, field programmable gate array) metadata cache.

Background technology

After FPGA receives pending data, data are write data FIFO (FirstInput First Output, First Input First Output), i.e. data-carrier store, and control information write control FIFO, i.e. memory controller; When control FIFO non-NULL, expression has data.Downstream module reads to control the controlled information of FIFO0, reads corresponding data then and handled from data FIFO.

Message with different passages in this patent carries out buffer memory by passage, require each passage that one group of FIFO control information must be arranged, as read/write address pointer, empty full state indication, individual counter etc., number of channels will cause managing the waste of inconvenience and logical resource more for a long time; Moreover, needing to set a DCON in this patent, a plurality of passages just need a plurality of different DCON.

The patent No. has been described a kind of method of packet buffer for the United States Patent (USP) of " US5664116 ", it is data cached promptly to adopt independent FIFO of each channel allocation to come, but the position of each message fragment in data FIFO do not have clear and definite sign, when in case read-write operation has a side to make a mistake, the data of whole buffer area all can read confusion, cause the mistake that can't recover.

Summary of the invention

The technical problem to be solved in the present invention provides a kind of management method of FPGA metadata cache, make the position of each message fragment in data FIFO obtain clear and definite sign, guaranteed the correctness of certain message fragment subsequent packet buffer memory when read-write operation makes a mistake.

The technical solution adopted for the present invention to solve the technical problems is:

A kind of management method of FPGA metadata cache,

May further comprise the steps during write data:

A: the write operation module receives message data, and obtains data channel number, start of message (SOM) sign and ENMES sign;

B: the write operation module is divided message data and is obtained burst by regular length, and with each burst respectively together with data channel number, start of message (SOM) sign and the ENMES sign form each fragment data;

C: the write operation module is handled whole fragment datas in the following manner one by one: a fragment data is all write data FIFO, write down the length of this fragment data and obtain the start address of this fragment data in data FIFO, this start address is to be transferred to the write operation module by data FIFO by default Wr_addr interface; The write operation module writes control FIFO with the length of this fragment data and the start address in data FIFO thereof;

May further comprise the steps during read data:

A, read operation module judge whether non-NULL of control FIFO, read control FIFO and obtain the length of a fragment data and the start address in data FIFO thereof;

B, read operation module provide the address of reading of data FIFO by default Rd_addr interface according to this start address;

C, read operation module are read the address according to this data FIFO are carried out a read operation, control initial value among the FIFO simultaneously and are 0 reading times counter and add 1;

D, judge according to the value of the length of this fragment data and reading times counter whether this fragment data reads and finish that if both are identical, promptly fragment data has read and finished, and gets back to steps A and carries out decision operation once more; Otherwise this is read the address increases by 1, and gets back to step C.

In the such scheme, described fragment data comprises by regular length divides burst that message data obtains and data channel number, start of message (SOM) sign and ENMES sign.

Beneficial effect of the present invention mainly shows: the address of the present invention return data FIFO when write operation, and when read operation, provide the start address of data FIFO, make the position of each message fragment in data FIFO obtain clear and definite sign, even certain message fragment makes a mistake when read-write operation, it is chaotic not cause that also whole data FIFO takes place, and guarantees the correctness of subsequent packet buffer memory; Moreover the present invention writes data FIFO with channel number together in company with data, only manages a data FIFO, just can the buffer memory multi-channel data, greatly simplified the complexity that realizes, and saved logical resource.

Description of drawings

Fig. 1 is the method flow diagram of write data FIFO in the management of FPGA metadata cache of the present invention;

Fig. 2 is the method flow diagram of read data FIFO in the management of FPGA metadata cache of the present invention.

Embodiment

The invention will be further described in conjunction with Fig. 1 and Fig. 2 respectively below.

With reference to Fig. 1, when the up-stream module of FPGA sent message data, the management method of metadata cache may further comprise the steps:

Step 101: the write operation module judges whether control FIFO and data FIFO be all non-full, if both are all non-full, then showing can also the buffer memory message data, enters step 102; Otherwise, show and can not receive data that execution in step 101 once more from up-stream module;

Step 102: the write operation module receives message data, and obtains data channel number, start of message (SOM) sign and ENMES sign;

Step 103: the write operation module is divided message data and is obtained burst by regular length, and with each burst respectively together with data channel number, start of message (SOM) sign and the ENMES sign form each fragment data;

Step 104: the write operation module all writes data FIFO with a fragment data, writes down the length of this fragment data and obtains the start address of this fragment data in data FIFO; Wherein, this start address is to be transferred to the write operation module by data FIFO by default Wr_addr interface; The length of record fragment data is because the length of message is fixing, often is not the integral multiple of the regular length set when dividing, and this makes the regular length that the curtailment of last burst of message data is set;

Step 105: the write operation module writes control FIFO with the length of this fragment data and the start address in data FIFO thereof;

Step 106: the write operation module judges whether that fragment data need write data FIFO in addition, if, get back to step 104, otherwise, process ends.

With reference to Fig. 2, when FPGA read message data, the management method of metadata cache may further comprise the steps:

Step 201: the read operation module is judged whether non-NULL of control FIFO, if not empty, and expression has at least a fragment data to be buffered in the data FIFO, enters step 202; Otherwise execution in step 201 once more;

Step 202: the read operation module reads control FIFO and obtains the length of a fragment data and the start address in data FIFO thereof;

Step 203: the read operation module provides the address of reading of data FIFO by default Rd_addr interface according to this start address;

Step 204: the read operation module is read the address according to this data FIFO is carried out a read operation, controls initial value among the FIFO simultaneously and is 0 reading times counter and add 1;

Step 205: judge according to the value of the length of this fragment data and reading times counter whether this fragment data reads and finish that if both are identical, the expression fragment data has read and finished, and gets back to step 201 and carries out decision operation once more; Otherwise, enter step 206;

Step 206: this is read the address increases by 1, and gets back to step 204.

Claims (2)

1. the management method of an on-spot programmable gate array data cache is characterized in that, may further comprise the steps during write data:

Whether a, write operation module judgement control FIFO and data FIFO be all non-full, if both are all non-full, enters next step;

B, write operation module receive message data, and obtain data channel number, start of message (SOM) sign and ENMES sign;

C, write operation module divide message data and obtain burst by regular length, and with each burst respectively together with data channel number, start of message (SOM) sign and the ENMES sign form each fragment data;

D, write operation module all write data FIFO with a fragment data, write down the length of this fragment data and obtain the start address of this fragment data in data FIFO, this start address is to be transferred to the write operation module by data FIFO by default Wr_addr interface; The write operation module writes control FIFO with the length of this fragment data and the start address in data FIFO thereof;

E, write operation module judge whether that fragment data need write data FIFO in addition, if, get back to steps d, otherwise, process ends;

May further comprise the steps during read data:

A, read operation module judge whether non-NULL of control FIFO, read control FIFO and obtain the length of a fragment data and the start address in data FIFO thereof;

B, read operation module provide the address of reading of data FIFO by default Rd_addr interface according to this start address;

C, read operation module are read the address according to this data FIFO are carried out a read operation, control initial value among the FIFO simultaneously and are 0 reading times counter and add 1;

D, judge according to the value of the length of this fragment data and reading times counter whether this fragment data reads and finish that if both are identical, promptly fragment data has read and finished, and gets back to steps A and carries out decision operation once more; Otherwise this is read the address increases by 1, and gets back to step C.

2. the management method of on-spot programmable gate array data cache as claimed in claim 1 is characterized in that: described fragment data comprises by regular length divides burst that message data obtains and data channel number, start of message (SOM) sign and ENMES sign.

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