CN105761758A - Shifting register unit, driving method, grid driving circuit and display device - Google Patents
Shifting register unit, driving method, grid driving circuit and display device Download PDFInfo
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- CN105761758A CN105761758A CN201610331065.3A CN201610331065A CN105761758A CN 105761758 A CN105761758 A CN 105761758A CN 201610331065 A CN201610331065 A CN 201610331065A CN 105761758 A CN105761758 A CN 105761758A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13454—Drivers integrated on the active matrix substrate
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
Abstract
The invention provides a shifting register unit, a driving method, a grid driving circuit and a display device. The shifting register unit comprises a first pull-up node control unit, a second pull-up node control unit, a third pull-up node control unit, a pull-down node control unit, a first output unit and a second output unit, wherein the second pull-up node control unit is used for controlling the potential of a second pull-up node to be at a first level under the control of a first pull-up node in an input period and an output period, used for controlling and maintaining the potential of the second pull-up node in a reset period, and used for controlling the potential of the second pull-up node to be at a second level in an output termination keeping period; the third pull-up node control unit is used for controlling the potential of a third pull-up node to be at the first level in the input period, used for controlling the potential of the third pull-up node to be risen by self in the output period, and used for controlling the third pull-up node to be connected with the second pull-up node in the reset period and the output termination keeping period. By adopting the shifting register unit, the stability of grid driving signal output can be improved, and the noise immunity can be improved.
Description
Technical field
The present invention relates to Display Technique field, particularly relate to a kind of shift register cell, driving method, gate driver circuit and display device.
Background technology
Development along with liquid crystal panel industry, competition in the industry is also more and more fierce, and GOA (GateOnArray, array base palte row cutting) circuit is as drive circuit main in display device, the quality of the properties of GOA circuit directly influences the excellent of liquid crystal display.Therefore, the lifting of the driveability of GOA circuit and improvement, also become the key technology of liquid crystal panel industry competition.In GOA circuit, the reduction of noise and the lifting of stability are the emphasis that GOA circuit design considers forever, and the noise of existing GOA circuit is high and stability is low.
Summary of the invention
A kind of shift register cell of offer, driving method, gate driver circuit and display device are provided, solve the problem that noise is high and stability is low of existing shift register cell.
In order to achieve the above object, the invention provides a kind of shift register cell, including gate drive signal outfan, described shift register cell also includes:
First pull-up node control unit, is connected with input, reset terminal and the first pull-up node respectively；
Second pull-up node control unit, it is connected with pull-down node, described first pull-up node and the second pull-up node respectively, it is the first level for controlling the current potential of described second pull-up node under the described first control pulling up node at input phase and output stage, the current potential controlling to maintain described second pull-up node at reseting stage is the first level, and the current potential controlling described second pull-up node in the output cut-off maintenance stage under the control of described pull-down node is second electrical level；3rd pull-up node control unit, pull up node respectively with described second and the 3rd pull-up node is connected, for controlling described 3rd pull-up node and the second pull-up node connection at input phase, thus the current potential controlling described 3rd pull-up node is the first level, draw high in the current potential bootstrapping of the 3rd pull-up node described in output stage control, keep the 3rd pull-up node described in stage control and described second pull-up node to connect at reseting stage and output cut-off；
Pull-down node control unit, is connected with pull-down node, is second electrical level for controlling the current potential of described pull-down node at input phase, output stage and reseting stage, keeps the current potential of pull-down node described in stage control to be the first level in output cut-off；
First output unit, pull up node with the described 3rd respectively and described gate drive signal outfan is connected, for under the control of described 3rd pull-up node, control at gate drive signal outfan output second electrical level described in input phase and reseting stage, and export the first level at gate drive signal outfan described in the output stage；And,
Second output unit, is connected with described pull-down node and described gate drive signal outfan respectively, for, under the control of described pull-down node, keeping gate drive signal outfan output second electrical level described in stage control in output cut-off.
During enforcement, described pull-down node control unit includes:
First pull-down node controls module, it is connected with described pull-down node, also pulling up node, described second pull-up node or described 3rd pull-up node to be connected with described first, the current potential controlling described pull-down node for pulling up the current potential of node, the current potential of described second pull-up node or the current potential of described 3rd pull-up node when described first when being the first level is second electrical level；
Second pull-down node controls module, is connected with described gate drive signal outfan and described pull-down node respectively, is second electrical level for controlling the current potential of described pull-down node when described gate drive signal outfan exports the first level；And,
3rd pull-down node controls module, is connected with described pull-down node, for keeping the current potential of pull-down node described in stage control to be the first level in output cut-off.
During enforcement, described first pull-down node controls module and includes: the first pull-down node controls transistor, grid pulls up node, described second pull-up node or described 3rd pull-up node and is connected with described first, and the first pole is connected with described pull-down node, and the second pole is connected with second electrical level outfan；
Described second pull-down node controls module and includes: the second pull-down node controls transistor, and grid is connected with described gate drive signal outfan, and the first pole is connected with described pull-down node, and the second pole is connected with described second electrical level outfan；
Described 3rd pull-down node controls module and includes: the 3rd pull-down node controls transistor, and grid and the first pole are all connected with the first clock signal input terminal, and the second pole is connected with described pull-down node；And, pull-down node maintains electric capacity, and the first end is connected with described pull-down node, and the second end is connected with described second electrical level outfan.
During enforcement, described second pull-up node control unit includes:
First pull-up controls transistor, and grid pulls up node with described first and is connected, and the second pole pulls up node with described second and is connected；
Second pull-up controls transistor, and grid and the first pole are all connected with the first level output end, and the first pole that the second pole controls transistor with described first pull-up is connected；
3rd pull-up controls transistor, and grid is connected with described pull-down node, and the first pole pulls up node with described second and is connected, and the second pole is connected with second electrical level outfan；And,
Pull-up maintains electric capacity, and the first end pulls up node with described second and is connected, and the second end is connected with second electrical level outfan.
During enforcement, described first output unit includes: the first output transistor, and grid pulls up node with the described 3rd and is connected, and the first pole is connected with second clock signal input part, and the second pole is connected with described gate drive signal outfan.
During enforcement, described 3rd pull-up node control module includes: the 4th pull-up controls transistor, grid and the first level output end and connects, and the first pole pulls up node with the described 3rd and is connected, and the second pole pulls up node with described second and is connected.
During enforcement, described second output unit includes: the second output transistor, and grid is connected with described pull-down node, and the first pole is connected with described gate drive signal outfan, and the second pole is connected with second electrical level outfan.
During enforcement, described first pull-up node control unit includes:
Input module, is connected with described input, described first pull-up node and the first scanning voltage signal output part respectively, is connected with described first scanning voltage signal output part for controlling described first pull-up node when being inputted the first level by described input；And,
Reseting module, is connected with described reset terminal, described first pull-up node and the second scanning voltage signal output part respectively, is connected with described second scanning voltage signal output part for controlling described first pull-up node when being inputted the first level by described reset terminal；
Described input connects with the gate drive signal outfan of adjacent upper level shift register cell, and described reset terminal connects with the gate drive signal outfan of adjacent next stage shift register cell；
When forward scan, described first scanning voltage signal output part exports the first level, described second scanning voltage signal output part output second electrical level；
When reverse scan, described first scanning voltage signal output part output second electrical level, described second scanning voltage signal output part exports the first level.
During enforcement, described input module includes: input transistors, and grid is connected with described input, and the first pole is connected with described first scanning voltage signal output part, and the second pole pulls up node with described first and is connected；
Described reseting module includes: reset transistor, and grid is connected with described reset terminal, and the first pole pulls up node with described first and is connected, and the second pole is connected with described second scanning voltage signal output part.
Present invention also offers the driving method of a kind of shift register cell, including:
Input phase in each display cycle, it is the first level that second pull-up node control unit controls the current potential of the second pull-up node under the first control pulling up node, 3rd pull-up node control unit controls the 3rd pull-up node and is connected with described second pull-up node, thus the current potential controlling described 3rd pull-up node is the first level, it is second electrical level that pull-down node control unit controls the current potential of pull-down node, and the first output unit controls described gate drive signal outfan output second electrical level under the described 3rd control pulling up node；
The output stage in each display cycle, it is the first level that second pull-up node control unit controls the current potential of described second pull-up node under the described first control pulling up node, 3rd pull-up node control unit controls the current potential bootstrapping of described 3rd pull-up node to be drawn high, it is second electrical level that pull-down node control unit controls the current potential of described pull-down node, and the first output unit controls described gate drive signal outfan under the described 3rd control pulling up node and exports the first level；
Reseting stage in each display cycle, it is the first level that second pull-up node control unit controls to maintain the current potential of described second pull-up node, 3rd pull-up node control unit controls described 3rd pull-up node and described second pull-up node connects, it is second electrical level that pull-down node control unit controls the current potential of described pull-down node, and the first output unit controls described gate drive signal outfan output second electrical level under the described 3rd control pulling up node；
Output in each display cycle ends the maintenance stage, it is second electrical level that second pull-up node control unit controls the current potential of described second pull-up node under the control of described pull-down node, 3rd pull-up node control unit controls described 3rd pull-up node and described second pull-up node connects, it is the first level that pull-down node control unit controls the current potential of described pull-down node, second output unit, under the control of described pull-down node, keeps gate drive signal outfan output second electrical level described in stage control in output cut-off.
During enforcement, input phase in each display cycle, it is that second electrical level step specifically includes that described pull-down node control unit controls the current potential of pull-down node: the first pull-down node controls module under the described first control pulling up node, described second pull-up node or described 3rd pull-up node, and the current potential controlling described pull-down node is second electrical level；
The output stage in each display cycle, it is that second electrical level step specifically includes that described pull-down node control unit controls the current potential of pull-down node: the first pull-down node controls module under the described first control pulling up node, described second pull-up node or described 3rd pull-up node, the current potential controlling described pull-down node is second electrical level, second pull-down node controls under the control of the gate drive signal that module export at described gate drive signal outfan, and the current potential of the described pull-down node of control is second electrical level further；
Reseting stage in each display cycle, it is that second electrical level step specifically includes that described pull-down node control unit controls the current potential of pull-down node: the first pull-down node controls module under the described second control pulling up node or described 3rd pull-up node, and the current potential controlling described pull-down node is second electrical level.
During enforcement, the driving method of shift register cell of the present invention also includes: at the input phase of each display cycle, and it is the first level that the first pull-up node control unit controls the current potential of described first pull-up node；
At the reseting stage of each display cycle, it is second electrical level that the first pull-up node control unit controls the current potential of described first pull-up node.
Present invention also offers a kind of gate driver circuit, including multistage above-mentioned shift register cell.
Present invention also offers a kind of display device, it is characterised in that include above-mentioned gate driver circuit.
With prior art star note, by adopting the second pull-up node control unit and the 3rd pull-up node control unit, shift register cell of the present invention, driving method, gate driver circuit and display device ensure that the current potential of the 3rd pull-up node is maintained the first level at input phase, output stage and reseting stage, to improve the stability of gate drive signal output, and by pull-down node input phase, output stage and reseting stage control described pull-down node current potential be second electrical level, to increase noise resisting ability.
Accompanying drawing explanation
Fig. 1 is the structure chart of the shift register cell described in the embodiment of the present invention；
Fig. 2 A is the structure chart of the shift register cell described in another embodiment of the present invention；
Fig. 2 B is the structure chart of the shift register cell described in further embodiment of this invention；
Fig. 2 C is the structure chart of the shift register cell described in yet another embodiment of the invention；
Fig. 3 A is the structure chart of the shift register cell described in another embodiment of the present invention；
Fig. 3 B is the structure chart of the shift register cell described in further embodiment of this invention；
Fig. 3 C is the structure chart of the shift register cell described in yet another embodiment of the invention；
Fig. 4 is the structure chart of the shift register cell described in the embodiment of the present invention；
Fig. 5 is the circuit diagram of the first specific embodiment of shift register cell of the present invention；
Fig. 6 is the working timing figure of the first specific embodiment of shift register cell of the present invention；
Fig. 7 is the circuit diagram of the second specific embodiment of shift register cell of the present invention；
Fig. 8 is the circuit diagram of the 3rd specific embodiment of shift register cell of the present invention；
Fig. 9 is the flow chart of the driving method of the shift register cell described in the embodiment of the present invention.
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is only a part of embodiment of the present invention, rather than whole embodiments.Based on the embodiment in the present invention, the every other embodiment that those of ordinary skill in the art obtain under not making creative work premise, broadly fall into the scope of protection of the invention.
As it is shown in figure 1, the shift register cell described in the embodiment of the present invention, including gate drive signal outfan OUT, described shift register cell also includes:
First pull-up node control unit 11, is connected with input INPUT, reset terminal RESET and the first pull-up node PU1 respectively；
Second pull-up node control unit 12, it is connected with pull-down node PD, described first pull-up node PU1 and the second pull-up node PU2 respectively, it is the first level for controlling the current potential of described second pull-up node PU2 under the described first control pulling up node PU1 at input phase and output stage, the current potential controlling to maintain described second pull-up node PU2 at reseting stage is the first level, and the current potential controlling described second pull-up node PU2 in the output cut-off maintenance stage under the control of described pull-down node PD is second electrical level；
3rd pull-up node control unit 13, pull up node PU2 and the 3rd pull-up node PU3 respectively to be connected with described second, connect for controlling described 3rd pull-up node PU3 and the second pull-up node PU2 at input phase, thus the current potential controlling described 3rd pull-up node PU3 is the first level, draw high in the current potential bootstrapping of the 3rd pull-up node PU3 described in output stage control, keep the 3rd pull-up node PU3 described in stage control and described second pull-up node PU2 to connect at reseting stage and output cut-off；
Pull-down node control unit 14, is connected with pull-down node PD, is second electrical level for controlling the current potential of described pull-down node PD at input phase, output stage and reseting stage, keeps the current potential of pull-down node PD described in stage control to be the first level in output cut-off；
First output unit 15, pull up node PU3 and described gate drive signal outfan OUT with the described 3rd respectively to be connected, for under the control of described 3rd pull-up node PU3, control to export second electrical level at gate drive signal outfan OUT described in input phase and reseting stage, and export the first level at gate drive signal outfan OUT described in the output stage；And,
Second output unit 16, is connected with described pull-down node PD and described gate drive signal outfan OUT respectively, for, under the control of described pull-down node PD, keeping gate drive signal outfan OUT described in stage control to export second electrical level in output cut-off.
By adopting the second pull-up node control unit and the 3rd pull-up node control unit, shift register cell described in the embodiment of the present invention ensures that the current potential of the 3rd pull-up node is maintained the first level at input phase, output stage and reseting stage, to improve the stability of gate drive signal output, and by pull-down node input phase, output stage and reseting stage control described pull-down node current potential be second electrical level, to increase noise resisting ability.
Concrete, described pull-down node control unit includes:
First pull-down node controls module, it is connected with described pull-down node, also pulling up node, described second pull-up node or described 3rd pull-up node to be connected with described first, the current potential controlling described pull-down node for pulling up the current potential of node, the current potential of described second pull-up node or the current potential of described 3rd pull-up node when described first when being the first level is second electrical level；
Second pull-down node controls module, is connected with described gate drive signal outfan and described pull-down node respectively, is second electrical level for controlling the current potential of described pull-down node when described gate drive signal outfan exports the first level；And,
3rd pull-down node controls module, is connected with described pull-down node, for keeping the current potential of pull-down node described in stage control to be the first level in output cut-off；
It is second electrical level that first pull-down node controls module by the first current potential pulling up node, the second pull-up node or the 3rd pull-up node control pull-down node, it is second electrical level that second pull-down node controls module by the current potential of gate drive signal outfan control pull-down node, to strengthen noise resisting ability.
In a specific embodiment, as shown in Figure 2 A, described pull-down node control unit 14 includes:
First pull-down node controls module 141, is connected with described pull-down node PD, also pulls up node PU1 with described first and is connected, and is second electrical level for pulling up the current potential controlling described pull-down node PD when the current potential of node PU1 is the first level when described first；
Second pull-down node controls module 142, is connected with described gate drive signal outfan OUT and described pull-down node PD respectively, is second electrical level for controlling the current potential of described pull-down node PD when described gate drive signal outfan OUT exports the first level；And,
3rd pull-down node controls module 143, is connected with described pull-down node PD, for keeping the current potential of pull-down node PD described in stage control to be the first level in output cut-off.
In another specific embodiment, as shown in Figure 2 B, described pull-down node control unit 14 includes:
First pull-down node controls module 141, is connected with described pull-down node PD, also pulls up node PU2 with described second and is connected, and is second electrical level for pulling up the current potential controlling described pull-down node PD when the current potential of node PU2 is the first level when described second；
Second pull-down node controls module 142, is connected with described gate drive signal outfan OUT and described pull-down node PD respectively, is second electrical level for controlling the current potential of described pull-down node PD when described gate drive signal outfan OUT exports the first level；And,
3rd pull-down node controls module 143, is connected with described pull-down node PD, for keeping the current potential of pull-down node PD described in stage control to be the first level in output cut-off.
In another specific embodiment, described pull-down node control unit 14 includes:
First pull-down node controls module 141, is connected with described pull-down node PD, also pulls up node PU3 with the described 3rd and is connected, and is second electrical level for pulling up the current potential controlling described pull-down node PD when the current potential of node PU3 is the first level when the described 3rd；
Second pull-down node controls module 142, is connected with described gate drive signal outfan OUT and described pull-down node PD respectively, is second electrical level for controlling the current potential of described pull-down node PD when described gate drive signal outfan OUT exports the first level；And,
3rd pull-down node controls module 143, is connected with described pull-down node PD, for keeping the current potential of pull-down node PD described in stage control to be the first level in output cut-off.
The first pull-down node control module 142 that differs only in of the embodiment shown in Fig. 2 A of the present invention, Fig. 2 B, Fig. 2 C is to be connected with the first pull-up node PU1, the second pull-up node PU2 or the 3rd pull-up node PU3.
Concrete, described first pull-down node controls module and includes: the first pull-down node controls transistor, grid pulls up node, described second pull-up node or described 3rd pull-up node and is connected with described first, and the first pole is connected with described pull-down node, and the second pole is connected with second electrical level outfan；
Described second pull-down node controls module and includes: the second pull-down node controls transistor, and grid is connected with described gate drive signal outfan, and the first pole is connected with described pull-down node, and the second pole is connected with described second electrical level outfan；
Described 3rd pull-down node controls module and includes: the 3rd pull-down node controls transistor, and grid and the first pole are all connected with the first clock signal input terminal, and the second pole is connected with described pull-down node；And, pull-down node maintains electric capacity, and the first end is connected with described pull-down node, and the second end is connected with described second electrical level outfan.
As shown in Figure 3A, the first pull-down node controls module and includes 141: the first pull-down node control transistor M1, and grid pulls up node PU1 with described first and is connected, and the first pole is connected with described pull-down node PD, and the second pole is connected with second electrical level outfan；
Described second electrical level outfan output second electrical level V2.
In the embodiment as shown in fig. 3 a, M1 is n-type transistor, and now second electrical level V2 can be low level VGL, controls pull-down node PD when the first current potential pulling up node PU1 is high level and accesses low level VGL.But M1 can also be p-type transistor when practical operation.
As shown in Figure 3 B, the first pull-down node controls module and includes 141: the first pull-down node control transistor M1, and grid pulls up node PU2 with described second and is connected, and the first pole is connected with described pull-down node PD, and the second pole is connected with second electrical level outfan；
Described second electrical level outfan output second electrical level V2.
M1 is n-type transistor in the embodiment shown in figure 3b, and now second electrical level V2 can be low level VGL, controls pull-down node PD when the second current potential pulling up node PU2 is high level and accesses low level VGL.But M1 can also be p-type transistor when practical operation.
As shown in Figure 3 C, the first pull-down node controls module and includes 141: the first pull-down node control transistor M1, and grid pulls up node PU3 with the described 3rd and is connected, and the first pole is connected with described pull-down node PD, and the second pole is connected with second electrical level outfan；
Described second electrical level outfan output second electrical level V2.
In the embodiment shown in Fig. 3 C, M1 is n-type transistor, and now second electrical level V2 can be low level VGL, controls pull-down node PD when the 3rd current potential pulling up node PU3 is high level and accesses low level VGL.But M1 can also be p-type transistor when practical operation.
The grid differing only in M1 of the embodiment shown in Fig. 3 A, Fig. 3 B, Fig. 3 C connects with the first pull-up node PU1, the second pull-up node PU2 or the 3rd pull-up node PU3.
Concrete, described second pull-up node control unit includes:
First pull-up controls transistor, and grid pulls up node with described first and is connected, and the second pole pulls up node with described second and is connected；
Second pull-up controls transistor, and grid and the first pole are all connected with the first level output end, and the first pole that the second pole controls transistor with described first pull-up is connected；
3rd pull-up controls transistor, and grid is connected with described pull-down node, and the first pole pulls up node with described second and is connected, and the second pole is connected with second electrical level outfan；And,
Pull-up maintains electric capacity, and the first end pulls up node with described second and is connected, and the second end is connected with second electrical level outfan.
Concrete, described first output unit includes: the first output transistor, and grid pulls up node with the described 3rd and is connected, and the first pole is connected with second clock signal input part, and the second pole is connected with described gate drive signal outfan.
When practical operation, the first clock signal can postpone two clock cycle than second clock signal.
Concrete, described 3rd pull-up node control module includes: the 4th pull-up controls transistor, grid and the first level output end and connects, and the first pole pulls up node with the described 3rd and is connected, and the second pole pulls up node with described second and is connected.
Concrete, described second output unit includes: the second output transistor, and grid is connected with described pull-down node, and the first pole is connected with described gate drive signal outfan, and the second pole is connected with second electrical level outfan.
Concrete, as shown in Figure 4, described first pull-up node control unit 11 includes:
Input module 111, it is connected with described input INPUT, described first pull-up node PU1 and the first scanning voltage signal output part CN respectively, is connected with described first scanning voltage signal output part CN for controlling described first pull-up node PU1 when being inputted the first level by described input INPUT；And,
Reseting module 112, it is connected with described reset terminal RESET, described first pull-up node PU1 and the second scanning voltage signal output part CNB respectively, is connected with described second scanning voltage signal output part CNB for controlling described first pull-up node PU1 when being inputted the first level by described reset terminal RESET；
When forward scan, described first scanning voltage signal output part CN exports the first level, and described second scanning voltage signal output part CNB exports second electrical level；
When reverse scan, described first scanning voltage signal output part CN exports second electrical level, and described second scanning voltage signal output part CNB exports the first level.
In the embodiment shown in fig. 4, the first scanning voltage signal of CN output and the second scanning voltage signal of CNB output are the control signal controlling forward scan or reverse scan.
Concrete, described input module includes: input transistors, and grid is connected with described input, and the first pole is connected with described first scanning voltage signal output part, and the second pole pulls up node with described first and is connected；
Described reseting module includes: reset transistor, and grid is connected with described reset terminal, and the first pole pulls up node with described first and is connected, and the second pole is connected with described second scanning voltage signal output part.
Below by three specific embodiments, shift register cell of the present invention is described.
As shown in Figure 5, first specific embodiment of shift register cell of the present invention, including gate drive signal outfan OUT, described shift register cell also includes the first pull-up node control unit, the second pull-up node control unit the 12, the 3rd pulls up node control unit 13, pull-down node control unit, the first output unit 15 and the second output unit 16；
Described pull-down node control unit includes the first pull-down node and controls module the 141, second pull-down node control module 142 and the 3rd pull-down node control module 143；
Described first pull-down node controls module 141 and includes: the first pull-down node controls transistor M1, and grid pulls up node PU1 with described first and is connected, and source electrode is connected with described pull-down node PD, and drain electrode is connected with low level output end；Described low level output end output low level VGL；
Described second pull-down node controls module 142 and includes: the second pull-down node controls transistor M2, and grid is connected with described gate drive signal outfan OUT, and source electrode is connected with described pull-down node PD, and drain electrode is connected with low level output end；
Described 3rd pull-down node controls module 143 and includes: the 3rd pull-down node controls transistor M3, grid and drain electrode and is all connected with the first clock signal input terminal, and source electrode is connected with described pull-down node；And,
Pull-down node maintains electric capacity C0, and the first end is connected with described pull-down node PD, and the second end is connected with described low level output end；
The first clock signal CK1 is inputted by described first clock signal input terminal；
Described first pull-up node control unit includes input module 111 and reseting module 112；
Described input module 111 includes: input transistors MI, and grid is connected with described input INPUT, and drain electrode is connected with described first scanning voltage signal output part, and source electrode pulls up node with described first and is connected；
Described first scanning voltage signal output part exports the first scanning voltage signal CN；
Described reseting module 112 includes: reset transistor MR, and grid is connected with described reset terminal RESET, and source electrode pulls up node PU1 with described first and is connected, and drain electrode is connected with described second scanning voltage signal output part；
The second scanning voltage signal CNB is exported by described second scanning voltage signal output part；
Described second pull-up node control unit 12 includes:
First pull-up controls transistor M4, and grid pulls up node PU1 with described first and is connected, and source electrode pulls up node with described second and is connected；
Second pull-up controls transistor M5, and grid and the first pole are all connected with high level output end, and the first pole that the second pole controls transistor with described first pull-up is connected；
3rd pull-up controls transistor M6, and grid is connected with described pull-down node PD, and source electrode pulls up node PU2 with described second and is connected, and drain electrode is connected with low level output end；And,
Pull-up maintains electric capacity C1, and the first end pulls up node PU2 with described second and is connected, and the second end is connected with low level output end；
Described high level output end output high level VGH；
Described 3rd pull-up node control module 13 includes: the 4th pull-up controls transistor M7, and grid is connected with high level output end, drains and is connected with described 3rd pull-up node PU3, and source electrode pulls up node PU2 with described second and is connected；
Described first output unit 15 includes: the first output transistor M8, and grid pulls up node PU3 with the described 3rd and is connected, and drain electrode is connected with second clock signal input part, and source electrode is connected with described gate drive signal outfan OUT；
Second clock signal CK2 is inputted by described second clock signal input part；
Described second output unit 16 includes: the second output transistor M9, and grid is connected with described pull-down node PD, and source electrode is connected with described gate drive signal outfan, and drain electrode is connected with low level output end.
In the first specific embodiment shown in Fig. 5, all of transistor is all n-type transistor.
As shown in Figure 6, the first specific embodiment of shift register cell of the present invention operationally,
When forward scan, INPUT connects with gate drive signal outfan OUT (N-1) of adjacent upper level shift register cell, RESET connects with gate drive signal outfan OUT (N+1) of adjacent next stage shift register cell, CN is high level, and CNB is low level；
Input phase t1 in each display cycle, the input signal accessed by input INPUT is high level, the reset signal accessed by reset terminal RESET is low level, CK2 is low level, CK1 is low level, CN is high level, CNB is low level, MI opens, so that the current potential of PU1 is high level, M4 opens, M5 opens, VGH is C1 charging by M5 and M4, the current potential of PU2 is high level, M7 turns on, thus the current potential of PU3 is also high level, and owing to the current potential of PU1 is that high level is thus opening M1, with by the current potential of PD down for VGL, now M8 opens, CK2 accesses OUT, then OUT output low level；
At the output stage t2 of each display cycle, input INPUT the input signal accessed is low level, reset terminal RESET the reset signal accessed is low level, CK2 is high level, CK1 is low level, and MI closes, and the current potential of PU1 and the current potential of PU2 remain high level, M8 stays open, the current potential of PU3 raises further owing to the bootstrapping of M8 draws high effect, and CK2 accesses OUT, OUT and exports high level, while now M1 stays open, M2 opens, then the current potential of PD is maintained low level；M7 owing to self is closed by the upset of gate source voltage difference, has been effectively ensured the high potential of PU3 after the current potential of PU3 raises；In addition control M1 by PU1 to open and drag down the current potential of PD, control M2 by OUT simultaneously and open and the current potential that drags down PD, adopt duplex feedback to significantly increase the noise resisting ability of circuit so that gate drive signal exports more steady；
M8 manufactured size compared with other transistors is relatively big, and namely M8 self has bigger parasitic capacitance, therefore when the source voltage of M8 and the drain voltage of M8 change, the grid voltage of M8 may occur from lifting phenomenon；
Reseting stage t3 in each display cycle, the input signal accessed by input INPUT is low level, the reset signal accessed by reset terminal RESET is high level, CK2 is low level, CK1 is low level, MR opens, the current potential of PU1 is pulled low as low level, M1 and M4 closes, the current potential of PU2 keeps high level, and the current potential of PU3 falls after rise along with the change of the voltage of CK2, but the current potential of PU3 is maintained as high level, the gate drive signal of OUT output becomes low level along with the change of CK2 voltage, and the current potential of PD remains low level；
Output in each display cycle ends maintenance stage t4, the input signal accessed by input INPUT is low level, the reset signal accessed by reset terminal RESET is high level, CK2 is low level, CK1 is high level, MR closes, the current potential of PU1 remains low level, M3 opens, and CK1 is charged to C0 by M3, and the current potential of PD raises, thus M9 and M6 opens, the current potential of PU2 and the current potential of PU3 are pulled low electric discharge owing to M6 opens, and M8 closes, and VGL continues to keep low level so that the gate drive signal of OUT output by M9 simultaneously；Wherein, C0 has been effectively ensured the high potential of PD.
When the first specific embodiment of shift register cell of the present invention is when reverse scan, CN need to be set to low level, CNB is set to high level.
As seen from Figure 6, CK1 postpones two clock cycle than CK2.
First specific embodiment of shift register cell of the present invention is by using 11 NMOS (N-Metal-Oxide-Semiconductor, N-type Metal-oxide-semicondutor) TFT (ThinFilmTransistor, thin film transistor (TFT)) and two electric capacity composition 11T2C circuit, drive the grid of display；First specific embodiment of shift register cell of the present invention increases M4, M5 and M7, has been effectively ensured the high level that the current potential of PU3 produces due to boot strap；In addition PU1, OUT drag down the current potential of PD by the duplex feedback of M1, M2, hence it is evident that add the noise resisting ability of circuit so that export more steady；Thus solving the technical problem that conventional GOA circuit noise is excessive.
The circuit diagram of the second specific embodiment of shift register cell of the present invention is as shown in Figure 7, the circuit diagram of the 3rd specific embodiment of shift register cell of the present invention is as shown in Figure 8, differing only in of first specific embodiment of the second specific embodiment of shift register cell of the present invention and shift register cell of the present invention as shown in Figure 5: the grid of M1 is connected with PU2, and namely PU2 drags down the current potential of PD by M1；3rd specific embodiment of shift register cell of the present invention differs only in the first specific embodiment of shift register cell of the present invention as shown in Figure 5: the grid of M1 is connected with PU3, and namely PU3 drags down the current potential of PD by M1.
Shift register cell described in the embodiment of the present invention has the advantages that output noise is low, stability is high, it is possible to be greatly improved the yield of display floater.
As it is shown in figure 9, the driving method of the shift register cell described in the embodiment of the present invention, including:
Input step S1: at the input phase of each display cycle, it is the first level that second pull-up node control unit controls the current potential of the second pull-up node under the first control pulling up node, 3rd pull-up node control unit controls the 3rd pull-up node and is connected with described second pull-up node, thus the current potential controlling described 3rd pull-up node is the first level, it is second electrical level that pull-down node control unit controls the current potential of pull-down node, and the first output unit controls described gate drive signal outfan output second electrical level under the described 3rd control pulling up node；
Output step S2: in the output stage of each display cycle, it is the first level that second pull-up node control unit controls the current potential of described second pull-up node under the described first control pulling up node, 3rd pull-up node control unit controls the current potential bootstrapping of described 3rd pull-up node to be drawn high, it is second electrical level that pull-down node control unit controls the current potential of described pull-down node, and the first output unit controls described gate drive signal outfan under the described 3rd control pulling up node and exports the first level；
Reset process S3: at the reseting stage of each display cycle, it is the first level that second pull-up node control unit controls to maintain the current potential of described second pull-up node, 3rd pull-up node control unit controls described 3rd pull-up node and described second pull-up node connects, it is second electrical level that pull-down node control unit controls the current potential of described pull-down node, and the first output unit controls described gate drive signal outfan output second electrical level under the described 3rd control pulling up node；
Output cut-off keeps step S4: the output in each display cycle ends the maintenance stage, it is second electrical level that second pull-up node control unit controls the current potential of described second pull-up node under the control of described pull-down node, 3rd pull-up node control unit controls described 3rd pull-up node and described second pull-up node connects, pull-down node control unit controls described gate drive signal outfan and exports the first level, second output unit, under the control of described pull-down node, keeps gate drive signal outfan output second electrical level described in stage control in output cut-off.
By adopting the second pull-up node control unit and the 3rd pull-up node control unit, the driving method of the shift register cell described in the embodiment of the present invention ensures that the current potential of the 3rd pull-up node is maintained the first level at input phase, output stage and reseting stage, to improve the stability of gate drive signal output, and by pull-down node input phase, output stage and reseting stage control described pull-down node current potential be second electrical level, to increase noise resisting ability.
Concrete, input phase in a display cycle, it is that second electrical level step specifically includes that described pull-down node control unit controls the current potential of pull-down node: the first pull-down node controls module under the described first control pulling up node, described second pull-up node or described 3rd pull-up node, and the current potential controlling described pull-down node is second electrical level；
The output stage in each display cycle, it is that second electrical level step specifically includes that described pull-down node control unit controls the current potential of pull-down node: the first pull-down node controls module under the described first control pulling up node, described second pull-up node or described 3rd pull-up node, the current potential controlling described pull-down node is second electrical level, second pull-down node controls under the control of the gate drive signal that module export at described gate drive signal outfan, and the current potential of the described pull-down node of control is second electrical level further；
Reseting stage in each display cycle, it is that second electrical level step specifically includes that described pull-down node control unit controls the current potential of pull-down node: the first pull-down node controls module under the described second control pulling up node or described 3rd pull-up node, and the current potential controlling described pull-down node is second electrical level.
Concrete, the driving method of shift register cell of the present invention also includes: at the input phase of each display cycle, and it is the first level that the first pull-up node control unit controls the current potential of described first pull-up node；
At the reseting stage of each display cycle, it is second electrical level that the first pull-up node control unit controls the current potential of described first pull-up node.
Gate driver circuit described in the embodiment of the present invention includes multistage above-mentioned shift register cell.
Display device described in the embodiment of the present invention includes above-mentioned gate driver circuit.
The above is the preferred embodiment of the present invention; it should be pointed out that, for those skilled in the art, under the premise without departing from principle of the present invention; can also making some improvements and modifications, these improvements and modifications also should be regarded as protection scope of the present invention.
Claims (14)
1. a shift register cell, including gate drive signal outfan, it is characterised in that described shift register cell also includes:
First pull-up node control unit, is connected with input, reset terminal and the first pull-up node respectively；
Second pull-up node control unit, it is connected with pull-down node, described first pull-up node and the second pull-up node respectively, it is the first level for controlling the current potential of described second pull-up node under the described first control pulling up node at input phase and output stage, the current potential controlling to maintain described second pull-up node at reseting stage is the first level, and the current potential controlling described second pull-up node in the output cut-off maintenance stage under the control of described pull-down node is second electrical level；3rd pull-up node control unit, pull up node respectively with described second and the 3rd pull-up node is connected, for controlling described 3rd pull-up node and the second pull-up node connection at input phase, thus the current potential controlling described 3rd pull-up node is the first level, draw high in the current potential bootstrapping of the 3rd pull-up node described in output stage control, keep the 3rd pull-up node described in stage control and described second pull-up node to connect at reseting stage and output cut-off；
Pull-down node control unit, is connected with pull-down node, is second electrical level for controlling the current potential of described pull-down node at input phase, output stage and reseting stage, keeps the current potential of pull-down node described in stage control to be the first level in output cut-off；
First output unit, pull up node with the described 3rd respectively and described gate drive signal outfan is connected, for under the control of described 3rd pull-up node, control at gate drive signal outfan output second electrical level described in input phase and reseting stage, and export the first level at gate drive signal outfan described in the output stage；And,
Second output unit, is connected with described pull-down node and described gate drive signal outfan respectively, for, under the control of described pull-down node, keeping gate drive signal outfan output second electrical level described in stage control in output cut-off.
2. shift register cell as claimed in claim 1, it is characterised in that described pull-down node control unit includes:
First pull-down node controls module, it is connected with described pull-down node, also pulling up node, described second pull-up node or described 3rd pull-up node to be connected with described first, the current potential controlling described pull-down node for pulling up the current potential of node, the current potential of described second pull-up node or the current potential of described 3rd pull-up node when described first when being the first level is second electrical level；
Second pull-down node controls module, is connected with described gate drive signal outfan and described pull-down node respectively, is second electrical level for controlling the current potential of described pull-down node when described gate drive signal outfan exports the first level；And,
3rd pull-down node controls module, is connected with described pull-down node, for keeping the current potential of pull-down node described in stage control to be the first level in output cut-off.
3. shift register cell as claimed in claim 2, it is characterized in that, described first pull-down node controls module and includes: the first pull-down node controls transistor, grid pulls up node, described second pull-up node or described 3rd pull-up node and is connected with described first, first pole is connected with described pull-down node, and the second pole is connected with second electrical level outfan；
Described second pull-down node controls module and includes: the second pull-down node controls transistor, and grid is connected with described gate drive signal outfan, and the first pole is connected with described pull-down node, and the second pole is connected with described second electrical level outfan；
Described 3rd pull-down node controls module and includes: the 3rd pull-down node controls transistor, and grid and the first pole are all connected with the first clock signal input terminal, and the second pole is connected with described pull-down node；And, pull-down node maintains electric capacity, and the first end is connected with described pull-down node, and the second end is connected with described second electrical level outfan.
4. shift register cell as claimed in claim 1, it is characterised in that described second pull-up node control unit includes:
First pull-up controls transistor, and grid pulls up node with described first and is connected, and the second pole pulls up node with described second and is connected；
Second pull-up controls transistor, and grid and the first pole are all connected with the first level output end, and the first pole that the second pole controls transistor with described first pull-up is connected；
3rd pull-up controls transistor, and grid is connected with described pull-down node, and the first pole pulls up node with described second and is connected, and the second pole is connected with second electrical level outfan；And,
Pull-up maintains electric capacity, and the first end pulls up node with described second and is connected, and the second end is connected with second electrical level outfan.
5. shift register cell as described in any claim in Claims 1-4, it is characterized in that, described first output unit includes: the first output transistor, grid pulls up node with the described 3rd and is connected, first pole is connected with second clock signal input part, and the second pole is connected with described gate drive signal outfan.
6. shift register cell as claimed in claim 5, it is characterized in that, described 3rd pull-up node control module includes: the 4th pull-up controls transistor, grid and the first level output end and connects, first pole pulls up node with the described 3rd and is connected, and the second pole pulls up node with described second and is connected.
7. shift register cell as claimed in claim 6, it is characterized in that, described second output unit includes: the second output transistor, and grid is connected with described pull-down node, first pole is connected with described gate drive signal outfan, and the second pole is connected with second electrical level outfan.
8. shift register cell as claimed in claim 6, it is characterised in that described first pull-up node control unit includes:
Input module, is connected with described input, described first pull-up node and the first scanning voltage signal output part respectively, is connected with described first scanning voltage signal output part for controlling described first pull-up node when being inputted the first level by described input；And,
Reseting module, is connected with described reset terminal, described first pull-up node and the second scanning voltage signal output part respectively, is connected with described second scanning voltage signal output part for controlling described first pull-up node when being inputted the first level by described reset terminal；
Described input connects with the gate drive signal outfan of adjacent upper level shift register cell, and described reset terminal connects with the gate drive signal outfan of adjacent next stage shift register cell；
When forward scan, described first scanning voltage signal output part exports the first level, described second scanning voltage signal output part output second electrical level；
When reverse scan, described first scanning voltage signal output part output second electrical level, described second scanning voltage signal output part exports the first level.
9. shift register cell as claimed in claim 8, it is characterized in that, described input module includes: input transistors, and grid is connected with described input, first pole is connected with described first scanning voltage signal output part, and the second pole pulls up node with described first and is connected；
Described reseting module includes: reset transistor, and grid is connected with described reset terminal, and the first pole pulls up node with described first and is connected, and the second pole is connected with described second scanning voltage signal output part.
10. the driving method of a shift register cell, it is characterised in that including:
Input phase in each display cycle, it is the first level that second pull-up node control unit controls the current potential of the second pull-up node under the first control pulling up node, 3rd pull-up node control unit controls the 3rd pull-up node and is connected with described second pull-up node, thus the current potential controlling described 3rd pull-up node is the first level, it is second electrical level that pull-down node control unit controls the current potential of pull-down node, and the first output unit control gate under the described 3rd control pulling up node drives signal output part output second electrical level；
The output stage in each display cycle, it is the first level that second pull-up node control unit controls the current potential of described second pull-up node under the described first control pulling up node, 3rd pull-up node control unit controls the current potential bootstrapping of described 3rd pull-up node to be drawn high, it is second electrical level that pull-down node control unit controls the current potential of described pull-down node, and the first output unit controls described gate drive signal outfan under the described 3rd control pulling up node and exports the first level；
Reseting stage in each display cycle, it is the first level that second pull-up node control unit controls to maintain the current potential of described second pull-up node, 3rd pull-up node control unit controls described 3rd pull-up node and described second pull-up node connects, it is second electrical level that pull-down node control unit controls the current potential of described pull-down node, and the first output unit controls described gate drive signal outfan output second electrical level under the described 3rd control pulling up node；
Output in each display cycle ends the maintenance stage, it is second electrical level that second pull-up node control unit controls the current potential of described second pull-up node under the control of described pull-down node, 3rd pull-up node control unit controls described 3rd pull-up node and described second pull-up node connects, it is the first level that pull-down node control unit controls the current potential of described pull-down node, second output unit, under the control of described pull-down node, keeps gate drive signal outfan output second electrical level described in stage control in output cut-off.
11. the driving method of shift register cell as claimed in claim 10, it is characterized in that, input phase in each display cycle, it is that second electrical level step specifically includes that described pull-down node control unit controls the current potential of pull-down node: the first pull-down node controls module under the described first control pulling up node, described second pull-up node or described 3rd pull-up node, and the current potential controlling described pull-down node is second electrical level；
The output stage in each display cycle, it is that second electrical level step specifically includes that described pull-down node control unit controls the current potential of pull-down node: the first pull-down node controls module under the described first control pulling up node, described second pull-up node or described 3rd pull-up node, the current potential controlling described pull-down node is second electrical level, second pull-down node controls under the control of the gate drive signal that module export at described gate drive signal outfan, and the current potential of the described pull-down node of control is second electrical level further；
Reseting stage in each display cycle, it is that second electrical level step specifically includes that described pull-down node control unit controls the current potential of pull-down node: the first pull-down node controls module under the described second control pulling up node or described 3rd pull-up node, and the current potential controlling described pull-down node is second electrical level.
12. the driving method of the shift register cell as described in claim 10 or 11, it is characterised in that also include: at the input phase of each display cycle, it is the first level that the first pull-up node control unit controls the current potential of described first pull-up node；
At the reseting stage of each display cycle, it is second electrical level that the first pull-up node control unit controls the current potential of described first pull-up node.
13. a gate driver circuit, it is characterised in that include multistage shift register cell as described in any claim in claim 1 to 9.
14. a display device, it is characterised in that include gate driver circuit as claimed in claim 13.
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| CN112470208A (en) * | 2019-03-28 | 2021-03-09 | 京东方科技集团股份有限公司 | Gate driving unit, gate driving method, gate driving circuit, display panel and display device |
| US11361703B2 (en) | 2019-03-28 | 2022-06-14 | Ordos Yuansheng Optoelectronics Co., Ltd. | Gate driving unit including four clock signals, gate driving method, gate driving circuit, display panel and display device |
| CN111179813A (en) * | 2020-03-18 | 2020-05-19 | 合肥京东方卓印科技有限公司 | Shifting register unit, driving method, grid driving circuit and display device |
| CN111179813B (en) * | 2020-03-18 | 2022-05-17 | 合肥京东方卓印科技有限公司 | Shifting register unit, driving method, grid driving circuit and display device |
| US11887683B2 (en) | 2020-03-18 | 2024-01-30 | Hefei Boe Joint Technology Co., Ltd. | Shift register unit, driving method, gate driving circuit and display device |
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