CN105761687A - Shift register and shift register circuit - Google Patents
Shift register and shift register circuit Download PDFInfo
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- CN105761687A CN105761687A CN201610079202.9A CN201610079202A CN105761687A CN 105761687 A CN105761687 A CN 105761687A CN 201610079202 A CN201610079202 A CN 201610079202A CN 105761687 A CN105761687 A CN 105761687A
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- 238000006073 displacement reaction Methods 0.000 claims description 20
- 230000005611 electricity Effects 0.000 claims description 15
- 239000004973 liquid crystal related substance Substances 0.000 description 22
- 238000007667 floating Methods 0.000 description 15
- 238000010586 diagram Methods 0.000 description 8
- 230000008878 coupling Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
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- 238000005516 engineering process Methods 0.000 description 1
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Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3614—Control of polarity reversal in general
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
Abstract
Shift register and shift register circuit. The shift register circuit comprises N stages of shift registers, wherein the nth stage of shift register comprises a driving circuit, a pull-up circuit and a pull-down circuit. The driving circuit outputs a gate signal of the shift register of the present stage according to a main pull-up signal outputted from the (n. The pull-up circuit outputs a main pull-up signal and an auxiliary pull-up signal of the shift register of the current stage to the (n +1) th stage shift register, and outputs a pre-charged pull-up signal of the shift register of the current stage to the (n +1+ M) th stage shift register. The pull-down circuit pulls down the gate signal and the internal power-saving potential according to the potentials of the (n.
Description
Technical field
The present invention relates to a kind of shift register circuit, polarity inversion can be supported particularly to one and pixel preliminary filling is provided
The shift register circuit of Electricity Functional.
Background technology
In order to avoid the liquid crystal molecule in liquid crystal display because being fixed on for a long time under the bias of identical polar, cause
The characteristic of liquid crystal molecule fails and causes image quality to decline, and therefore prior art liquid crystal display often can utilize polarity inversion
Method, it is to avoid liquid crystal molecule accepts the bias of identical polar for a long time.For example, the liquid crystal display of prior art can be
After each frame period terminates, the bias polarity that reversion liquid crystal molecule is accepted.And in the liquid crystal display of large-size, for
Avoiding causing with internal signal crosstalk (crosstalk) when inverting acute, therefore prior art it is also proposed row reversion such as
(column inversion) or the mode of some reversion (dot inversion) so that adjacent two row or wantonly two adjacent pixels
Liquid crystal molecule can receive the bias of opposite polarity.
After a polarity reversal, owing to liquid crystal molecule deflection angle is contrary, the therefore turnaround time required for liquid crystal molecule
It is likely to increase therewith.In order to avoid turning to of liquid crystal molecule does not catches up with the speed that content frame updates, prior art also can be led to
Crossing the mode of precharge, allow pixel before accepting correct data voltage, receiving in advance will inclined in order to the polarity that deflects
Pressure so that pixel can turn in advance, so can reduce the turnaround time required for liquid crystal molecule.In the prior art, if
Liquid crystal display is to carry out polarity inversion in the way of row reversion, then owing to, in row reversion, the pixel with string will be by phase
The bias of same polarity, therefore the shift register circuit in liquid crystal display can be in output signal to open one-row pixels
Time, the most also signal is exported to next line pixel to be pre-charged the liquid crystal molecule in next line pixel.
If but liquid crystal display is to carry out polarity inversion in the way of a reversion, then all can due to wantonly two adjacent pixels
Receive the bias of opposed polarity, therefore cannot be suitable for the shift register circuit of the above-mentioned liquid crystal display in row reversion.Additionally,
Liquid crystal display is the different demands meeting various application, when intended polarity inverts, it is also possible to come in the way of other arrange
Carry out polarity inversion so that the function of precharge is difficult to implement.The most how to allow shift register circuit can support to comprise row anti-
Turning and the pre-charging functions of other arrangement modes, becoming one has problem to be solved.
Summary of the invention
One embodiment of the invention provides a kind of shift register, and shift register comprises primary nodal point, secondary nodal point, drives
Galvanic electricity road, pull-up circuit and pull-down circuit.Primary nodal point can receive the auxiliary pull-up signal of previous stage shift register output, the
Two nodes, can receive the main pull-up signal of previous stage shift register output and the pre-of front (M+1) level shift register output
Filling with and draw signal, M is the integer more than 3.
Drive circuit is coupled to secondary nodal point, in order to the current potential according to secondary nodal point and clock signal Output Shift Register
Signal.Pull-up circuit comprises the first switch and pull-up output circuit.First switch has the first end, the second end and control
End, the first end of the first switch receives clock signal, the second end of the first switch is coupled to the 3rd node, and the control of the first switch
End processed is coupled to primary nodal point.Pull-up output circuit is coupled to the 3rd node, in order to the main pull-up letter of Output Shift Register
Number, preliminary filling pull-up signal and auxiliary pull-up signal.
Pull-down circuit is coupled to primary nodal point, secondary nodal point and the 3rd node, in order to according to front (M-2) level shift register
The current potential of the 3rd node and the drop-down primary nodal point of current potential of the 3rd node of rear two grades of shift registers and the electricity of secondary nodal point
Position, and according to the current potential of secondary nodal point and the current potential pulldown gate signal of secondary nodal point of previous stage shift register, first segment
The current potential of the 3rd node of point, the secondary nodal point of shift register and shift register.
Another embodiment of the present invention provides a kind of shift register circuit, and shift register circuit is according to being high potential during difference
M clock signal export multiple signals, shift register circuit comprises N level shift register.In N level shift register
N-th grade of shift register comprises: primary nodal point, secondary nodal point, drive circuit, pull-up circuit and pull-down circuit.M is more than 3
Integer, N is the integer of the twice more than M, and n is the integer more than M.N level shift register differs two shift LDs of M level
Device can be according to clock signal output signal identical in M clock signal.
Primary nodal point receives the auxiliary pull-up signal of (n-1) level shift register output.Secondary nodal point receives (n-1)
The main pull-up signal of level shift register output and the preliminary filling pull-up signal of (n-1-M) level shift register output.Drive
Circuit is coupled to the secondary nodal point of n-th grade of shift register, in order to the secondary nodal point according to n-th grade of shift register current potential and
The signal of one of M clock signal clock signal n-th grade of shift register of output.
Pull-up circuit comprises the first switch and pull-up output circuit.First switch has the first end, the second end and controls end,
First end of the first switch receives clock signal, the second end of the first switch is coupled to the 3rd node, and the control of the first switch
End is coupled to the primary nodal point of n-th grade of shift register.Pull-up output circuit is coupled to Section three of n-th grade of shift register
Point, in order to export the main pull-up signal of n-th grade of shift register, preliminary filling pull-up signal and auxiliary pull-up signal；And
Pull-down circuit is coupled to the primary nodal point of n-th grade of shift register, secondary nodal point and the 3rd node, in order to according to
(n-M+2) current potential of the 3rd node of the current potential of the 3rd node of level shift register and (n+2) level shift register is drop-down
The primary nodal point of n-th grade of shift register and the current potential of secondary nodal point, and the electricity of the secondary nodal point according to n-th grade of shift register
The signal of the drop-down n-th grade of shift register of current potential of the secondary nodal point of position and (n-1) level shift register and n-th grade of shifting
The primary nodal point of bit register, secondary nodal point and the current potential of the 3rd node.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of the shift register circuit of one embodiment of the invention.
Fig. 2 is the schematic diagram of the shift register of the shift register circuit of Fig. 1 of one embodiment of the invention.
Fig. 3 is the time sequential routine figure of the shift register of Fig. 2 of one embodiment of the invention.
Fig. 4 is the schematic diagram of the shift register of the shift register circuit of Fig. 1 of another embodiment of the present invention.
Fig. 5 is the schematic diagram of the shift register of the shift register circuit of Fig. 1 of another embodiment of the present invention.
[symbol description]
10 shift register circuits
1001、1002、1003、1004、1005、1006, shift register
1007、1008、1009、10010、10011、10012、
100n、100’n
HC1, HC2, HC3, HC4 clock signal
The initial signal of SI
SQ5、SQ6、SQn、SQ(n-1)Mainly pull up signal
SR5、SR6、SRn、SR(n-1)Auxiliary pull-up signal
SQ’1、SQ’6、SQ’n、SQ’(n-1-M)Preliminary filling pull-up signal
R6、Rn、Rm、R(m-1)Primary nodal point
Q5、Q6、Qn、Q(n-1)Secondary nodal point
T4、T6、T8、Tn、T(n+2)、T(n-M+2)3rd node
110 drive circuits
120 pull-up circuits
122 pull-up output circuits
130 pull-down circuits
132 first drop-down unit
134 second drop-down unit
LC1 first selects signal
LC2 second selects signal
VGH high potential
VGL electronegative potential
C1 electric capacity
M1 first switchs
M2A, M2B second switch
M3A, M3B the 3rd switchs
M4A, M4B the 4th switchs
M5 the 5th switchs
M6 the 6th switchs
M7 the 7th switchs
M8 the 8th switchs
M9 the 9th switchs
M10 the tenth switchs
M11 the 11st switchs
M12 twelvemo is closed
M13 the 13rd switchs
M14 the 14th switchs
M15 the 15th switchs
M16 sixteenmo closes
M17 the 17th switchs
M18 eighteenmo closes
M19 the 19th switchs
M20 the 20th switchs
M21 the 21st switchs
M22 the second twelvemo is closed
M23 the 23rd switchs
M24 the 24th switchs
M25 the 25th switchs
M26 the second sixteenmo closes
M27 the 27th switchs
M28 the second eighteenmo closes
Gn、G6Signal
First period of TP1
Second period of TP2
TP3 the 3rd period
TP4 the 4th period
TP5 the 5th period
TP6 the 6th period
TP7 the 7th period
TP8 the 8th period
Detailed description of the invention
Fig. 1 is the schematic diagram of the shift register circuit 10 of one embodiment of the invention.Shift register circuit 10 can comprise N level and move
Bit register, and multiple signals G can be exported according to M clock signal during difference being high potential1To GN, M is more than 3
Integer, and the integer that N is the twice more than M.In the embodiment in figure 1, M is 4 and N to be 12.
Fig. 3 comprises the sequential chart of four clock signal HC1 to HC4 that shift register circuit 10 is received.In figure 3, time
Clock signal HC1 to HC4 has the identical cycle, and can be become high potential VGH, and clock signal from electronegative potential VGL the most in turn
HC1 to HC4 is the time mutual non-overlapping of high potential VGH.In FIG, every one-level shift register can differ from it by the shifting of M level
Bit register receives identical clock signal, such as first order shift register 1001With level V shift register 1005Together with
Sample receives clock signal HC1, and second level shift register 1002With the 6th grade of shift register 1006When can receive equally
Clock signal HC2, and the rest may be inferred.Certainly, in other embodiments of the invention, shift register circuit is also dependent on varying number
Clock signal, such as 8,16 clock signals, export signal.
Fig. 2 is n-th grade of shift register 100 in shift register 10nSchematic diagram, n is the integer more than M.N-th grade
Shift register 100nComprise primary nodal point Rn, secondary nodal point Qn, drive circuit 110, pull-up circuit 120 and pull-down circuit 130.
Primary nodal point RnReceive (n-1) level shift register (i.e. n-th grade shift register 100nPrevious stage displacement post
Storage) export auxiliary pull-up signal SR(n-1).Secondary nodal point QnReceive the main pull-up of (n-1) level shift register output
Signal SQ(n-1)And (n-1-M) level shift register (i.e. n-th grade shift register 100nBefore (M+1) level shift register)
The preliminary filling pull-up signal SQ ' of output(n-1-M).For example, in the case of n is 6, (n-1-M) level shift register is
First order shift register 100 in Fig. 11。
Drive circuit 110 is coupled to n-th grade of shift register 100nSecondary nodal point Qn, and can be according to n-th grade of shift LD
Device 100nSecondary nodal point QnCurrent potential and n-th grade of shift register 100nReceived clock signal n-th grade of displacement of output is posted
Storage 100nSignal Gn.In shift register circuit 10, the 6th grade of shift register 1006Received clock signal
For HC2, and to the 5th grade of shift register 1005For, the 5th grade of shift register 1005Received clock signal is then
HC1。
Pull-up circuit 120 comprises the first switch M1 and pull-up output circuit 122.First switch M1 have the first end, second
End and control end.First end of the first switch M1 receives clock signal, and second end of the first switch M1 is coupled to n-th grade of displacement and posts
Storage 100nThe 3rd node Tn, and the control end of the first switch M1 is coupled to n-th grade of shift register 100nPrimary nodal point
Rn.Pull-up output circuit 122 is coupled to n-th grade of shift register 100nThe 3rd node Tn, in order to export n-th grade of shift LD
Device 100nMain pull-up signal SQn, preliminary filling pull-up signal SQ 'nAnd auxiliary pull-up signal SRn。
In fig. 2, pull-up output circuit 122 comprises second switch M2A to the 4th switch M4A.Second switch M2A has
One end, the second end and control end, first end of second switch M2A is coupled to n-th grade of shift register 100nThe 3rd node Tn,
The auxiliary pull-up signal SR of second end n-th grade of shift register 100n of output of second switch M2An, and the control of second switch M2A
End processed is coupled to first end of second switch M2A.3rd switch M3A has the first end, the second end and controls end, the 3rd switch
First end of M3A is coupled to n-th grade of shift register 100nThe 3rd node Tn, second end of the 3rd switch M3A exports n-th grade
Shift register 100nMain pull-up signal SQn, and the end that controls of the 3rd switch M3A is coupled to the first of the 3rd switch M3A
End.4th switch M4A has the first end, the second end and controls end, and first end of the 4th switch M4A is coupled to n-th grade of displacement and posts
Storage 100nThe 3rd node Tn, second end n-th grade of shift register 100 of output of the 4th switch M4AnPreliminary filling pull-up signal
SQ’n, and the end that controls of the 4th switch M4A is coupled to first end of the 4th switch M4A.
Pull-down circuit 130 is coupled to n-th grade of shift register 100nPrimary nodal point Rn, secondary nodal point QnAnd the 3rd node
Tn, and can be according to (n-M+2) level shift register (that is n-th grade of shift register 100nBefore (M-2) level shift register)
The 3rd node T(n-M+2)Current potential and (n+2) level shift register (that is n-th grade of shift register 100nRear two-stage move
Bit register) the 3rd node T(n+2)Current potential come drop-down n-th grade of shift register 100nPrimary nodal point RnAnd secondary nodal point Qn
Current potential, and according to n-th grade of shift register 100nSecondary nodal point QnCurrent potential and (n-1) level shift register (that is
N level shift register 100nPrevious stage shift register) secondary nodal point Q(n-1)The drop-down n-th grade of shift register of current potential
100nSignal GnAnd n-th grade of shift register 100nPrimary nodal point Qn, secondary nodal point RnAnd the 3rd node TnCurrent potential.
Additionally, in fig. 2, n-th grade of shift register 100nMain pull-up signal SQnCan export to the displacement of (n+1) level
Depositor (that is n-th grade of shift register 100nRear stage shift register, the most in FIG, the 6th grade of shift register
1006Main pull-up signal SQ6Can export to the 7th grade of shift register 1007) secondary nodal point Q(n+1), n-th grade of shift LD
Device 100nPreliminary filling pull-up signal SQ 'nCan export to (n+1+M) level shift register (that is n-th grade of shift register 100n
(M+1) level shift register afterwards, the most in FIG, the 6th grade of shift register 1006Preliminary filling pull-up signal SQ '6Can export
To the tenth one-level shift register 10011) secondary nodal point Q(n+1+M), and n-th grade of shift register 100nAuxiliary pull-up signal
SRnCan export to (n+1) level shift register (that is n-th grade of shift register 100nRear stage shift register, such as
In FIG, the 6th grade of shift register 1006Auxiliary pull-up signal SR6Can export to the 7th grade of shift register 1007)
One node R(n+1)。
Puller circuit 130 comprises the 5th switch M5 to the 7th switch M7, the first drop-down unit 132 and second time in figure 2 the lower
Draw unit 134.5th switch M5 has the first end, the second end and controls end, and first end of the 5th switch M5 is coupled to n-th grade of shifting
Bit register 100nSecondary nodal point Qn, second end of the 5th switch M5 is in order to receive electronegative potential VGL, and the control of the 5th switch M5
End processed is coupled to (n-M+2) level shift register (that is n-th grade of shift register 100nBefore (M-2) level shift register)
The 3rd node T(n-M+2).6th switch M6 has the first end, the second end and controls end, and first end of the 6th switch M6 is coupled to
N-th grade of shift register 100nSecondary nodal point Qn, second end of the 6th switch M6 receives electronegative potential VGL, and the 6th switchs M6's
Control end and be coupled to (n+2) level shift register (that is n-th grade of shift register 100nRear two-stage shift register)
3rd node T(n+2).7th switch M7 has the first end, the second end and controls end, and first end of the 7th switch M7 is coupled to displacement
Depositor 100nPrimary nodal point Rn, the second end reception electronegative potential VGL of the 7th switch M7, and the control end coupling of the 7th switch M7
It is connected to (n+2) level shift register (that is n-th grade of shift register 100nRear two-stage shift register) the 3rd node
T(n+2)。
Additionally, in order to avoid transistor is caused characteristic to fail by fixing bias for a long time, n-th grade of displacement of Fig. 3
Depositor 100nMutually symmetrical with the first drop-down unit 132 of framework can be utilized in turn and the second drop-down unit 134 is stablized or under
Draw the current potential to internal node and output signal.
First drop-down unit 132 comprises the 8th switch M8 to the 17th and switchs M17.8th switch M8 have the first end, the
Two ends and control end, first end of the 8th switch M8 can receive the first selection signal LC1, and the control end of the 8th switch M8 couples
The first end in the 8th switch M8.9th switch M9 has the first end, the second end and controls end, the first end coupling of the 9th switch M9
It is connected to first end of the 8th switch M8, and the end that controls of the 9th switch M9 is coupled to second end of the 8th switch M8.Tenth switch
M10 have the first end, the second end and control end, the tenth switch M10 the first end be coupled to the 8th switch M8 the second end, the tenth
Second end of switch M10 can receive electronegative potential VGL, and the control end of the tenth switch M10 is coupled to (n-1) level shift register
(that is n-th grade of shift register 100nPrevious stage shift register) secondary nodal point Q(n-1).11st switch M11 has the
One end, the second end and control end, first end of the 11st switch M11 is coupled to second end of the 9th switch M9, the 11st switch
Second end of M11 can receive electronegative potential VGL, and the control end of the 11st switch M11 is coupled to (n-1) level shift register
Secondary nodal point Q(n-1).Twelvemo is closed M12 and is had the first end, the second end and control end, and twelvemo is closed first end of M12 and coupled
In second end of the 8th switch M8, twelvemo closes second end of M12 can receive electronegative potential VGL, and twelvemo closes the control of M12
End processed is coupled to n-th grade of shift register 100nSecondary nodal point Qn.13rd switch M13 has the first end, the second end and control
End, first end of the 13rd switch M13 is coupled to second end of the 9th switch M9, and second end of the 13rd switch M13 can receive
Electronegative potential VGL, and the control end of the 13rd switch M13 is coupled to n-th grade of shift register 100nSecondary nodal point Qn.14th
Switch M14 has the first end, the second end and controls end, and first end of the 14th switch M14 is coupled to n-th grade of shift register
100nSecondary nodal point Qn, second end of the 14th switch M14 can receive electronegative potential VGL, and the control end of the 14th switch M14
It is coupled to second end of the 9th switch M9.15th switch M15 has the first end, the second end and controls end, the 15th switch M15
The first end be coupled to n-th grade of shift register 100nDrive circuit 110 to receive n-th grade of shift register 100nGrid
Signal Gn, second end of the 15th switch M15 can receive electronegative potential VGL, and the control end of the 15th switch M15 is coupled to the 9th
Second end of switch M9.Sixteenmo closes M16 to be had the first end, the second end and controls end, and sixteenmo closes the first end coupling of M16
It is connected to n-th grade of shift register 100nThe 3rd node Tn, sixteenmo closes second end of M16 can receive electronegative potential VGL, and the
Sixteenmo closes the end that controls of M16 and is coupled to second end of the 9th switch M9.17th switch M17 have the first end, the second end and
Controlling end, first end of the 17th switch M17 is coupled to n-th grade of shift register 100nPrimary nodal point Rn, the 17th switch
Second end of M17 can receive electronegative potential VGL, and the end that controls of the 17th switch M17 is coupled to second end of the 9th switch M9.
Second drop-down unit 134 comprises eighteenmo and closes M18 to the 27th switch M27.Eighteenmo closes M18 and has the
One end, the second end and control end, eighteenmo closes first end of M18 can receive the second selection signal LC2, and eighteenmo closes
The end that controls of M18 is coupled to first end of eighteenmo pass M18.19th switch M19 has the first end, the second end and control
End, the 19th switch M19 the first end be coupled to eighteenmo close M18 the first end, and the 19th switch M19 control end coupling
It is connected to eighteenmo and closes second end of M18.20th switch M20 has the first end, the second end and controls end, the 20th switch
First end of M20 is coupled to eighteenmo and closes second end of M18, and second end of the 20th switch M20 can receive electronegative potential VGL,
And the control end of the 20th switch M20 is coupled to the secondary nodal point Q of (n-1) level shift register(n-1).21st switch
M21 has the first end, the second end and controls end, and first end of the 21st switch M21 is coupled to the second of the 19th switch M19
End, second end of the 21st switch M21 can receive electronegative potential VGL, and the control end of the 21st switch M21 is coupled to the
(n-1) the secondary nodal point Q of level shift register(n-1).Second twelvemo is closed M22 and is had the first end, the second end and control end, and second
First end of twelvemo pass M22 is coupled to eighteenmo and closes second end of M18, and the second twelvemo is closed second end of M22 and can be received
Electronegative potential VGL, and the control end that the second twelvemo closes M22 is coupled to n-th grade of shift register 100nSecondary nodal point Qn.Second
13 switch M23 have the first end, the second end and control end, and first end of the 23rd switch M23 is coupled to the 19th switch
Second end of M19, second end of the 23rd switch M23 can receive electronegative potential VGL, and the control end of the 23rd switch M23
It is coupled to n-th grade of shift register 100nSecondary nodal point Qn.24th switch M24 has the first end, the second end and control
End, first end of the 24th switch M24 is coupled to n-th grade of shift register 100nSecondary nodal point Qn, the 24th switch
Second end of M24 can receive electronegative potential VGL, and the end that controls of the 24th switch M24 is coupled to the second of the 19th switch M19
End.25th switch M25 has the first end, the second end and controls end, and first end of the 25th switch M25 is coupled to n-th
Level shift register 100nDrive circuit 110 to receive n-th grade of shift register 100nSignal Gn, the 25th opens
The second end closing M25 can receive electronegative potential VGL, and the end that controls of the 25th switch M25 is coupled to the of the 19th switch M19
Two ends.Second sixteenmo closes M26 to be had the first end, the second end and controls end, and the second sixteenmo closes first end of M26 and is coupled to the
N level shift register 100nThe 3rd node Tn, the second sixteenmo closes second end of M26 can receive electronegative potential VGL, and the 20th
The end that controls of six switch M26 is coupled to second end of the 19th switch M19.27th switch M27 has the first end, the second end
And control end, first end of the 27th switch M27 is coupled to n-th grade of shift register 100nPrimary nodal point Rn, the 27th
Second end of switch M27 can receive electronegative potential VGL, and the end that controls of the 27th switch M27 is coupled to the 19th switch M19's
Second end.
N-th grade of shift register 100nDrive circuit 110 comprise second eighteenmo close M28 and electric capacity C1.28th
Switch M28 has the first end, the second end and controls end, and the second eighteenmo closes first end of M28 can receive clock signal (with the 6th
Level shift register 1006As a example by, its clock signal is HC2), the second eighteenmo closes second end of M28 in order to export n-th grade of shifting
Bit register 100nSignal Gn, and the control end that the second eighteenmo closes M28 is coupled to n-th grade of shift register 100n's
Secondary nodal point Qn.Electric capacity C1 has the first end and the second end, and first end of electric capacity C1 is coupled to the second eighteenmo and closes the control of M28
End, and second end of electric capacity C1 is coupled to the second eighteenmo and closes second end of M28.
Fig. 3 is the 6th grade of shift register 100 of Fig. 16Time sequential routine figure.In the fig. 3 embodiment, first selects letter
Number LC1 can be maintained at high potential VGH, and second selects signal LC2 can be maintained at electronegative potential VGL, therefore the 6th grade of shift LD
Device 1006Pull-down circuit mainly stablize internal saving by the 5th switch M5 to the 7th switch M7 and the first drop-down unit 132 thereof
The voltage of point.In an embodiment of the present invention, first signal LC1 and second is selected to select signal LC2 can be maintained at high electricity in turn
Position VGH so that shift register 1006The first drop-down unit 132 or the second drop-down unit 134 can be utilized in turn to stablize in
The voltage of portion's node, that is, when second selects signal LC2 to be maintained at high potential VGH, and first selects signal LC1 to be maintained at low
During current potential VGL, the pull-down circuit 130 of the 6th grade of shift register 1006 then can rely on the 5th switch M5 to the 7th switch M7 and
Second drop-down unit 134 stablizes internal node Rn、QnAnd TnAnd signal G6Voltage.
In the first period TP1 of Fig. 3, clock signal HC1 is high potential VGH, and clock signal HC2 is electronegative potential VGL, by
First order shift register 1001The preliminary filling pull-up signal SQ ' of output1For high potential VGH, and by level V shift register 1005
The main pull-up signal SQ of output5And auxiliary pull-up signal SR5Current potential be then floating.Due to the 6th grade of shift register
1006Secondary nodal point Q6Preliminary filling pull-up signal SQ ' can be received1, therefore the 6th grade of shift register 1006Secondary nodal point Q6Electricity
Position also can be thus lifted to high potential VGH, and charges electric capacity C1.Additionally, due to the second section of level V shift register 1005
Point Q5Also high potential VGH (in the about first period TP1, twice 2VGH of secondary nodal point Q6 current potential) can be in, therefore the 6th grade
Shift register 1006The tenth switch M10 to the 13rd switch M13 all can be switched on so that the 14th switch M14 to the tenth
Seven switch M17 can be cut off, thus without drop-down 6th grade of shift register 1006Primary nodal point R6And secondary nodal point Q6's
Current potential.Furthermore, fourth stage shift register 1004And the 8th grade of shift register 1008The 3rd node T4And T8It is also in low
Current potential VGL, so the 6th grade of shift register 1006The 5th switch M5 to the 7th switch M7 also will not drop-down 6th grade of displacement
Depositor 1006Primary nodal point R6And secondary nodal point Q6Current potential.
In the second period TP2, clock signal HC1 is electronegative potential VGL, and clock signal HC2 is high potential VGH, by first
Level shift register 1001The preliminary filling pull-up signal SQ ' of output1Current potential be floating, and by level V shift register
1005The main pull-up signal SQ of output5And auxiliary pull-up signal SR5Current potential be also all floating.Clock signal HC2 can be led to
Cross electric capacity C1 by the 6th grade of shift register 1006Secondary nodal point Q6Ground to the high potential of the twice of about original current potential
2VGH, and the 6th grade of shift register 1006M28 output can be closed by the second eighteenmo and there is the signal of high potential VGH
G6.Additionally, the 6th grade of shift register 1006The tenth switch M10 to the 13rd switch M13 still can be switched on, and the 14th opens
Close M14 to the 17th switch M17 still can be cut off, thus without drop-down 6th grade of shift register 1006Primary nodal point R6And
Secondary nodal point Q6Current potential.
In the 3rd period TP3, clock signal HC1 and HC2 are all electronegative potential VGL, by first order shift register 1001
The preliminary filling pull-up signal SQ ' of output1For floating, and by level V shift register 1005The main pull-up signal SQ of output5
And auxiliary pull-up signal SR5Also floating it is all.Due to the 6th grade of shift register 1006Secondary nodal point Q6Around do not put
Power path, therefore its current potential still can be maintained at high potential VGH so that the 6th grade of shift register 1006Second eighteenmo close
M28 is persistently switched on, and and then makes signal G6It is pulled down to the electronegative potential VGL identical with clock signal HC2.Additionally, the
Six grades of shift registers 1006Twelvemo close M12 to the 13rd switch M13 still can be switched on, therefore the 14th switch M14
Still can be cut off, without drop-down 6th grade of shift register 100 to the 17th switch M176Primary nodal point R6And secondary nodal point
Q6Current potential.
In the 4th period TP4, clock signal HC1 and HC2 are all electronegative potential VGL, by first order shift register 1001
The preliminary filling pull-up signal SQ ' of output1For floating, and by level V shift register 1005The main pull-up signal SQ of output5
And auxiliary pull-up signal SR5Also floating it is all, but fourth stage shift register 1004The 3rd node T4Then can be in height
Current potential VGH, therefore the 6th grade of shift register 1006The 5th switch M5 can be switched on, and by the 6th grade of shift register 1006
Secondary nodal point Q6Current potential be pulled down to electronegative potential VGL.6th grade of shift register 1006Secondary nodal point Q6Current potential can by under
Move electronegative potential VGL, therefore the 6th grade of shift register 100 to6Twelvemo close M12 to the 13rd switch M13 can be cut off,
But level V shift register 1005Secondary nodal point Q5It is still within high potential VGH, therefore the tenth switch M10 to the 11st
Switch M11 still can be switched on so that the 14th switch M14 to the 17th switch M17 still can be cut off, without drop-down 6th grade
Shift register 1006Primary nodal point R6And secondary nodal point Q6Current potential.
In 5th period TP5, clock signal HC1 is high potential VGH, and clock signal HC2 is electronegative potential VGL, by the first order
Shift register 1001The preliminary filling pull-up signal SQ ' of output1For floating, and by level V shift register 1005Output
Main pull-up signal SQ5And auxiliary pull-up signal SR5It is all high potential VGH.Due to the 6th grade of shift register 1006Second section
Point Q6Main pull-up signal SQ can be received5, therefore the 6th grade of shift register 1006Secondary nodal point Q6Current potential also can be elevated
To high potential VGH, and electric capacity C1 is charged.Additionally, due to level V shift register 1005Secondary nodal point Q5Also height can be in
Current potential (in the about first period TP1, secondary nodal point Q6Twice 2VGH of current potential), therefore the 6th grade of shift register 1006?
Ten switch M10 to the 13rd switch M13 can be switched on so that the 14th switch M14 to the 17th switch M17 can be cut
Only, therefore the 6th grade of shift register 1006Primary nodal point R6And secondary nodal point Q6Current potential all without being pulled down.Furthermore, by
In the 6th grade of shift register 1006Primary nodal point R6Auxiliary pull-up signal SR can be received5, therefore the 6th grade of shift register
1006Primary nodal point R6Current potential also can be thus lifted to high potential VGH so that the 6th grade of shift register 1006First switch
M1 is switched on, and to the 6th grade of shift register 1006First switch M1 parasitic capacitance charging.
In the 6th period TP6, clock signal HC1 is electronegative potential VGL, and clock signal HC2 is high potential VGH, by first
Level shift register 1001The preliminary filling pull-up signal SQ ' of output1For floating, and by level V shift register 1005Output
Main pull-up signal SQ5And auxiliary pull-up signal SR5It is all floating.Due to primary nodal point R6With secondary nodal point Q6Around
There is no discharge path, therefore the first switch M1 and the second eighteenmo pass M28 still can be switched on, and clock signal HC2 can pass through electric capacity
C1 is by the 6th grade of shift register 1006Secondary nodal point Q6Ground to the high potential VGH of the twice of about original current potential, and
6th grade of shift register 1006The grid letter of high potential VGH i.e. can be had by the second end output of the second eighteenmo pass M28
Number G6；Similarly, clock signal HC2 also can pass through the 6th grade of shift register 1006The parasitic capacitance of the first switch M1 by the
Six grades of shift registers 1006Primary nodal point R6Ground to the high potential VGH of the twice of about original current potential, and the 6th grade
Shift register 1006The 3rd node T6Current potential also can be pulled to the high potential VGH identical with clock signal HC2.At this
In the case of, the 6th grade of shift register 1006Second switch M2A, the 3rd switch M3A and the 4th switch M4A all can be switched on,
And export the auxiliary pull-up signal SR with high potential VGH6, main pull-up signal SQ6And preliminary filling pull-up signal SQ '6.Additionally, the
Six grades of shift registers 1006The tenth switch M10 to the 13rd switch M13 still can be switched on, and then make the 14th switch
M14 to the 17th switch M17 is cut off, therefore the 6th grade of shift register 1006Primary nodal point R6And secondary nodal point Q6Electricity
Position is all without being pulled down.
In the 7th period TP7, clock signal HC1 and HC2 are all electronegative potential VGL, by first order shift register 1001
The preliminary filling pull-up signal SQ ' of output1For floating, and by level V shift register 1005The main pull-up signal SQ of output5
And auxiliary pull-up signal SR5Also floating it is all.6th grade of shift register 1006Secondary nodal point Q6Current potential still can keep
At high potential VGH, and the 6th grade of shift register 1006Second eighteenmo close M28 can be switched on so that signal G6Under by
It is pulled to the electronegative potential VGL identical with clock signal HC2.6th grade of shift register 1006Primary nodal point R6Current potential still can protect
Hold at high potential VGH, and the 6th grade of shift register 1006First switch M1 can be switched on so that the 6th grade of shift register
1006The 3rd node T6Current potential be pulled down to electronegative potential VGL, and thus the 6th grade of shift register 100 of cut-off6Second open
Close M2A, the 3rd switch M3A and the 4th switch M4A.Consequently, it is possible to the 6th grade of shift register 1006The auxiliary pull-up letter of output
Number SR6, main pull-up signal SQ6And preliminary filling pull-up signal SQ '6Become floating.Additionally, the 6th grade of shift register
1006Twelvemo close M12 to the 13rd switch M13 still can be switched on, and the 14th switch M14 to the 17th switch M17 still
Can be cut off, thus without drop-down 6th grade of shift register 1006Primary nodal point R6And secondary nodal point Q6Current potential.Furthermore,
Fourth stage shift register 1004And the 8th grade of shift register 1008The 3rd node T4And T8The most all can be in electronegative potential VGL,
So the 6th grade of shift register 1006The 5th switch M5 to the 7th switch M7 also will not drop-down 6th grade of shift register 1006
Primary nodal point R6And secondary nodal point Q6Current potential.
In the 8th period TP8, clock signal HC1 and HC2 are all electronegative potential VGL, by first order shift register 1001
The preliminary filling pull-up signal SQ ' of output1For floating, and by level V shift register 1005The main pull-up signal SQ of output5
And auxiliary pull-up signal SR5Also floating it is all, but the 8th grade of shift register 1008The 3rd node T8Then can be in height
Current potential VGH, therefore the 6th grade of shift register 1006The 6th switch M6 and the 7th switch M7 all can be switched on, and then can be by the
Six grades of shift registers 1006Primary nodal point R6And secondary nodal point Q6Current potential be pulled down to electronegative potential VGL.Now, the 6th grade of shifting
Bit register 1006The tenth switch M10 to the 13rd switch M13 can be cut off, and the 14th switch M14 to the 17th switch
M17 then can be switched on, therefore can be by the 6th grade of shift register 1006Primary nodal point R6And secondary nodal point Q6Current potential stable exist
Electronegative potential VGL, and by the 6th grade of shift register 1006Signal G6Stable at electronegative potential VGL.
Profess it, in the second period TP2, the 6th grade of shift register 1006Can first export signal G6So that couple
In the 6th grade of shift register 1006Pixel can be pre-charged, also can make the liquid crystal molecule in pixel can be in advance
Turn to, then in the 6th period TP6, the 6th grade of shift register 1006Can again export signal G6, now be coupled to
6th grade of shift register 1006Pixel i.e. can be driven according to data signal so that the liquid crystal molecule in pixel can be rapid
Deflect into correspondence direction.
As long as consequently, it is possible to the characteristic deflected according to demand and the polarity of system, selecting suitable clock signal quantity, i.e. M
Numerical value, shift register 100 can be madenAccording to (M+1) level shift register, i.e. (n-1-M) level shift LD before it
Device, the preliminary filling exported pull-up signal, signal G of output in advancen, reach liquid crystal molecule precharge in pixel
Effect.
In the section Example of the present invention, n-th grade of shift register 100nPull-up output circuit 122 second switch
M2A to the 4th switch M4A also can have different connected modes from Fig. 2.Fig. 4 is n-th grade of displacement of another embodiment of the present invention
Depositor 100 'nSchematic diagram.Shift register 100 'nWith shift register 100nStructure similar, difference is only that displacement is posted
Storage 100 'nPull-up output circuit 122 ' in, second switch M2B to the 4th switch connected mode of M4B and shift register
100nThe connected mode of second switch M2A to the 4th switch M4A different.
Second switch M2B has the first end, the second end and controls end, and first end of second switch M2B can receive high potential
The exportable n-th grade of shift register 100 ' of second end of VGH, second switch M2BnAuxiliary pull-up signal SRn, and second switch
The control end of M2B is coupled to the 3rd node T of shift register 100 ' nn.3rd switch M3B has the first end, the second end and control
End processed, first end of the 3rd switch M3B can receive high potential VGH, the second exportable shift register of end of the 3rd switch M3B
100’nMain pull-up signal SQn, and the control end of the 3rd switch M3B is coupled to shift register 100 'nThe 3rd node Tn。
4th switch M4B has the first end, the second end and controls end, and first end of the 4th switch M4B can receive high potential VGH, and the 4th
The preliminary filling pull-up signal SQ ' of the second end exportable shift register 100 ' n of switch M4Bn, and the control end of the 4th switch M4B
It is coupled to 100 ' n the 3rd node T of shift registern。
Additionally, in the section Example of the present invention, the front M level shift register in shift register circuit 10, i.e. first
Level shift register 1001To fourth stage shift register 1004, can be redundancy shift register, and can not be in order to export grid letter
Number.In the case, the shift LD utensil that before shift register circuit 10, M level shift register can be later with (M+1) level
There is different frameworks.Furthermore, in FIG, first order shift register 1001Primary nodal point, secondary nodal point and level V displacement
Depositor 1005Secondary nodal point can receive the initial signal SI of synchronization.
Fig. 5 is the m level shift register 100 of the shift register circuit 10 of one embodiment of the inventionmSchematic diagram, m is
It is not more than the integer of M.Shift register 100mWith shift register 100nFramework similar, difference is shift register 100m
Shift register 100 can not be comprisednIn secondary nodal point Qn, and secondary nodal point QnThe switch coupled mutually and drive circuit 110, also
That is, the shift register 100 of Fig. 5mWith shift register 100nDifference be shift register 100mThe 3rd switch can not be comprised
M3A, the 5th switch M5, the 6th switch M6, the 14th switch M14, the 15th switch M15, the 24th switch M24, the 20th
Five switch M25, the second eighteenmo close M28 and electric capacity C1.Additionally, due to shift register 100mDo not comprise secondary nodal point, because of
Before the control end of this tenth switch M10, the 11st switch M11, the 20th switch M20 and the 21st switch M21 can be coupled to
The primary nodal point R of one-level shift register(m-1), and twelvemo close M12, the 13rd switch M13, second twelvemo close M22 and
The control end of the 23rd switch M23 can be coupled to shift register 100mPrimary nodal point Rm。
Owing to the function that front M level shift register is main is to produce preliminary filling pull-up signal to provide to thereafter (M+1)
The shift register of level, and signal need not be exported in panel pixel, therefore can reduce above-mentioned relevant switch, to keep away
Exempt from waste material and unnecessary technique can be reduced.Certainly, in the section Example of the present invention, in shift register circuit 10
Front M level shift register is used as and shift register 100nIdentical framework.
In sum, the shift register that embodiments of the invention are provided can be according to the shift register of front (M+1) level
The preliminary filling pull-up signal exported, to export the signal of this grade, therefore can reach the effect to pixel precharge, and logical
Cross and select suitable clock signal quantity (i.e. the numerical value of M), i.e. can ensure that when using different types of polar inversion method, allow
Pixel can receive the voltage of correct polarity and be pre-charged, and therefore too increases the elasticity in panel circuit design.
The foregoing is only the preferred embodiments of the present invention, all equalizations done according to claims of the present invention change and repair
Decorations, all should belong to the covering scope of the present invention.
Claims (17)
1. a shift register, comprises:
Primary nodal point, pulls up signal in order to receive the auxiliary of previous stage shift register output；
Secondary nodal point, in order to receive main pull-up signal and front (M+1) level shift LD of this previous stage shift register output
The preliminary filling pull-up signal of device output, M is the integer more than 3；
Drive circuit, is coupled to this secondary nodal point, exports this displacement in order to the current potential according to this secondary nodal point and clock signal and posts
The signal of storage；
Pull-up circuit, comprises:
First switch, have the first end in order to receive this clock signal, the second end is coupled to the 3rd node and control end be coupled to
This primary nodal point；And
Pull-up output circuit, is coupled to the 3rd node, in order to export the main pull-up signal of this shift register, preliminary filling pull-up
Signal and auxiliary pull-up signal；And
Pull-down circuit, is coupled to this primary nodal point, this secondary nodal point and the 3rd node, in order to post according to the displacement of front (M-2) level
The current potential of the 3rd node of storage and current potential this primary nodal point drop-down of the 3rd node of rear two grades of shift registers and this second
The current potential of node, and according to the current potential of this secondary nodal point and current potential these grid drop-down of the secondary nodal point of this previous stage shift register
The current potential of the 3rd node of pole signal, this primary nodal point, this secondary nodal point of this shift register and this shift register.
2. shift register as claimed in claim 1, this of wherein this shift register mainly pulls up after signal is output to
The secondary nodal point of one-level shift register, after this preliminary filling pull-up signal of this shift register is output to, the displacement of (M+1) level is posted
The secondary nodal point of storage, and this shift register this auxiliary pull-up signal be output to the first of this rear stage shift register
Node.
3. shift register as claimed in claim 1 or 2, wherein this pull-up output circuit comprises:
Second switch, has the first end and is coupled to the 3rd node of this shift register, and the second end is posted in order to export this displacement
This auxiliary of storage pulls up signal, and control end is coupled to this first end of this second switch；
3rd switch, has the first end and is coupled to the 3rd node of this shift register, and the second end is posted in order to export this displacement
This of storage mainly pulls up signal, and control end is coupled to this first end of the 3rd switch；And
4th switch, has the first end and is coupled to the 3rd node of this shift register, and the second end is posted in order to export this displacement
This preliminary filling of storage pulls up signal, and control end is coupled to this first end of the 4th switch.
4. shift register as claimed in claim 1 or 2, wherein this pull-up output circuit comprises:
Second switch, has the first end in order to receive system high potential, and the second end is in order to export this auxiliary of this shift register
Pull up signal, and control end is coupled to the 3rd node of this shift register；
3rd switch, has the first end in order to receive this system high potential, and the second end is in order to export this master of this shift register
Signal to be pulled up, and control end and be coupled to the 3rd node of this shift register；And
4th switch, has the first end in order to receive this system high potential, and the second end is pre-in order to export this of this shift register
Fill with and draw signal, and control end is coupled to the 3rd node of this shift register.
5. shift register as claimed in claim 1, wherein this pull-down circuit comprises:
5th switch, has the first end and is coupled to this secondary nodal point of this shift register, and the second end is in order to receive the low electricity of system
Position, and control the 3rd node of (M-2) level shift register before end is coupled to this；
6th switch, has the first end and is coupled to this secondary nodal point of this shift register, and the second end is low in order to receive this system
Current potential, and control end and be coupled to the 3rd node of these rear two grades of shift registers；And
7th switch, has the first end and is coupled to this primary nodal point of this shift register, and the second end is low in order to receive this system
Current potential, and control end and be coupled to the 3rd node of these rear two grades of shift registers.
6. shift register as claimed in claim 5, wherein this pull-down circuit also comprises:
First drop-down unit, comprises:
8th switch, has the first end in order to receive the first selection signal, the second end, and control end is coupled to the 8th switch
This first end；
9th switch, have the first end be coupled to the 8th switch the one end being somebody's turn to do, the second end, and control end be coupled to the 8th
This second end of switch；
Tenth switch, have the first end be coupled to the 8th switch this second end, the second end in order to receive this system electronegative potential,
And control end is coupled to this secondary nodal point of this previous stage shift register；
11st switch, has the first end and is coupled to this second end of the 9th switch, and the second end is in order to receive the low electricity of this system
Position, and control end and be coupled to this secondary nodal point of this previous stage shift register；
Twelvemo is closed, and has the first end and is coupled to this second end of the 8th switch, and the second end is in order to receive the low electricity of this system
Position, and control end and be coupled to this secondary nodal point of this shift register；
13rd switch, has the first end and is coupled to this second end of the 9th switch, and the second end is in order to receive the low electricity of this system
Position, and control end and be coupled to this secondary nodal point of this shift register；
14th switch, has the first end and is coupled to this secondary nodal point of this shift register, and the second end is in order to receive this system
Electronegative potential, and control end be coupled to the 9th switch this second end；
15th switch, has the first end and is coupled to this drive circuit to receive this signal of this shift register, and second
End is in order to receive this system electronegative potential, and control end is coupled to this second end of the 9th switch；
Sixteenmo closes, and has the first end and is coupled to the 3rd node of this shift register, and the second end is in order to receive this system
Electronegative potential, and control end be coupled to the 9th switch this second end；And
17th switch, has the first end and is coupled to this primary nodal point of this shift register, and the second end is in order to receive this system
Electronegative potential, and control end be coupled to the 9th switch this second end.
7. shift register as claimed in claim 6, wherein this pull-down circuit also comprises:
Second drop-down unit, comprises:
Eighteenmo closes, and has the first end in order to receive the second selection signal, the second end, and control end is coupled to this eighteenmo
This first end closed；
19th switch, have the first end be coupled to this eighteenmo close the one end being somebody's turn to do, the second end, and control end be coupled to this
This second end that eighteenmo closes；
20th switch, has the first end and is coupled to this second end that this eighteenmo closes, and the second end is low in order to receive this system
Current potential, and control end and be coupled to this secondary nodal point of this previous stage shift register；
21st switch, has the first end and is coupled to this second end of the 19th switch, and the second end is in order to receive this system
Electronegative potential, and control end and be coupled to this secondary nodal point of this previous stage shift register；
Second twelvemo is closed, and has the first end and is coupled to this second end that this eighteenmo closes, and the second end is in order to receive this system
Electronegative potential, and control end and be coupled to this secondary nodal point of this shift register；
23rd switch, has the first end and is coupled to this second end of the 19th switch, and the second end is in order to receive this system
Electronegative potential, and control end and be coupled to this secondary nodal point of this shift register；
24th switch, has the first end and is coupled to this secondary nodal point of this shift register, and the second end in order to receive this is
System electronegative potential, and control end be coupled to the 19th switch this second end；
25th switch, has the first end and is coupled to this drive circuit to receive this signal of this shift register, the
Two ends are in order to receive this system electronegative potential, and control end is coupled to this second end of the 19th switch；
Second sixteenmo closes, and has the first end and is coupled to the 3rd node of this shift register, and the second end in order to receive this is
System electronegative potential, and control end be coupled to the 19th switch this second end；And
27th switch, has the first end and is coupled to this primary nodal point of this shift register, and the second end in order to receive this is
System electronegative potential, and control end be coupled to the 19th switch this second end.
8. shift register as claimed in claim 1, wherein this drive circuit comprises:
Second eighteenmo closes, and has the first end in order to receive this clock signal, and the second end is in order to export being somebody's turn to do of this shift register
Signal, and control end and be coupled to this secondary nodal point of this shift register；And
Electric capacity, has the first end and is coupled to this control end that this second eighteenmo closes, and the second end is coupled to this second eighteenmo
This second end closed.
9. a shift register circuit, in order to export multiple signals according to M clock signal during difference being high potential, should
Shift register circuit comprises N level shift register, and n-th grade of shift register in this N level shift register comprises:
Primary nodal point, pulls up signal in order to receive the auxiliary of (n-1) level shift register output；
Secondary nodal point, in order to receive main pull-up signal and the displacement of (n-1-M) level of this (n-1) level shift register output
The preliminary filling pull-up signal of depositor output；
Drive circuit, is coupled to this secondary nodal point of this n-th grade of shift register, in order to according to this n-th grade of shift register
Clock signal in the current potential of this secondary nodal point and this M clock signal exports the signal of this n-th grade of shift register；
Pull-up circuit, comprises:
First switch, have the first end in order to receive this clock signal, the second end is coupled to the 3rd node and control end be coupled to
This primary nodal point of this n-th grade of shift register；And
Pull-up output circuit, is coupled to the 3rd node of this n-th grade of shift register, in order to export this n-th grade of shift LD
The main pull-up signal of device, preliminary filling pull-up signal and auxiliary pull-up signal；And
Pull-down circuit, is coupled to this primary nodal point of this n-th grade of shift register, this secondary nodal point and the 3rd node, in order to
The current potential of the 3rd node according to (n-M+2) level shift register and the electricity of the 3rd node of (n+2) level shift register
This primary nodal point of position this n-th grade of shift register drop-down and the current potential of this secondary nodal point, and according to this n-th grade of shift register
The current potential of this secondary nodal point and current potential this n-th grade of shift LD drop-down of secondary nodal point of this (n-1) level shift register
This signal of device and this primary nodal point of this n-th grade of shift register, this secondary nodal point and the current potential of the 3rd node；
Wherein:
M is the integer more than 3, and N is the integer of the twice more than M, and n is the integer more than M；And
Two shift registers differing M level in this N level shift register are defeated according to clock signal identical in this M clock signal
Go out signal.
10. shift register circuit as claimed in claim 9, this of wherein this n-th grade of shift register mainly pulls up signal quilt
Exporting the secondary nodal point to (n+1) level shift register, this preliminary filling pull-up signal of this n-th grade of shift register is output to
The secondary nodal point of (n+1+M) level shift register, and this n-th grade of shift register this auxiliary pull-up signal be output to this
The primary nodal point of (n+1) level shift register.
11. shift register circuits as described in claim 9 or 10, wherein this pull-up output electricity of this n-th grade of shift register
Road comprises:
Second switch, has the first end and is coupled to the 3rd node of this n-th grade of shift register, the second end in order to export this
This auxiliary of n level shift register pulls up signal, and control end is coupled to this first end of this second switch；
3rd switch, has the first end and is coupled to the 3rd node of this n-th grade of shift register, the second end in order to export this
This of n level shift register mainly pulls up signal, and control end is coupled to this first end of the 3rd switch；And
4th switch, has the first end and is coupled to the 3rd node of this n-th grade of shift register, the second end in order to export this
This preliminary filling of n level shift register pulls up signal, and control end is coupled to this first end of the 4th switch.
12. shift register circuits as described in claim 9 or 10, wherein this pull-up output electricity of this n-th grade of shift register
Road comprises:
Second switch, has the first end in order to receive system high potential, and the second end is in order to export being somebody's turn to do of this n-th grade of shift register
Auxiliary pulls up signal, and control end is coupled to the 3rd node of this n-th grade of shift register；
3rd switch, has the first end in order to receive this system high potential, and the second end is in order to export this n-th grade of shift register
This mainly pulls up signal, and control end is coupled to the 3rd node of this n-th grade of shift register；And
4th switch, has the first end in order to receive this system high potential, and the second end is in order to export this n-th grade of shift register
This preliminary filling pulls up signal, and control end is coupled to the 3rd node of this n-th grade of shift register.
13. shift register circuits as claimed in claim 9, wherein this pull-down circuit of this n-th grade of shift register comprises:
5th switch, has the first end and is coupled to this secondary nodal point of this n-th grade of shift register, and the second end is in order to receive system
Electronegative potential, and control end and be coupled to the 3rd node of this (n-M+2) level shift register；
6th switch, has the first end and is coupled to this secondary nodal point of this n-th grade of shift register, and the second end in order to receive this is
System electronegative potential, and control end and be coupled to the 3rd node of this (n+2) level shift register；And
7th switch, has the first end and is coupled to this primary nodal point of this shift register, and the second end is low in order to receive this system
Current potential, and control end and be coupled to the 3rd node of this (n+2) level shift register.
14. shift register circuits as claimed in claim 13, wherein this pull-down circuit of this n-th grade of shift register also wraps
Contain:
First drop-down unit, comprises:
8th switch, has the first end in order to receive the first selection signal, the second end, and control end is coupled to the 8th switch
This first end；
9th switch, have the first end be coupled to the 8th switch the one end being somebody's turn to do, the second end, and control end be coupled to the 8th
This second end of switch；
Tenth switch, have the first end be coupled to the 8th switch this second end, the second end in order to receive this system electronegative potential,
And control end is coupled to this secondary nodal point of this (n-1) level shift register；
11st switch, has the first end and is coupled to this second end of the 9th switch, and the second end is in order to receive the low electricity of this system
Position, and control end and be coupled to this secondary nodal point of this (n-1) level shift register；
Twelvemo is closed, and has the first end and is coupled to this second end of the 8th switch, and the second end is in order to receive the low electricity of this system
Position, and control end and be coupled to this secondary nodal point of this n-th grade of shift register；
13rd switch, has the first end and is coupled to this second end of the 9th switch, and the second end is in order to receive the low electricity of this system
Position, and control end and be coupled to this secondary nodal point of this n-th grade of shift register；
14th switch, has the first end and is coupled to this secondary nodal point of this n-th grade of shift register, and the second end is in order to receive this
System electronegative potential, and control end be coupled to the 9th switch this second end；
15th switch, has the first end and is coupled to this drive circuit of this n-th grade of shift register to receive this n-th grade displacement
This signal of depositor, the second end in order to receive this system electronegative potential, and control end be coupled to the 9th switch this
Two ends；
Sixteenmo closes, and has the first end and is coupled to the 3rd node of this n-th grade of shift register, and the second end is in order to receive this
System electronegative potential, and control end be coupled to the 9th switch this second end；And
17th switch, has the first end and is coupled to this primary nodal point of this n-th grade of shift register, and the second end is in order to receive this
System electronegative potential, and control end be coupled to the 9th switch this second end.
15. shift register circuits as claimed in claim 13, wherein this pull-down circuit of this n-th grade of shift register also wraps
Contain:
Second drop-down unit, comprises:
Eighteenmo closes, and has the first end in order to receive the second selection signal, the second end, and control end is coupled to this eighteenmo
This first end closed；
19th switch, have the first end be coupled to this eighteenmo close the one end being somebody's turn to do, the second end, and control end be coupled to this
This second end that eighteenmo closes；
20th switch, has the first end and is coupled to this second end that this eighteenmo closes, and the second end is low in order to receive this system
Current potential, and control end and be coupled to this secondary nodal point of this (n-1) level shift register；
21st switch, has the first end and is coupled to this second end of the 19th switch, and the second end is in order to receive this system
Electronegative potential, and control end and be coupled to this secondary nodal point of this (n-1) level shift register；
Second twelvemo is closed, and has the first end and is coupled to this second end that this eighteenmo closes, and the second end is in order to receive this system
Electronegative potential, and control end and be coupled to this secondary nodal point of this n-th grade of shift register；
23rd switch, has the first end and is coupled to this second end of the 19th switch, and the second end is in order to receive this system
Electronegative potential, and control end and be coupled to this secondary nodal point of this n-th grade of shift register；
24th switch, has the first end and is coupled to this secondary nodal point of this n-th grade of shift register, and the second end is in order to receive
This system electronegative potential, and control end be coupled to the 19th switch this second end；
25th switch, has the first end and is coupled to this drive circuit of this n-th grade of shift register to receive this n-th grade shifting
This signal of bit register, the second end is in order to receive this system electronegative potential, and control end is coupled to the 19th switch
This second end；
Second sixteenmo closes, and has the first end and is coupled to the 3rd node of this n-th grade of shift register, and the second end is in order to receive
This system electronegative potential, and control end be coupled to the 19th switch this second end；And
27th switch, has the first end and is coupled to this primary nodal point of this n-th grade of shift register, and the second end is in order to receive
This system electronegative potential, and control end be coupled to the 19th switch this second end.
16. shift register circuits as claimed in claim 9, wherein this drive circuit of this n-th grade of shift register comprises:
Second eighteenmo closes, and has the first end in order to receive this clock signal, and the second end is in order to export this n-th grade of shift register
This signal, and control end and be coupled to this secondary nodal point of this n-th grade of shift register；And
Electric capacity, has the first end and is coupled to this control end that this second eighteenmo closes, and the second end is coupled to this second eighteenmo
This second end closed.
17. shift register circuits as claimed in claim 9, wherein the m level shift register bag in this N level shift register
Contain:
Primary nodal point, pulls up signal in order to receive the auxiliary of this (m-1) level shift register output；
Pull-up circuit, comprises:
First switch, has the first end and is coupled to the 3rd node in order to clock signal, the second end receiving in this M clock signal
And control end is coupled to this primary nodal point of this m level shift register；And
Pull-up output circuit, is coupled to the 3rd node of this m level shift register, in order to export this m level shift LD
The preliminary filling pull-up signal of device and auxiliary pull-up signal；And
Pull-down circuit, is coupled to this primary nodal point and the 3rd node of this m level shift register, in order to according at least this
Current potential this m level drop-down displacement of this primary nodal point of m level shift register and the 3rd node of (m+2) level shift register
This primary nodal point of depositor and the current potential of the 3rd node；
Wherein m is the integer of no more than M.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW104144421 | 2015-12-30 | ||
| TW104144421A TWI562114B (en) | 2015-12-30 | 2015-12-30 | Shift register and shift register circuit |
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| Publication Number | Publication Date |
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| CN105761687A true CN105761687A (en) | 2016-07-13 |
| CN105761687B CN105761687B (en) | 2019-01-08 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610079202.9A Expired - Fee Related CN105761687B (en) | 2015-12-30 | 2016-02-04 | Shift register and shift register circuit |
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| Country | Link |
|---|---|
| CN (1) | CN105761687B (en) |
| TW (1) | TWI562114B (en) |
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| CN108399884A (en) * | 2017-12-28 | 2018-08-14 | 友达光电股份有限公司 | Shift register circuit |
| CN108492790A (en) * | 2017-05-12 | 2018-09-04 | 惠科股份有限公司 | The Waveform generating method of the first buffering circuit of displacement |
| CN111192546A (en) * | 2018-11-15 | 2020-05-22 | 群创光电股份有限公司 | Display panel and electronic device |
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| US20130077736A1 (en) * | 2011-09-23 | 2013-03-28 | Hydis Technologies Co., Ltd. | Shift Register and Driving Circuit Using the Same |
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| CN111192546A (en) * | 2018-11-15 | 2020-05-22 | 群创光电股份有限公司 | Display panel and electronic device |
| CN111192546B (en) * | 2018-11-15 | 2023-08-15 | 群创光电股份有限公司 | Display panel and electronic device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105761687B (en) | 2019-01-08 |
| TWI562114B (en) | 2016-12-11 |
| TW201724067A (en) | 2017-07-01 |
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