CN105760784B - Diversification configuration information compression method and device - Google Patents
Diversification configuration information compression method and device Download PDFInfo
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- CN105760784B CN105760784B CN201610097052.4A CN201610097052A CN105760784B CN 105760784 B CN105760784 B CN 105760784B CN 201610097052 A CN201610097052 A CN 201610097052A CN 105760784 B CN105760784 B CN 105760784B
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/72—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
Abstract
The invention discloses a kind of diversification configuration information compression method and devices, wherein this method includes：Cryptographic algorithm is planned and generates the corresponding data flow diagram of cryptographic algorithm；Common factor is extracted according to the repeat property of data flow diagram, and determines the common factor redundancy of common factor；Subgraph division is carried out to data flow diagram according to restructural cipher processor hardware feature and common factor redundancy；And configuration compress mode is determined according to the structure feature information and interconnection features information of the subgraph after division, and compression configuration is carried out to the configuration information of reconfigurable arithmetic unit corresponding to subgraph and the configuration information of interconnection by configuring compress mode.The calculating feature of this method combining cipher algorithm carrys out option and installment Information Compression mode, and is compressed based on selected configuration information compress mode to configuration information, removes the configuration information of redundancy, and then the execution efficiency of restructural cipher processor can be improved.
Description
Technical field
The present invention relates to electronic technology field more particularly to a kind of diversification configuration information compression methods and device.
Background technique
Restructural cipher processor (PRU_CRYPTO), has used a kind of coarseness reconfigurable processor framework, has combined
The flexibility of software and the high efficiency of hardware, by general reconfigurable arithmetic unit array RCA (Reconfigurable
Computing Array) carry out dynamic configuration not only can change control stream, data path can also be changed, dynamic implement is not
Same cryptographic algorithm, and the hardware resource of restructural Cipher Processing itself is free of any security information.Restructural Cipher Processing
Have the advantages that high-performance, low-power consumption, flexibility be good, favorable expandability, is suitable for handling the cryptographic algorithm of computation-intensive, example
Such as, Advanced Encryption Standard (Advanced Encryption Standard, AES), SM3, ZUC, secure hash algorithm SHA256
(Secure Hash Algorithm, SHA) etc..Therefore, restructural cipher processor has a good application prospect, and can also expire
The demand that foot difference cryptographic consumer multi-level security requirement and cryptographic algorithm constantly upgrade.
The operation main body of restructural cipher processor is reconfigurable arithmetic unit array, in restructural cipher processor
In RCA, the function that reconfigurable arithmetic unit RC (Reconfigurable Computing) is realized is determined by configuration parameter,
Its interconnection architecture can also be determined between RC by configuration parameter.By the planning mapped on RCA algorithm, each RC is determined
Realize what kind of interconnection is between which kind of function and RC, and generate corresponding configuration parameter, can realize the height of data flow well
Fast parallel processing.But different cryptographic algorithms have different degrees of repetitive structure, for example, function complete one used in many RC
At this moment sample still will result in parameter repetition and redundancy using individual configuration parameter to each RC, to seriously affect configuration effect
Rate, and then influence the efficiency of dynamic implement cryptographic algorithm, that is, influence the execution efficiency of restructural cipher processor.
In order to reduce the size of configuration information, allocative efficiency is improved, proposes a kind of pressure of stratification configuration in the related technology
Contracting method, as shown in Figure 1, Fig. 1 illustrates a kind of compression method of stratification configuration, compression method is as follows：
It is assumed that the corresponding partial data flow graph of core algorithm (DFG, Data Flow Graph) is divided into multiple subgraphs, son
Figure respectively corresponds configuration 1,2,3 from top to bottom.And each configuration includes input, calculates, three parts of output.Wherein, pass through
Fig. 1 can be seen that the output of configuration 1 and configure 2 input, and the dependence between them is clear, configure 2 data input ground
Location is exactly the address data output for configuring 1, in order to reduce the size of configuration information, it is convenient to omit the configuration of this part passes through system
Automatic distribution.As soon as the particular content of the configuration memory storage configuration 1,2,3 of inside is set, it is external only to need to tell and weigh
Structure processor (RPU, Reconfigurable Processing Unit)：The address of array input 1 and output 3, and configuration
The calling sequence list (address list of configuration 1,2,3) of index.These information just constitute configuration group.Partial data flow graph pair
What is answered is configuration group, therefore configuration combinational algorithm is corresponding, is that the level-one of configuration system is abstract.The information of these configuration groups is same
It can store inside reconfigurable processor, it is external only to need through write-in data I/O Address and configuration group serial number.Match
The sequence sets and application for setting group correspond to, this is abstract for the second level of configuration system.Outside write-in configuration words set, by configure come
It indexes middle layer configuration information (specific algorithm, configuration group), then indexes bottom configuration information (tool by middle layer configuration information
Body Mapping implementation, the contents such as selection including operator, routing function).
This method can largely compress the amount of configuration data that RPU interface needs to read, thus by the bottom of original magnanimity
Layer configuration information calls programming secondary index table.However, the entire compress mode of this method is comparatively single, restructural
Cipher processor is not directed to the respective calculating of different cryptographic algorithms only with the mode for carrying out configuration group division to configuration parameter
Characteristic stores to carry out configuration information compression, and under certain applications, the total amount of data of bottom configuration parameter can not be most
It optimally reduces, the configuration information of some repetitive structures may still exist in the expanded form, to cause configuration information superfluous
It is remaining.
Summary of the invention
The purpose of the present invention is intended to solve above-mentioned one of technical problem at least to a certain extent.
For this purpose, the first purpose of this invention is to propose a kind of diversification configuration information compression method.This method combines
The calculating feature of cryptographic algorithm carrys out option and installment Information Compression mode, and based on selected configuration information compress mode to configuration
Information is compressed, and the configuration information of redundancy is removed, and then the execution efficiency of restructural cipher processor can be improved.
Second object of the present invention is to propose a kind of diversification configuration information compression set.
In order to achieve the above object, the diversification configuration information compression method of first aspect present invention embodiment, including：To password
Algorithm is planned and generates the corresponding data flow diagram of the cryptographic algorithm；It is extracted according to the repeat property of the data flow diagram public
The factor, and determine the common factor redundancy of the common factor；According to restructural cipher processor hardware feature and the common factor
Redundancy carries out subgraph division to the data flow diagram；And structure feature information and interconnection features according to the subgraph after division
Information determines configuration compress mode, and by the configuration compress mode to reconfigurable arithmetic unit corresponding to the subgraph
Configuration information and the configuration information of interconnection carry out compression configuration.
The diversification configuration information compression method of the embodiment of the present invention, it is corresponding by being planned to obtain to cryptographic algorithm
Then data flow diagram extracts common factor according to the repeat property of data flow diagram and determines common factor redundancy, further according to restructural
Cipher processor hardware feature and common factor redundancy carry out subgraph division to data flow diagram, finally according to ready-portioned subgraph
Structure feature information and interconnection features information determine configuration information and interconnection of the configuration compress mode to its reconfigurable arithmetic unit
Configuration information carry out compression configuration, the calculating feature of this method combining cipher algorithm carrys out option and installment Information Compression mode, and
Configuration information is compressed based on selected configuration information compress mode, removes the configuration information of redundancy, and then can be improved
The execution efficiency of restructural cipher processor.
In one embodiment of the invention, the configuration compress mode includes：Reconfigurable arithmetic unit configures compression side
Formula, the configuration compress mode of row configuration compress mode and multiple reconfigurable arithmetic units as a whole.
In one embodiment of the invention, the diversification configuration information compression method, for each of after division
Subgraph, if the arithmetic operation of all reconfigurable arithmetic units in subgraph is identical, and interconnection architecture is identical, then according to division
Configuration compress mode determined by the structure feature information and interconnection features information of subgraph afterwards is the reconfigurable arithmetic unit
Configure compress mode, wherein it is described by the configuration compress mode to reconfigurable arithmetic unit corresponding to the subgraph
Configuration information and the configuration information of interconnection carry out compression configuration, including：For each subgraph, by corresponding reconfigurable arithmetic unit
Configuration information and each reconfigurable arithmetic unit between the configuration information of interconnection be stored in configuration memory, and save institute
It states the call number of configuration information and uses the corresponding relationship of the number of the reconfigurable arithmetic unit of the configuration information.
In one embodiment of the invention, the diversification configuration information compression method, if each after dividing
The structure of subgraph is all the same, then pressure is configured according to determined by the structure feature information of the subgraph after division and interconnection features information
Contracting mode is that the row configures compress mode, wherein it is described by the configuration compress mode to can corresponding to the subgraph
The configuration information of restructing operation unit and the information of interconnection carry out compression configuration, including：By the subgraph configuration information of a subgraph
It is stored in configuration memory, and saves the corresponding relationship of the number and the call number of the subgraph configuration information of subgraph, wherein
The subgraph configuration information includes the interconnection between the configuration information of reconfigurable arithmetic unit and each reconfigurable arithmetic unit
Configuration information.
In one embodiment of the invention, the diversification configuration information compression method, for each of after division
Subgraph, if the row in subgraph is identical as the arithmetic operation between row, and the capable interconnection architecture between row is identical, then basis is drawn
Configuration compress mode determined by the structure feature information and interconnection features information of subgraph after point is the multiple restructural fortune
Calculate unit configuration compress mode as a whole, wherein it is described by the configuration compress mode to corresponding to the subgraph
The configuration information of reconfigurable arithmetic unit and the configuration information of interconnection carry out compression configuration, including：For each subgraph, by a line
Row configuration information compression be stored in configuration memory, and save line number it is corresponding with the call number of the row configuration information pass
System, wherein the row configuration information includes between the configuration information of reconfigurable arithmetic unit and each reconfigurable arithmetic unit
Interconnect configuration information.
In order to achieve the above object, the diversification configuration information compression set of second aspect of the present invention embodiment, including generate mould
Block, for being planned cryptographic algorithm and being generated the corresponding data flow diagram of the cryptographic algorithm；First determining module is used for root
Common factor is extracted according to the repeat property of the data flow diagram, and determines the common factor redundancy of the common factor；Division module is used
In carrying out subgraph division to the data flow diagram according to restructural cipher processor hardware feature and the common factor redundancy；The
Two determining modules, for determining configuration compress mode according to the structure feature information and interconnection features information of the subgraph after division；
Compression module, for by the configuration compress mode to the configuration information of reconfigurable arithmetic unit corresponding to the subgraph and
The configuration information of interconnection carries out compression configuration.
The diversification configuration information compression set of the embodiment of the present invention plan to cryptographic algorithm by generation module
To corresponding data flow diagram, then the first determining module extracts common factor according to the repeat property of data flow diagram and determines common factor
Redundancy, division module carry out subgraph to data flow diagram further according to restructural cipher processor hardware feature and common factor redundancy
It divides, the second last determining module determines configuration compression according to the structure feature information and interconnection features information of ready-portioned subgraph
Mode carries out compression configuration to the configuration information of its reconfigurable arithmetic unit and the configuration information of interconnection using compression module, the dress
The calculating feature for setting combining cipher algorithm carrys out option and installment Information Compression mode, and is based on selected configuration information compress mode
Configuration information is compressed, the configuration information of redundancy is removed, and then the execution efficiency of restructural cipher processor can be improved.
In one embodiment of the invention, the configuration compress mode specifically includes：Reconfigurable arithmetic unit configuration pressure
Contracting mode, the configuration compress mode of row configuration compress mode and multiple reconfigurable arithmetic units as a whole.
In one embodiment of the invention, the diversification configuration information compression set, for each of after division
Subgraph, if the arithmetic operation of all reconfigurable arithmetic units in subgraph is identical, and interconnection architecture is identical, then and described second
It is institute that determining module configures compress mode according to determined by the structure feature information of the subgraph after division and interconnection features information
State reconfigurable arithmetic unit configuration compress mode, wherein the compression module is specifically used for：It, will be corresponding for each subgraph
The configuration information of interconnection between the configuration information of reconfigurable arithmetic unit and each reconfigurable arithmetic unit is stored in configuration and deposits
In reservoir, and save the call number of the configuration information and the number of the reconfigurable arithmetic unit using the configuration information
Corresponding relationship.
In one embodiment of the invention, the diversification configuration information compression set, diversification configuration information pressure
Contracting method, if the structure of each subgraph after dividing is all the same, second determining module is according to the subgraph after division
Configuration compress mode determined by structure feature information and interconnection features information is that the row configures compress mode, wherein described
Compression module is specifically used for：The subgraph configuration information of one subgraph is stored in configuration memory, and saves the number of subgraph
With the corresponding relationship of the call number of subgraph configuration information, wherein the subgraph configuration information includes matching for reconfigurable arithmetic unit
Interconnection configuration information between confidence breath and each reconfigurable arithmetic unit.
In one embodiment of the invention, the diversification configuration information compression set, for each of after division
Subgraph, if the arithmetic operation between row in subgraph and row is identical, and the capable interconnection architecture between row is identical, then and described the
Two determining modules configure compress mode according to determined by the structure feature information of the subgraph after division and interconnection features information
The configuration compress mode of the multiple reconfigurable arithmetic unit as a whole, wherein the compression module is specifically used for：For
The row configuration information compression of a line is stored in configuration memory, and saves line number and the row configuration information by each subgraph
Call number corresponding relationship, wherein the row configuration information includes the configuration information of reconfigurable arithmetic unit and each weighs
The configuration information of interconnection between structure arithmetic element.
The additional aspect of the present invention and advantage will be set forth in part in the description, and will partially become from the following description
Obviously, or practice through the invention is recognized.
Detailed description of the invention
Above-mentioned and/or additional aspect of the invention and advantage will become from the description of the embodiment in conjunction with the following figures
Obviously and it is readily appreciated that, wherein：
Fig. 1 is the schematic diagram of the configuration parameter compressed format of stratification according to an embodiment of the invention；
Fig. 2 is the schematic diagram of restructural cipher processor configuration control framework according to an embodiment of the invention；
Fig. 3 is the signal of three kinds of configuration informations of restructural cipher processor according to an embodiment of the invention and its effect
Figure；
Fig. 4 is the flow chart of diversification configuration information compression method according to an embodiment of the invention；
Fig. 5 is the diversification configuration information of reconfigurable arithmetic unit configuration compress mode according to an embodiment of the invention
The flow chart of compression method；
Fig. 6 is the schematic diagram of reconfigurable arithmetic unit configuration compress mode according to an embodiment of the invention；
Fig. 7 is the stream of the diversification configuration information compression method of row configuration compress mode according to an embodiment of the invention
Cheng Tu；
Fig. 8 is the schematic diagram of row configuration compress mode according to an embodiment of the invention；
Fig. 9 is the configuration compress mode of multiple reconfigurable arithmetic units according to an embodiment of the invention as a whole
The flow chart of diversification configuration information compression method；
Figure 10 is the signal of the configuration compress mode of multiple arithmetic elements according to an embodiment of the invention as a whole
Figure；
Figure 11 is the structural schematic diagram of diversification configuration information compression set according to an embodiment of the invention.
Specific embodiment
The embodiment of the present invention is described below in detail, examples of the embodiments are shown in the accompanying drawings, wherein from beginning to end
Same or similar label indicates same or similar element or element with the same or similar functions.Below with reference to attached
The embodiment of figure description is exemplary, it is intended to is used to explain the present invention, and is not considered as limiting the invention.
The present invention provides the diversification configuration information compression method on restructural cipher processor, as shown in Fig. 2, can weigh
Structure cipher processor is designed using Reconfiguration Technologies, a variety of passwords can be supported by the switching of configuration information on one piece of hardware
Algorithm (such as AES, SM3, ZUC, SHA256 etc.).Wherein mainly by reconfigurable configuration controller module 10, Reconfigurable Computation module
20 and the part of reconfigurable data control module 30 3 form, these three parts are all in itself by configuration parameter as information
Source, to determine which type of function restructural cipher processor is able to achieve.
Wherein, it is loaded with target password algorithm in configuration information and realizes required whole map informations on hardware.With confidence
The process for ceasing the mapping of restructural cipher processor hardware capability is：Firstly, configuration information enters restructural match by interface
Controller module 10 is set, the configuration information of 10 pairs of reconfigurable configuration controller module inputs parses, and generates corresponding
Configuration parameter and control signal, are then sent to Reconfigurable Computation module 20 and can for configuration parameter generated and control information
Reconstruct data control block 30.
In restructural cipher processor, the object being configured is mainly the restructural operation in Reconfigurable Computation module 20
Cell array RCA and reconfigurable data control module 30, wherein the function description of RCA mainly includes the function that each RC is realized
This two parts of interconnection architecture between RC.
Below with reference to Fig. 3 in restructural cipher processor three kinds of configuration informations and its effect be introduced.
As shown in figure 3, in restructural cipher processor for configuration level, needed for entire restructural cipher processor
Configuration information can be abstracted as three component parts：The configuration information of 1.RC；2. the configuration information of interconnection；3. data transmission is matched
Confidence breath.
Wherein, the configuration information of reconfigurable arithmetic unit RC mainly includes that target algorithm is shown in restructural cipher processor
When penetrating, function that the upper each RC of RCA is realized (such as the operation of arithmetic addition subtraction multiplication and division, shift operation, logical operation or fortune of tabling look-up
Calculate), this kind of configuration information shows as the corresponding different calculation function of different codings in parameter.
Wherein, the configuration information of interconnection mainly includes target algorithm in restructural cipher processor when upper mapping, RC it
Between input and output have how an interconnecting relation, this kind of configuration information shows as each RC input interface in parameter one
A corresponding data input coding, the corresponding different RC data source of different codings.
Wherein, the configuration information of data transmission mainly describes input data in calculating process, operation intermediate data and defeated
The whereabouts of data out is such as transmitted to RC internal register, data buffer storage channel, public heap register or output register etc..
When being configured to restructural cipher processor, the configuration information of reconfigurable arithmetic unit RC, interconnection configuration
In information and configuration information this three parts of data transmission, the configuration information amount of data transmission is smaller, and general without containing repeating
Part, therefore, to the compression of configuration information be primarily directed to the configuration information of reconfigurable arithmetic unit RC, interconnection with confidence
Breath.Since the two configuration information amount is very big, and repeating part is very more, has very strong compression space, therefore in order to reduce configuration
The redundancy of information, can the configuration information of the configuration information to reconfigurable arithmetic unit RC and interconnection carry out compression processing.
Below with reference to the accompanying drawings the diversification configuration information compression method and device of the embodiment of the present invention are described.
Fig. 4 is the flow chart of diversification configuration information compression method according to an embodiment of the invention.
As shown in figure 4, the diversification configuration information compression method may include：
S41 plans cryptographic algorithm and generates the corresponding data flow diagram of cryptographic algorithm.
It is understood that generally requiring the scale characteristic of associative array when mapping planning to cryptographic algorithm, designing
The corresponding data flow diagram of cryptographic algorithm (DFG, Data Flow Graph), data flow diagram can intuitively show mapping structure very much,
That is, data flow diagram can very intuitively the logic function, data of expression system internal system logic flow direction and logical conversion
Process.
S42 extracts common factor according to the repeat property of data flow diagram, and determines the common factor redundancy of common factor.
Specifically, first planning cryptographic algorithm and obtaining corresponding data flow diagram, it is then directed to resulting data flow diagram
Repeat property the higher part of multiplicity in data flow diagram is extracted, that is, extract common factor, and determination extract
Common factor common factor redundancy.
S43 carries out subgraph division to data flow diagram according to restructural cipher processor hardware feature and common factor redundancy.
S44 determines configuration compress mode according to the structure feature information of the subgraph after division and interconnection features information, and leads to
Configuration compress mode is crossed to compress the configuration information of reconfigurable arithmetic unit corresponding to subgraph and the configuration information of interconnection
Configuration.
Specifically, according to the structure feature information of the subgraph after division and interconnection features information, several compress modes are selected
In the configuration information of reconfigurable arithmetic unit and the configuration information of interconnection corresponding to most suitable a kind of pair of subgraph compress
Configuration.
It should be noted that the structure feature information of ready-portioned subgraph can be the fortune of reconfigurable arithmetic unit in subgraph
Calculate part reconfigurable arithmetic unit conduct in the structure and subgraph of the row and row between operation, continuous several rows of reconfigurable arithmetic units
It is whole, wherein there is identical reconfigurable arithmetic unit structure etc. between each entirety.
Wherein, the interconnection features information of ready-portioned subgraph can be reconfigurable arithmetic unit in subgraph interconnection situation,
Row in subgraph between continuous several rows of reconfigurable arithmetic units and part reconfigurable arithmetic unit in the interconnection architecture and subgraph of row
Interconnection architecture as a whole and its between entirety.
In one embodiment of the invention, configuration compress mode includes：Reconfigurable arithmetic unit configures compress mode, row
Configure the configuration compress mode of compress mode and multiple reconfigurable arithmetic units as a whole.
The diversification configuration information compression method of the embodiment of the present invention, it is corresponding by being planned to obtain to cryptographic algorithm
Then data flow diagram extracts common factor according to the repeat property of data flow diagram and determines common factor redundancy, further according to restructural
Cipher processor hardware feature and common factor redundancy carry out subgraph division to data flow diagram, finally according to ready-portioned subgraph
Structure feature information and interconnection features information determine configuration of the configuration compress mode to reconfigurable arithmetic unit corresponding to subgraph
Information and the configuration information of interconnection carry out compression configuration, and the calculating feature of this method combining cipher algorithm carrys out option and installment information pressure
Contracting mode, and configuration information is compressed based on selected configuration information compress mode, the configuration information of redundancy is removed, into
And the execution efficiency of restructural cipher processor can be improved.
Fig. 5 is the diversification configuration information of reconfigurable arithmetic unit configuration compress mode according to an embodiment of the invention
The flow chart of compression method.
It should be noted that restructural cipher processor Concurrent Feature with height when executing cryptographic algorithm, is doing
Many RC units are often had when Algorithm mapping and execute same function, and input and output interconnect as being also,
The configuration information of its corresponding RC and the configuration information of interconnection are also just the same.
For each subgraph after division, if the arithmetic operation of all reconfigurable arithmetic units in subgraph is identical, and
And interconnection architecture is identical, then compression is configured according to determined by the structure feature information of the subgraph after division and interconnection features information
Mode is that reconfigurable arithmetic unit configures compress mode.
Wherein, by configuring compress mode to the configuration information of reconfigurable arithmetic unit corresponding to subgraph and matching for interconnection
Confidence breath carries out compression configuration as shown in figure 5, the configuration compress mode is that reconfigurable arithmetic unit configures the polynary of compress mode
Changing configuration information compression method may include：
S51 plans cryptographic algorithm and generates the corresponding data flow diagram of cryptographic algorithm.
It is appreciated that generally requiring the scale characteristic of associative array when doing Algorithm mapping planning, designing algorithm
Corresponding data flow diagram (DFG), data flow diagram can intuitively show mapping structure very much.
S52 extracts common factor according to the repeat property of data flow diagram, and determines the common factor redundancy of common factor.
Specifically, first planning cryptographic algorithm and obtaining corresponding data flow diagram, it is then directed to resulting data flow diagram
Repeat property namely extraction common factor is extracted to multiplicity in data flow diagram higher part, and determine and extract
The common factor redundancy of common factor.
S53 carries out subgraph division to data flow diagram according to restructural cipher processor hardware feature and common factor redundancy.
S54, for each subgraph, by the configuration information of corresponding reconfigurable arithmetic unit and each reconfigurable arithmetic unit
Between the configuration information of interconnection be stored in configuration memory, and save the call number of configuration information and using configuration information
The corresponding relationship of the number of reconfigurable arithmetic unit.
The diversification configuration information compression method of the embodiment of the present invention, it is corresponding by being planned to obtain to cryptographic algorithm
Then data flow diagram extracts common factor according to the repeat property of data flow diagram and determines common factor redundancy, further according to restructural
Cipher processor hardware feature and common factor redundancy carry out subgraph division to data flow diagram, finally according to ready-portioned subgraph
Structure feature information and interconnection features information determine that configuration compress mode is that reconfigurable arithmetic unit configures compress mode to subgraph
The configuration information of corresponding reconfigurable arithmetic unit and the configuration information of interconnection carry out compression configuration, and this method combining cipher is calculated
The calculating feature of method carrys out option and installment Information Compression mode, and based on selected configuration information compress mode to configuration information into
Row compression, removes the configuration information of redundancy, and then the execution efficiency of restructural cipher processor can be improved.
Fig. 6 is the schematic diagram of arithmetic element configuration compress mode according to an embodiment of the invention.
As shown in fig. 6, the mapping can be abstracted into DFG (left figure in Fig. 6) when doing the planning of the mapping on RCA to algorithm,
After obtaining DFG, DFG can be divided into subgraph 1 and subgraph 2 in figure, wherein in subgraph 1 in such a way that subgraph divides
All RC all have same arithmetic operation, and the interconnection situation of these RC is also just the same.It is drawn in conjunction with such DFG
Point, the configuration information of the configuration information of the corresponding RC of subgraph and the corresponding interconnection of subgraph can be stored in configuration memory,
It is carrying out only needing be read the index for storing the configuration information when RC configuration, and is being numbered using the RC of the configuration, different RC are logical
Complete configuration in configuration memory can be accessed by crossing the same index, and configuration information needed for indexing the number plus RC
Amount is far smaller than their complete configuration information content, further such that the configuration information amount integrally read greatly reduces.
It is to be appreciated that it is only the implementation for illustrative purposes that data flow diagram DFG, which is divided into two subgraphs, in Fig. 6
The number for dividing subgraph is not defined in example, in practical applications, can according to restructural cipher processor hardware feature and
Data flow diagram is divided into other quantity subgraph by common factor redundancy, for example, data flow diagram can be divided to three subgraphs, or
Four subgraphs etc..
Fig. 7 is the stream of the diversification configuration information compression method of row configuration compress mode according to an embodiment of the invention
Cheng Tu.
It should be noted that the RCA on restructural cipher processor can be divided by row, reflected to cryptographic algorithm
During penetrating, by the division to DFG, so that the RC function in some subgraphs between each row and row, and mutual connection therebetween
Structure is just the same.At this moment the configuration information of their corresponding several reconfigurable arithmetic units and the configuration information of interconnection also complete phase
Together, at this time it will increase the number for reading configuration memory if still configuring compress mode using RC, to reduce configuration effect
Therefore rate while decrement is constant, can there is higher match by the way of row configuration compression in this case
Set efficiency.As shown in Figure 7：
S71 plans cryptographic algorithm and generates the corresponding data flow diagram of cryptographic algorithm.
It is appreciated that generally requiring the scale characteristic of associative array when doing Algorithm mapping planning, designing algorithm
Corresponding data flow diagram (DFG), data flow diagram can intuitively show mapping structure very much.
S72 extracts common factor according to the repeat property of data flow diagram, and determines the common factor redundancy of common factor.
Specifically, first planning cryptographic algorithm and obtaining corresponding data flow diagram, it is then directed to resulting data flow diagram
Repeat property namely extraction common factor is extracted to multiplicity in data flow diagram higher part, and determine and extract
The common factor redundancy of common factor.
S73 carries out subgraph division to data flow diagram according to restructural cipher processor hardware feature and common factor redundancy.
The subgraph configuration information of one subgraph is stored in configuration memory by S74, and saves the number and subgraph of subgraph
The corresponding relationship of the call number of configuration information, wherein subgraph configuration information includes the configuration information of reconfigurable arithmetic unit and each
The configuration information of interconnection between a reconfigurable arithmetic unit.
The diversification configuration information compression method of the embodiment of the present invention, it is corresponding by being planned to obtain to cryptographic algorithm
Then data flow diagram extracts common factor according to the repeat property of data flow diagram and determines common factor redundancy, further according to restructural
Cipher processor hardware feature and common factor redundancy carry out subgraph division to data flow diagram, finally according to ready-portioned subgraph
Structure feature information and interconnection features information determine that configuration compress mode is that row configuration compress mode is weighed to corresponding to subgraph
The configuration information of structure arithmetic element and the configuration information of interconnection carry out compression configuration, the calculating feature of this method combining cipher algorithm
Carry out option and installment Information Compression mode, and configuration information is compressed based on selected configuration information compress mode, removes
The configuration information of redundancy, and then the execution efficiency of restructural cipher processor can be improved.
Fig. 8 is the schematic diagram of row configuration compress mode according to an embodiment of the invention.
As shown in figure 8, after becoming two subgraphs shown in Fig. 8 left figure by division to the DFG of an algorithm, continuous several rows
It is capable just the same with the structure and function of row between RC, in conjunction with such DFG subgraph, the configuration information of a line can be compressed
It is stored in configuration memory, the corresponding index with configuration memory of row configuration need to be only read in configuration, several rows of RC use same
One index achievees the purpose that repetitive unit compresses, further substantially reduces configuration information total amount.Several RC unit institutes in the line
With under the different situation of function, higher configuration effect is compressed with compared to the RC configuration in reconfigurable arithmetic unit compress mode
Rate.
It is to be appreciated that it is only the implementation for illustrative purposes that data flow diagram DFG, which is divided into two subgraphs, in Fig. 8
The number for dividing subgraph is not defined in example, in practical applications, can according to restructural cipher processor hardware feature and
Data flow diagram is divided into other quantity subgraph by common factor redundancy, for example, data flow diagram can be divided to three subgraphs, or
Four subgraphs etc..
Fig. 9 is the configuration compress mode of multiple reconfigurable arithmetic units according to an embodiment of the invention as a whole
The flow chart of diversification configuration information compression method.
It should be noted that the more cryptographic algorithm of some cyclic parts is directed to, in order to guarantee to encrypt pile line operation
Efficiency, cyclic part in cryptographic algorithm can be carried out expansion be mapped on RCA, the corresponding configuration information of cyclic part is often
The same.Even sometimes acyclic part, after mapping is abstracted into DFG, still can be drawn by carrying out subgraph to DFG
Point, as a whole a part of RC, with duplicate reconfigurable arithmetic unit structure and mutually between different entirety
It is coupled structure, they have same configuration information.Such DFG division can provide compression space well.
S91 plans cryptographic algorithm and generates the corresponding data flow diagram of cryptographic algorithm.
It is appreciated that generally requiring the scale characteristic of associative array when doing Algorithm mapping planning, designing algorithm
Corresponding data flow diagram (DFG), data flow diagram can intuitively show mapping structure very much.
S92 extracts common factor according to the repeat property of data flow diagram, and determines the common factor redundancy of common factor.
Specifically, first planning cryptographic algorithm and obtaining corresponding data flow diagram, it is then directed to resulting data flow diagram
Repeat property namely extraction common factor is extracted to multiplicity in data flow diagram higher part, and determine and extract
The common factor redundancy of common factor.
S93 carries out subgraph division to data flow diagram according to restructural cipher processor hardware feature and common factor redundancy.
The row configuration information compression of a line is stored in configuration memory by S94 for each subgraph, and saves line number
With the corresponding relationship of the call number of row configuration information, wherein row configuration information include reconfigurable arithmetic unit configuration information and
The configuration information of interconnection between each reconfigurable arithmetic unit.
The diversification configuration information compression method of the embodiment of the present invention, it is corresponding by being planned to obtain to cryptographic algorithm
Then data flow diagram extracts common factor according to the repeat property of data flow diagram and determines common factor redundancy, further according to restructural
Cipher processor hardware feature and common factor redundancy carry out subgraph division to data flow diagram, finally according to ready-portioned subgraph
Structure feature information and interconnection features information determine that configuration compress mode is the configuration of multiple reconfigurable arithmetic units as a whole
Compress mode carries out compression configuration to the configuration information of reconfigurable arithmetic unit corresponding to subgraph and the configuration information of interconnection, should
The calculating feature of method combining cipher algorithm carrys out option and installment Information Compression mode, and is based on selected configuration information compression side
Formula compresses configuration information, removes the configuration information of redundancy, and then the execution efficiency of restructural cipher processor can be improved.
Figure 10 is the configuration compress mode of multiple reconfigurable arithmetic units according to an embodiment of the invention as a whole
Schematic diagram.
As shown in Figure 10, simplest situation is by taking loop unrolling as an example, and RPU_CRYPTO configures Encryption Algorithm, and DFG is drawn
It is divided into subgraph 1 and subgraph 2, executes the once-through operation after cyclic part is unfolded respectively, each alphabetical (A, B ... the) in figure represents
The structure of a kind of arithmetical operation, two subgraphs is just the same, is mapped on RCA, and the 1st~3 row RC executes subgraph 1, the 4th~6 row
RC executes subgraph 2.Configuration parameter needed for them be it is duplicate, in this case required for one cycle match confidence
Breath (including arithmetic element configuration information and interconnection configuration information) is stored in configuration memory, therefore, by the way of index just
It may be implemented to share the loop configuration information, greatly reduced configuration information amount.
It is to be appreciated that it is only the implementation for illustrative purposes that data flow diagram DFG, which is divided into two subgraphs, in Figure 10
The number for dividing subgraph is not defined in example, in practical applications, can according to restructural cipher processor hardware feature and
Data flow diagram is divided into other quantity subgraph by common factor redundancy, for example, data flow diagram can be divided to three subgraphs, or
Four subgraphs etc..
In order to realize above-described embodiment, the application also proposed a kind of diversification configuration information compression set.
Figure 11 is the structural schematic diagram of diversification configuration information compression set according to an embodiment of the invention.Such as Figure 11
Shown, which includes：Generation module 110, the first determining module 111, division module 112,
Two determining modules 113 and compression module 114, wherein：
Generation module 110 is for planning cryptographic algorithm and generating the corresponding data flow diagram of cryptographic algorithm.
First determining module 111 is used to extract common factor according to the repeat property of data flow diagram, and determines the public affairs of common factor
Factor redundancy.
Division module 112 be used for according to restructural cipher processor hardware feature and common factor redundancy to data flow diagram into
Row subgraph divides.
Second determining module 113 is used to be matched according to the determination of the structure feature information and interconnection features information of the subgraph after division
Set compress mode.
Compression module 114 is used for by configuring compress mode to the configuration information of reconfigurable arithmetic unit corresponding to subgraph
Compression configuration is carried out with the configuration information of interconnection.
In one embodiment of the invention, configuration compress mode includes：Reconfigurable arithmetic unit configures compress mode, row
Configure the configuration compress mode of compress mode and multiple reconfigurable arithmetic units as a whole.
In one embodiment of the invention, diversification configuration information compression set, for each subgraph after division, such as
The arithmetic operation of all reconfigurable arithmetic units in fruit figure is identical, and interconnection architecture is identical, then the second determining module 113
The configuration compress mode according to determined by the structure feature information of the subgraph after division and interconnection features information is restructural operation
Unit configures compress mode, wherein compression module 114 is specifically used for：For each subgraph, by corresponding reconfigurable arithmetic unit
Configuration information and each reconfigurable arithmetic unit between interconnection configuration information be stored in configuration memory, and save configuration
The corresponding relationship of the call number of information and the number of the reconfigurable arithmetic unit using configuration information.
In one embodiment of the invention, diversification configuration information compression set, diversification configuration information compression method,
If the structure of each subgraph after dividing is all the same, the second determining module 113 is according to the structure feature of the subgraph after division
Configuration compress mode determined by information and interconnection features information is row configuration compress mode, wherein compression module 114 is specifically used
In：The subgraph configuration information of one subgraph is stored in configuration memory, and saves the number and subgraph configuration information of subgraph
Call number corresponding relationship, wherein subgraph configuration information includes the configuration information of reconfigurable arithmetic unit and each restructural
The configuration information of interconnection between arithmetic element.
In one embodiment of the invention, diversification configuration information compression set, for each subgraph after division, such as
Row in fruit figure is identical as the arithmetic operation between row, and the capable interconnection architecture between row is identical, then the second determining module
The 113 configuration compress modes according to determined by the structure feature information of the subgraph after division and interconnection features information are multiple weigh
The configuration compress mode of structure arithmetic element as a whole, compression module 114 are specifically used for：For each subgraph, by the row of a line
Configuration information compression is stored in configuration memory, and saves the corresponding relationship of the call number of line number and row configuration information, wherein
Row configuration information includes the interconnection configuration information between the configuration information of reconfigurable arithmetic unit and each reconfigurable arithmetic unit.
It should be noted that the aforementioned explanation to diversification configuration information compression method embodiment is also applied for the reality
The diversification configuration information compression set of example is applied, details are not described herein again.
The diversification configuration information compression set of the embodiment of the present invention plan to cryptographic algorithm by generation module
To corresponding data flow diagram, then the first determining module extracts common factor according to the repeat property of data flow diagram and determines common factor
Redundancy, division module carry out subgraph to data flow diagram further according to restructural cipher processor hardware feature and common factor redundancy
It divides, the second last determining module determines configuration compression according to the structure feature information and interconnection features information of ready-portioned subgraph
Mode carries out compression configuration to the configuration information of the reconfigurable arithmetic unit of subgraph and the configuration information of interconnection using compression module,
The method achieve optimal configuration information compress mode can be selected, configuration effect is improved while reducing configuration information amount
Rate.
In the description of the present invention, it is to be understood that, term " first ", " second " are used for description purposes only, and cannot
It is interpreted as indication or suggestion relative importance or implicitly indicates the quantity of indicated technical characteristic.Define as a result, " the
One ", the feature of " second " can explicitly or implicitly include at least one of the features.In the description of the present invention, " multiple "
It is meant that at least two, such as two, three etc., unless otherwise specifically defined.
In the description of this specification, reference term " one embodiment ", " some embodiments ", " example ", " specifically show
The description of example " or " some examples " etc. means specific features, structure, material or spy described in conjunction with this embodiment or example
Point is included at least one embodiment or example of the invention.In the present specification, schematic expression of the above terms are not
It must be directed to identical embodiment or example.Moreover, particular features, structures, materials, or characteristics described can be in office
It can be combined in any suitable manner in one or more embodiment or examples.In addition, without conflicting with each other, the skill of this field
Art personnel can tie the feature of different embodiments or examples described in this specification and different embodiments or examples
It closes and combines.
Any process described otherwise above or method description are construed as in flow chart or herein, and expression includes
It is one or more for realizing specific logical function or process the step of executable instruction code module, segment or portion
Point, and the range of the preferred embodiment of the present invention includes other realization, wherein can not press shown or discussed suitable
Sequence, including according to related function by it is basic simultaneously in the way of or in the opposite order, to execute function, this should be of the invention
Embodiment person of ordinary skill in the field understood.
It should be appreciated that each section of the invention can be realized with hardware, software, firmware or their combination.Above-mentioned
In embodiment, software that multiple steps or method can be executed in memory and by suitable instruction execution system with storage
Or firmware is realized.It, and in another embodiment, can be under well known in the art for example, if realized with hardware
Any one of column technology or their combination are realized：With for realizing the logic gates of logic function to data-signal
Discrete logic, with suitable combinational logic gate circuit specific integrated circuit, programmable gate array (PGA), scene
Programmable gate array (FPGA) etc..
Those skilled in the art are understood that realize all or part of step that above-described embodiment method carries
It suddenly is that relevant hardware can be instructed to complete by program, the program can store in a kind of computer-readable storage medium
In matter, which when being executed, includes the steps that one or a combination set of embodiment of the method.
It, can also be in addition, each functional unit in each embodiment of the present invention can integrate in a processing module
It is that each unit physically exists alone, can also be integrated in two or more units in a module.Above-mentioned integrated mould
Block both can take the form of hardware realization, can also be realized in the form of software function module.The integrated module is such as
Fruit is realized and when sold or used as an independent product in the form of software function module, also can store in a computer
In read/write memory medium.
Storage medium mentioned above can be read-only memory, disk or CD etc..Although having been shown and retouching above
The embodiment of the present invention is stated, it is to be understood that above-described embodiment is exemplary, and should not be understood as to limit of the invention
System, those skilled in the art can be changed above-described embodiment, modify, replace and become within the scope of the invention
Type.
Claims (8)
1. a kind of diversification configuration information compression method, which is characterized in that include the following steps：
Cryptographic algorithm is planned and generates the corresponding data flow diagram of the cryptographic algorithm；
Common factor is extracted according to the repeat property of the data flow diagram, and determines the common factor redundancy of the common factor；
Subgraph division is carried out to the data flow diagram according to restructural cipher processor hardware feature and the common factor redundancy；
And
Configuration compress mode is determined according to the structure feature information of the subgraph after division and interconnection features information, and is matched by described
Compress mode is set to compress the configuration information of reconfigurable arithmetic unit corresponding to the subgraph and the configuration information of interconnection
Configuration；Wherein, the configuration compress mode includes：Reconfigurable arithmetic unit configures compress mode, row configures compress mode and more
The configuration compress mode of a reconfigurable arithmetic unit as a whole.
2. diversification configuration information compression method as described in claim 1, which is characterized in that for every height after division
Figure, if the arithmetic operation of all reconfigurable arithmetic units in subgraph is identical, and interconnection architecture is identical, then according to division after
Subgraph structure feature information and interconnection features information determined by configuration compress mode be the reconfigurable arithmetic unit match
Set compress mode, wherein
The configuration information and interconnection by the configuration compress mode to reconfigurable arithmetic unit corresponding to the subgraph
Configuration information carry out compression configuration, including：
It, will be mutual between the configuration information of corresponding reconfigurable arithmetic unit and each reconfigurable arithmetic unit for each subgraph
The configuration information of connection is stored in configuration memory, and is saved the call number of the configuration information and used the configuration information
The corresponding relationship of the number of the reconfigurable arithmetic unit.
3. diversification configuration information compression method as described in claim 1, which is characterized in that if each subgraph after dividing
Structure it is all the same, then according to determined by the structure feature information of the subgraph after division and interconnection features information configure compression side
Formula is that the row configures compress mode, wherein
The configuration information and interconnection by the configuration compress mode to reconfigurable arithmetic unit corresponding to the subgraph
Configuration information carry out compression configuration, including：
The subgraph configuration information of one subgraph is stored in configuration memory, and saves the number and subgraph configuration of subgraph
The corresponding relationship of the call number of information, wherein the subgraph configuration information includes the configuration information of reconfigurable arithmetic unit and each
The configuration information of interconnection between a reconfigurable arithmetic unit.
4. diversification configuration information compression method as described in claim 1, which is characterized in that for every height after division
Figure, if the row in subgraph is identical as the arithmetic operation between row, and the capable interconnection architecture between row is identical, then according to division
Configuration compress mode determined by the structure feature information and interconnection features information of subgraph afterwards is the multiple restructural operation
The configuration compress mode of unit as a whole, wherein
The configuration information and interconnection by the configuration compress mode to reconfigurable arithmetic unit corresponding to the subgraph
Configuration information carry out compression configuration, including：
For each subgraph, the row configuration information compression of a line is stored in configuration memory, and saves line number and the row
The corresponding relationship of the call number of configuration information, wherein the row configuration information include reconfigurable arithmetic unit configuration information and
The configuration information of interconnection between each reconfigurable arithmetic unit.
5. a kind of diversification configuration information compression set, which is characterized in that including：
Generation module, for being planned cryptographic algorithm and being generated the corresponding data flow diagram of the cryptographic algorithm；
First determining module for extracting common factor according to the repeat property of the data flow diagram, and determines the common factor
Common factor redundancy；
Division module is used for according to restructural cipher processor hardware feature and the common factor redundancy to the data flow diagram
Carry out subgraph division；
Second determining module, for determining configuration compression according to the structure feature information and interconnection features information of the subgraph after division
Mode；Wherein, the configuration compress mode specifically includes：Reconfigurable arithmetic unit configures compress mode, row configuration compress mode
With the configuration compress mode of multiple reconfigurable arithmetic units as a whole；
Compression module, for matching confidence to reconfigurable arithmetic unit corresponding to the subgraph by the configuration compress mode
Breath and the configuration information of interconnection carry out compression configuration.
6. diversification configuration information compression set as claimed in claim 5, which is characterized in that for every height after division
Figure, if the arithmetic operation of all reconfigurable arithmetic units in subgraph is identical, and interconnection architecture is identical, then described second really
Configuration compress mode is described determined by structure feature information and interconnection features information of the cover half root tuber according to the subgraph after division
Reconfigurable arithmetic unit configures compress mode, wherein
The compression module, is specifically used for：
It, will be mutual between the configuration information of corresponding reconfigurable arithmetic unit and each reconfigurable arithmetic unit for each subgraph
The configuration information of connection is stored in configuration memory, and is saved the call number of the configuration information and used the configuration information
The corresponding relationship of the number of the reconfigurable arithmetic unit.
7. diversification configuration information compression set as claimed in claim 5, which is characterized in that diversification configuration information compression side
Method, which is characterized in that if the structure of each subgraph after dividing is all the same, after second determining module is according to division
Configuration compress mode determined by the structure feature information and interconnection features information of subgraph is that the row configures compress mode,
In,
The compression module, is specifically used for：
The subgraph configuration information of one subgraph is stored in configuration memory, and saves the number and subgraph configuration of subgraph
The corresponding relationship of the call number of information, wherein the subgraph configuration information includes the configuration information of reconfigurable arithmetic unit and each
The configuration information of interconnection between a reconfigurable arithmetic unit.
8. diversification configuration information compression set as claimed in claim 5, which is characterized in that for every height after division
Figure, if the arithmetic operation between row in subgraph and row is identical, and the capable interconnection architecture between row is identical, then and described second
It is institute that determining module configures compress mode according to determined by the structure feature information of the subgraph after division and interconnection features information
State the configuration compress mode of multiple reconfigurable arithmetic units as a whole, wherein
The compression module, is specifically used for：
For each subgraph, the row configuration information compression of a line is stored in configuration memory, and saves line number and the row
The corresponding relationship of the call number of configuration information, wherein the row configuration information include reconfigurable arithmetic unit configuration information and
The configuration information of interconnection between each reconfigurable arithmetic unit.
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| CN102508816A (en) * | 2011-11-15 | 2012-06-20 | 东南大学 | Configuration method applied to coarse-grained reconfigurable array |
| CN103914404A (en) * | 2014-04-29 | 2014-07-09 | 东南大学 | Configuration information cache device in coarseness reconfigurable system and compression method |
| CN103942181A (en) * | 2014-03-31 | 2014-07-23 | 清华大学 | Method and device for generating configuration information of dynamic reconfigurable processor |
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| CN102508816A (en) * | 2011-11-15 | 2012-06-20 | 东南大学 | Configuration method applied to coarse-grained reconfigurable array |
| CN103942181A (en) * | 2014-03-31 | 2014-07-23 | 清华大学 | Method and device for generating configuration information of dynamic reconfigurable processor |
| CN103914404A (en) * | 2014-04-29 | 2014-07-09 | 东南大学 | Configuration information cache device in coarseness reconfigurable system and compression method |
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