CN105760784A - Diversified configuration information compression method and device - Google Patents
Diversified configuration information compression method and device Download PDFInfo
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Abstract
The invention discloses a diversified configuration information compressing method and device.The method comprises the steps that a cryptographic algorithm is planned, and a data flow diagram corresponding to the cryptographic algorithm is generated; a common factor is extracted according to the repetition characteristic of the data flow diagram, and the common factor redundancy rate of the common factor is determined; sub-diagram partitioning is performed on the data flow diagram according to the hardware characteristic of a reconfigurable password processor and the common factor redundancy rate; a configuration compressing mode is determined according to structural characteristic information of partitioned sub-diagrams and interconnection characteristic information, and compressing configuration is performed on configuration information of reconfigurable arithmetic units corresponding to the sub-diagrams and interconnected configuration information through the configuration compressing mode.According to the method, the configuration information compressing mode is selected by combining the calculation characteristic of the cryptographic algorithm, the configuration information is compressed on the basis of the selected configuration information compressing mode to remove the redundant configuration information, and then the execution efficiency of the configurable password processor can be improved.
Description
Technical field
The present invention relates to electronic technology field, particularly relate to a kind of diversification configuration information compression method and device.
Background technology
Restructural cipher processor (PRU_CRYPTO), employ a kind of coarseness reconfigurable processor framework, combine the motility of software and the high efficiency of hardware, it is possible not only to change control stream by general reconfigurable arithmetic unit array RCA (ReconfigurableComputingArray) carries out dynamically configuration, data path can also be changed, the cryptographic algorithm that dynamic implement is different, and the hardware resource of restructural Cipher Processing itself is without any safety information.Restructural Cipher Processing has that high-performance, low-power consumption, motility be good, the advantage of favorable expandability, it is suitable for processing the cryptographic algorithm of computation-intensive, such as, Advanced Encryption Standard (AdvancedEncryptionStandard, AES), SM3, ZUC, SHA SHA256 (SecureHashAlgorithm, SHA) etc..Therefore, restructural cipher processor has good application prospect, also can meet the multi-level security requirement of different cryptographic consumer and demand that cryptographic algorithm constantly upgrades.
The computing main body of restructural cipher processor is reconfigurable arithmetic unit array, in the RCA of restructural cipher processor, determine reconfigurable arithmetic unit RC (ReconfigurableComputing) function realized by configuration parameter, between RC, its interconnection architecture can also be determined by configuration parameter.By the planning that algorithm is mapped on RCA, it is determined which kind of function each RC realizes, and between RC, interconnection is how, and generates corresponding configuration parameter, and the high-speed parallel that can realize data stream well processes.But different cryptographic algorithms have repetitive structure in various degree, such as, the function that a lot of RC use is just the same, at this moment each RC still adopts independent configuration parameter will result in parameter repeat and redundancy, thus having a strong impact on allocative efficiency, and then affect the efficiency of dynamic implement cryptographic algorithm, namely affect the execution efficiency of restructural cipher processor.
In order to reduce the size of configuration information, improving allocative efficiency, propose the compression method of a kind of stratification configuration in correlation technique, as it is shown in figure 1, Fig. 1 illustrates the compression method of a kind of stratification configuration, its compression method is as follows:
Assuming that partial data flow graph (DFG, DataFlowGraph) corresponding to core algorithm is divided into multiple subgraph, subgraph is correspondence configuration 1,2,3 respectively from top to bottom.And each configuration includes input, calculates, three parts of output.Wherein, as seen in Figure 1, the output of 1 and the input of configuration 2 are configured, dependence between them is clear and definite, the data input address of configuration 2 be exactly configure 1 address data output, in order to reduce the size of configuration information, the configuration of this part can be omitted, automatically distributed by system.The particular content of the configuration memorizer storage configuration 1,2,3 of one inside is set, outside just has only to tell reconfigurable processor (RPU, ReconfigurableProcessingUnit): the address of array input 1 and output 3, and configuration index call the order list address list of 1,2,3 (configuration).These information just constitute configuration group.What partial data flow graph was corresponding is configuration group, and therefore configuration combinational algorithm is corresponding, is that the one-level of configuration system is abstract.The information of these configuration groups is equally possible to be stored in inside reconfigurable processor, and outside has only to by write data I/O Address and configuration group sequence number.The sequence sets of configuration group is corresponding with application, and this is that two grades of configuration system are abstract.The set of outside write configuration words, intermediate layer configuration information (concrete algorithm, configuration group) is indexed by configuring, bottom configuration information (concrete Mapping implementation, including the content such as selection of operator, routing function) is indexed again by intermediate layer configuration information.
This method can compress the amount of configuration data that RPU seam needs to read in a large number, thus the bottom configuration information of original magnanimity calls programming secondary index table.But, the whole compress mode of this method is comparatively single, at restructural cipher processor only with the mode that configuration parameter is carried out configuration group division, do not carry out configuration information compression storage for the different respective estimated performances of cryptographic algorithm, under some application scenario, the data total amount of its bottom configuration parameter can not most optimally reduce, and the configuration information of some repetitive structures is likely to still to exist in the expanded form, thus causing configuration information redundancy.
Summary of the invention
The purpose of the present invention is intended to solve at least to a certain extent one of above-mentioned technical problem.
For this, first purpose of the present invention is in that to propose a kind of diversification configuration information compression method.The calculating feature of the method combining cipher algorithm carrys out option and installment Information Compression mode, and based on selected configuration information compress mode, configuration information is compressed, and removes the configuration information of redundancy, and then can improve the execution efficiency of restructural cipher processor.
Second purpose of the present invention is in that to propose a kind of diversification configuration information compressor.
For reaching above-mentioned purpose, the diversification configuration information compression method of first aspect present invention embodiment, including: cryptographic algorithm is planned and generates the data flow diagram that described cryptographic algorithm is corresponding；Repeat property according to described data flow diagram extracts common factor, and determines the common factor redundancy of described common factor；According to restructural cipher processor ardware feature and described common factor redundancy, described data flow diagram is carried out subgraph division；And determine configuration compress mode according to the structure feature information of subgraph after dividing and interconnection features information, and it is compressed configuring to the configuration information of reconfigurable arithmetic unit corresponding to described subgraph and the configuration information of interconnection by described configuration compress mode.
The diversification configuration information compression method of the embodiment of the present invention, corresponding data flow diagram is obtained by cryptographic algorithm is carried out planning, then extract common factor according to the repeat property of data flow diagram and determine common factor redundancy, further according to restructural cipher processor ardware feature and common factor redundancy, data flow diagram is carried out subgraph division, structure feature information and interconnection features information finally according to ready-portioned subgraph determine that the configuration information of its reconfigurable arithmetic unit and the configuration information of interconnection are compressed configuration by configuration compress mode, the calculating feature of the method combining cipher algorithm carrys out option and installment Information Compression mode, and based on selected configuration information compress mode, configuration information is compressed, remove the configuration information of redundancy, and then the execution efficiency of restructural cipher processor can be improved.
In one embodiment of the invention, described configuration compress mode includes: reconfigurable arithmetic unit configuration compress mode, row configuration compress mode and multiple reconfigurable arithmetic unit are as overall configuration compress mode.
nullIn one embodiment of the invention，Described diversification configuration information compression method，For each subgraph after dividing，If the arithmetic operation of all reconfigurable arithmetic units in subgraph is identical，And interconnection architecture is identical，It is then described reconfigurable arithmetic unit configuration compress mode according to the structure feature information of subgraph after dividing and interconnection features information determined configuration compress mode，Wherein，The described configuration information of reconfigurable arithmetic unit corresponding to described subgraph and the configuration information of interconnection being compressed by described configuration compress mode is configured，Including: for each subgraph，The configuration information of the interconnection between configuration information and each reconfigurable arithmetic unit of corresponding reconfigurable arithmetic unit is stored in configuration memorizer，And preserve the call number of described configuration information and the corresponding relation of the numbering of the described reconfigurable arithmetic unit using described configuration information.
In one embodiment of the invention, described diversification configuration information compression method, if the structure of each subgraph after dividing is all identical, it is then described row configuration compress mode according to the structure feature information of subgraph after dividing and interconnection features information determined configuration compress mode, wherein, the described configuration information of reconfigurable arithmetic unit corresponding to described subgraph and the information of interconnection being compressed by described configuration compress mode is configured, including: the subgraph configuration information of a subgraph is stored in configuration memorizer, and preserve the numbering of subgraph and the corresponding relation of the call number of described subgraph configuration information, wherein, described subgraph configuration information includes the configuration information of the interconnection between the configuration information of reconfigurable arithmetic unit and each reconfigurable arithmetic unit.
nullIn one embodiment of the invention，Described diversification configuration information compression method，For each subgraph after dividing，If the row in subgraph is identical with the arithmetic operation between row，And go identical with the interconnection architecture between row，It is then that the plurality of reconfigurable arithmetic unit is as overall configuration compress mode according to the structure feature information of subgraph after dividing and interconnection features information determined configuration compress mode，Wherein，The described configuration information of reconfigurable arithmetic unit corresponding to described subgraph and the configuration information of interconnection being compressed by described configuration compress mode is configured，Including: for each subgraph，The row configuration information of a line is compressed and is stored in configuration memorizer，And preserve the corresponding relation of line number and the call number of described row configuration information，Wherein，Described row configuration information includes the interconnection configuration information between the configuration information of reconfigurable arithmetic unit and each reconfigurable arithmetic unit.
For reaching above-mentioned purpose, the diversification configuration information compressor of second aspect present invention embodiment, including generation module, for cryptographic algorithm being planned and generating the data flow diagram that described cryptographic algorithm is corresponding；First determines module, extracts common factor for the repeat property according to described data flow diagram, and determines the common factor redundancy of described common factor；Divide module, for described data flow diagram being carried out subgraph division according to restructural cipher processor ardware feature and described common factor redundancy；Second determines module, determines configuration compress mode for the structure feature information according to the subgraph after dividing and interconnection features information；Compression module, for being compressed configuring to the configuration information of reconfigurable arithmetic unit corresponding to described subgraph and the configuration information of interconnection by described configuration compress mode.
nullThe diversification configuration information compressor of the embodiment of the present invention，By generation module, cryptographic algorithm is carried out planning and obtain corresponding data flow diagram，Then first determines that module is extracted common factor according to the repeat property of data flow diagram and determines common factor redundancy，Divide module, further according to restructural cipher processor ardware feature and common factor redundancy, data flow diagram is carried out subgraph division，The second last determines according to structure feature information and the interconnection features information of ready-portioned subgraph, module determines that configuration compress mode utilizes compression module that the configuration information of its reconfigurable arithmetic unit and the configuration information of interconnection are compressed configuration，The calculating feature of this device combining cipher algorithm carrys out option and installment Information Compression mode，And based on selected configuration information compress mode, configuration information is compressed，Remove the configuration information of redundancy，And then the execution efficiency of restructural cipher processor can be improved.
In one embodiment of the invention, described configuration compress mode specifically includes: reconfigurable arithmetic unit configuration compress mode, row configuration compress mode and multiple reconfigurable arithmetic unit are as overall configuration compress mode.
In one embodiment of the invention, described diversification configuration information compressor, for each subgraph after dividing, if the arithmetic operation of all reconfigurable arithmetic units in subgraph is identical, and interconnection architecture is identical, then described second determines that module is described reconfigurable arithmetic unit configuration compress mode according to structure feature information and the interconnection features information determined configuration compress mode of the subgraph after dividing, wherein, described compression module, specifically for: for each subgraph, the configuration information of the interconnection between configuration information and each reconfigurable arithmetic unit of corresponding reconfigurable arithmetic unit is stored in configuration memorizer, and preserve the call number of described configuration information and the corresponding relation of the numbering of the described reconfigurable arithmetic unit using described configuration information.
In one embodiment of the invention, described diversification configuration information compressor, diversification configuration information compression method, if the structure of each subgraph after dividing is all identical, then described second determines that module is described row configuration compress mode according to structure feature information and the interconnection features information determined configuration compress mode of the subgraph after dividing, wherein, described compression module, specifically for: the subgraph configuration information of a subgraph is stored in configuration memorizer, and preserve the corresponding relation of the numbering of subgraph and the call number of subgraph configuration information, wherein, described subgraph configuration information includes the interconnection configuration information between the configuration information of reconfigurable arithmetic unit and each reconfigurable arithmetic unit.
In one embodiment of the invention, described diversification configuration information compressor, for each subgraph after dividing, if the row in subgraph is identical with the arithmetic operation between row, and go identical with the interconnection architecture between row, then described second determines that module is that the plurality of reconfigurable arithmetic unit is as overall configuration compress mode according to structure feature information and the interconnection features information determined configuration compress mode of the subgraph after dividing, wherein, described compression module, specifically for: for each subgraph, the row configuration information of a line is compressed and is stored in configuration memorizer, and preserve the corresponding relation of line number and the call number of described row configuration information, wherein, described row configuration information includes the configuration information of the interconnection between the configuration information of reconfigurable arithmetic unit and each reconfigurable arithmetic unit.
Aspect and advantage that the present invention adds will part provide in the following description, and part will become apparent from the description below, or is recognized by the practice of the present invention.
Accompanying drawing explanation
Above-mentioned and/or the additional aspect of the present invention and advantage are from conjunction with will be apparent from easy to understand the accompanying drawings below description to embodiment, wherein:
Fig. 1 is the schematic diagram of the configuration parameter compressed format of stratification according to an embodiment of the invention；
Fig. 2 is the schematic diagram of restructural cipher processor configuration control framework according to an embodiment of the invention；
Fig. 3 is the schematic diagram of three kinds of configuration informations of restructural cipher processor and effect thereof according to an embodiment of the invention；
Fig. 4 is the flow chart of diversification configuration information compression method according to an embodiment of the invention；
Fig. 5 is the flow chart of the diversification configuration information compression method of reconfigurable arithmetic unit configuration compress mode according to an embodiment of the invention；
Fig. 6 is the schematic diagram of reconfigurable arithmetic unit configuration compress mode according to an embodiment of the invention；
Fig. 7 goes the flow chart of diversification configuration information compression method of configuration compress mode according to an embodiment of the invention；
Fig. 8 is the schematic diagram gone according to an embodiment of the invention and configure compress mode；
Fig. 9 is multiple according to an embodiment of the invention reconfigurable arithmetic unit flow chart as the diversification configuration information compression method of overall configuration compress mode；
Figure 10 is multiple according to an embodiment of the invention arithmetic element schematic diagram as overall configuration compress mode；
Figure 11 is the structural representation of diversification configuration information compressor according to an embodiment of the invention.
Detailed description of the invention
Being described below in detail embodiments of the invention, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has the element of same or like function from start to finish.The embodiment described below with reference to accompanying drawing is illustrative of, it is intended to is used for explaining the present invention, and is not considered as limiting the invention.
The present invention provides the diversification configuration information compression method on restructural cipher processor, as shown in Figure 2, restructural cipher processor adopts Reconfiguration Technologies design, on one piece of hardware, can support that multiple cryptographic algorithm is (such as AES by the switching of configuration information, SM3, ZUC, SHA256 etc.).Wherein mainly controlled 30 3 parts of module by reconfigurable configuration controller module 10, Reconfigurable Computation module 20 and reconfigurable data to form, these three part is all as information source in itself by configuration parameter, in order to determine which type of function restructural cipher processor can realize.
Wherein, configuration information is loaded with target password algorithm on hardware, realizes required whole map informations.Configuration information to the process of the mapping of restructural cipher processor hardware capability is: first, configuration information enters reconfigurable configuration controller module 10 by interface, the configuration information of input is resolved by this reconfigurable configuration controller module 10, and generate corresponding configuration parameter and control signal, then the configuration parameter generated and control information are sent to Reconfigurable Computation module 20 and reconfigurable data control module 30.
In restructural cipher processor, the object being configured is mainly the reconfigurable arithmetic unit array RCA in Reconfigurable Computation module 20 and reconfigurable data controls module 30, wherein, the function of RCA describes and mainly includes these two parts of interconnection architecture between each RC function and RC realized.
Below in conjunction with Fig. 3, three kinds of configuration informations in restructural cipher processor and effect thereof are introduced.
As it is shown on figure 3, configuration aspect in restructural cipher processor, configuration information required in whole restructural cipher processor can abstract be the configuration information of three ingredient: 1.RC；2. the configuration information of interconnection；3. the configuration information of data transmission.
Wherein, the configuration information of reconfigurable arithmetic unit RC mainly includes target algorithm when mapping on restructural cipher processor, the function (such as the computing of arithmetic addition subtraction multiplication and division, shift operation, logical operations or table lookup operations) that RCA each RC upper realizes, this kind of configuration information shows as the calculation function that different codings is corresponding different in parameter.
Wherein, interconnection configuration information mainly include target algorithm in restructural cipher processor on map time, input and output between RC have a how interconnecting relation, this kind of configuration information shows as each RC input interface in parameter a corresponding data input coding, the RC Data Source that different codings is corresponding different.
Wherein, the configuration information of data transmission mainly describes the whereabouts of the input data in calculating process, computing intermediate data and output data, such as transmission to RC internal register, data buffer storage passage, public heap depositor or output register etc..
When restructural cipher processor is configured, in the configuration information of reconfigurable arithmetic unit RC, the configuration information of interconnection and this three part of configuration information of data transmission, the configuration information amount of data transmission is less, and generally do not contain repeating part, therefore, the compression of configuration information is primarily directed to the configuration information of the configuration information of reconfigurable arithmetic unit RC, interconnection.Owing to the two configuration information amount is very big, and repeating part is very many, has very strong compression stroke, therefore in order to reduce the redundancy of configuration information, can be compressed the configuration information of the configuration information of reconfigurable arithmetic unit RC Yu interconnection processing.
Below with reference to the accompanying drawings diversification configuration information compression method and the device of the embodiment of the present invention are described.
Fig. 4 is the flow chart of diversification configuration information compression method according to an embodiment of the invention.
As shown in Figure 4, this diversification configuration information compression method may include that
S41, plans cryptographic algorithm and generates the data flow diagram that cryptographic algorithm is corresponding.
It is understandable that, when cryptographic algorithm is mapped planning, generally require the scale characteristic of associative array, design the data flow diagram (DFG that cryptographic algorithm is corresponding, DataFlowGraph), data flow diagram can show mapping structure very intuitively, i.e. data flow diagram can the logic function of expression system, data flow to and logistic transformation process in the logic of internal system very intuitively.
S42, extracts common factor according to the repeat property of data flow diagram, and determines the common factor redundancy of common factor.
Specifically, first cryptographic algorithm planned and obtain corresponding data flow diagram, then for the repeat property of the data flow diagram of gained, the part that multiplicity in data flow diagram is higher is extracted, namely extract common factor, and determine the common factor redundancy of the common factor extracted.
S43, carries out subgraph division according to restructural cipher processor ardware feature and common factor redundancy to data flow diagram.
S44, determines configuration compress mode according to the structure feature information of the subgraph after dividing and interconnection features information, and by configuring compress mode, the configuration information of the reconfigurable arithmetic unit corresponding to subgraph and the configuration information of interconnection is compressed configuration.
Specifically, according to the structure feature information of the subgraph after dividing and interconnection features information, the most suitable a kind of configuration information of the reconfigurable arithmetic unit corresponding to subgraph and the configuration information of interconnection are compressed in several compress mode is selected to configure.
It should be noted that, the structure feature information of ready-portioned subgraph can be the row between the arithmetic operation of reconfigurable arithmetic unit in subgraph, continuous several rows reconfigurable arithmetic unit and row structure and subgraph in part reconfigurable arithmetic unit as entirety, wherein, between each entirety, there is identical reconfigurable arithmetic unit structure etc..
Wherein, the interconnection features information of ready-portioned subgraph can be in the interconnection architecture of row between continuous several rows reconfigurable arithmetic unit and row in the interconnection situation of reconfigurable arithmetic unit in subgraph, subgraph and subgraph part reconfigurable arithmetic unit as the interconnection architecture between overall and entirety.
In one embodiment of the invention, configuration compress mode includes: reconfigurable arithmetic unit configuration compress mode, row configuration compress mode and multiple reconfigurable arithmetic unit are as overall configuration compress mode.
The diversification configuration information compression method of the embodiment of the present invention, corresponding data flow diagram is obtained by cryptographic algorithm is carried out planning, then extract common factor according to the repeat property of data flow diagram and determine common factor redundancy, further according to restructural cipher processor ardware feature and common factor redundancy, data flow diagram is carried out subgraph division, structure feature information and interconnection features information finally according to ready-portioned subgraph determine that the configuration information of the reconfigurable arithmetic unit corresponding to subgraph and the configuration information of interconnection are compressed configuration by configuration compress mode, the calculating feature of the method combining cipher algorithm carrys out option and installment Information Compression mode, and based on selected configuration information compress mode, configuration information is compressed, remove the configuration information of redundancy, and then the execution efficiency of restructural cipher processor can be improved.
Fig. 5 is the flow chart of the diversification configuration information compression method of reconfigurable arithmetic unit configuration compress mode according to an embodiment of the invention.
It should be noted that; restructural cipher processor has the Concurrent Feature of height when performing cryptographic algorithm; often have a lot of RC unit when doing Algorithm mapping and perform same function; and input and output interconnection is also the same, and namely the configuration information of the RC of its correspondence and the configuration information of interconnection are also just the same.
For each subgraph after dividing, if the arithmetic operation of all reconfigurable arithmetic units in subgraph is identical, and interconnection architecture is identical, then it is reconfigurable arithmetic unit configuration compress mode according to the structure feature information of subgraph after dividing and the determined configuration compress mode of interconnection features information.
Wherein, the configuration information of the reconfigurable arithmetic unit corresponding to subgraph and the configuration information of interconnection are compressed configuration as it is shown in figure 5, the diversification configuration information compression method that this configuration compress mode is reconfigurable arithmetic unit configuration compress mode may include that by configuring compress mode
S51, plans cryptographic algorithm and generates the data flow diagram that cryptographic algorithm is corresponding.
Being appreciated that when doing Algorithm mapping planning, generally requiring the scale characteristic of associative array, design data flow diagram corresponding to algorithm (DFG), data flow diagram can show mapping structure very intuitively.
S52, extracts common factor according to the repeat property of data flow diagram, and determines the common factor redundancy of common factor.
Specifically, first cryptographic algorithm planned and obtain corresponding data flow diagram, then for the repeat property of the data flow diagram of gained the part that multiplicity in data flow diagram is higher extracted and namely extract common factor, and determine the common factor redundancy of the common factor extracted.
S53, carries out subgraph division according to restructural cipher processor ardware feature and common factor redundancy to data flow diagram.
S54, for each subgraph, the configuration information of the interconnection between configuration information and each reconfigurable arithmetic unit of corresponding reconfigurable arithmetic unit is stored in configuration memorizer, and preserves the call number of configuration information and the corresponding relation of the numbering of the reconfigurable arithmetic unit using configuration information.
nullThe diversification configuration information compression method of the embodiment of the present invention，Corresponding data flow diagram is obtained by cryptographic algorithm is carried out planning，Then extract common factor according to the repeat property of data flow diagram and determine common factor redundancy，Further according to restructural cipher processor ardware feature and common factor redundancy, data flow diagram is carried out subgraph division，Structure feature information and interconnection features information finally according to ready-portioned subgraph determine that configuration compress mode is that the configuration information of the reconfigurable arithmetic unit corresponding to subgraph and the configuration information of interconnection are compressed configuration by reconfigurable arithmetic unit configuration compress mode，The calculating feature of the method combining cipher algorithm carrys out option and installment Information Compression mode，And based on selected configuration information compress mode, configuration information is compressed，Remove the configuration information of redundancy，And then the execution efficiency of restructural cipher processor can be improved.
Fig. 6 is the schematic diagram of arithmetic element configuration compress mode according to an embodiment of the invention.
As shown in Figure 6, when mapping planning algorithm being on RCA, this mapping can be abstracted into DFG (in Fig. 6 left figure), after obtaining DFG, the mode that can be divided by subgraph, DFG is divided in figure subgraph 1 and subgraph 2, and wherein all RC in subgraph 1 are respectively provided with same arithmetic operation, and the interconnection situation of these RC is also just the same.Divide in conjunction with such DFG, the configuration information of interconnection corresponding with subgraph for the configuration information of RC corresponding for subgraph can be stored in configuration memorizer, the index storing this configuration information is only need be read when carrying out RC configuration, and use the RC of this configuration to number, different RC just can access the complete configuration in configuration memorizer by same index, and index the complete configuration quantity of information being far smaller than them plus the configuration information amount that the numbering of RC is required, further such that the overall configuration information amount read is greatly reduced.
It will be appreciated that, it is only for illustrative purposes that data flow diagram DFG is divided in Fig. 6 two subgraphs, the number dividing subgraph is not defined by this embodiment, in actual applications, according to restructural cipher processor ardware feature and common factor redundancy, data flow diagram can be divided into other quantity subgraphs, such as, data flow diagram can divide three subgraphs, or four subgraphs etc..
Fig. 7 goes the flow chart of diversification configuration information compression method of configuration compress mode according to an embodiment of the invention.
It should be noted that RCA on restructural cipher processor can divide by row, in the mapping process to cryptographic algorithm, by the division to DFG so that RC function between each row and row in some subgraphs, and interconnection architecture therebetween is just the same.At this moment the configuration information of several reconfigurable arithmetic units of they correspondences is also identical with the configuration information of interconnection, if at this time still adopting RC to configure compress mode, the number of times reading configuration memorizer can be increased, thus reducing allocative efficiency, therefore, the mode of row configuration compression can be adopted in this case, while decrement is constant, it is possible to have higher allocative efficiency.As shown in Figure 7:
S71, plans cryptographic algorithm and generates the data flow diagram that cryptographic algorithm is corresponding.
Being appreciated that when doing Algorithm mapping planning, generally requiring the scale characteristic of associative array, design data flow diagram corresponding to algorithm (DFG), data flow diagram can show mapping structure very intuitively.
S72, extracts common factor according to the repeat property of data flow diagram, and determines the common factor redundancy of common factor.
Specifically, first cryptographic algorithm planned and obtain corresponding data flow diagram, then for the repeat property of the data flow diagram of gained the part that multiplicity in data flow diagram is higher extracted and namely extract common factor, and determine the common factor redundancy of the common factor extracted.
S73, carries out subgraph division according to restructural cipher processor ardware feature and common factor redundancy to data flow diagram.
S74, the subgraph configuration information of one subgraph is stored in configuration memorizer, and preserve the corresponding relation of the numbering of subgraph and the call number of subgraph configuration information, wherein, subgraph configuration information includes the configuration information of the interconnection between the configuration information of reconfigurable arithmetic unit and each reconfigurable arithmetic unit.
The diversification configuration information compression method of the embodiment of the present invention, corresponding data flow diagram is obtained by cryptographic algorithm is carried out planning, then extract common factor according to the repeat property of data flow diagram and determine common factor redundancy, further according to restructural cipher processor ardware feature and common factor redundancy, data flow diagram is carried out subgraph division, structure feature information and interconnection features information finally according to ready-portioned subgraph determine that configuration compress mode is that the configuration information of the reconfigurable arithmetic unit corresponding to subgraph and the configuration information of interconnection are compressed configuration by row configuration compress mode, the calculating feature of the method combining cipher algorithm carrys out option and installment Information Compression mode, and based on selected configuration information compress mode, configuration information is compressed, remove the configuration information of redundancy, and then the execution efficiency of restructural cipher processor can be improved.
Fig. 8 is the schematic diagram gone according to an embodiment of the invention and configure compress mode.
As shown in Figure 8, to the DFG of an algorithm by after dividing and becoming two subgraphs shown in the left figure of Fig. 8, between continuous several rows RC, row is just the same with the 26S Proteasome Structure and Function of row, in conjunction with such DFG subgraph, it is possible to the configuration information of a line is compressed and is stored in configuration memorizer, the corresponding index with configuration memorizer of this row configuration only need to be read in when configuration, the same index of several rows RC, reaches the purpose of repetitive compression, substantially reduces configuration information total amount further.It is expert under the different situation of function used by interior several RC unit, compares the configuration of the RC in reconfigurable arithmetic unit compress mode and be compressed with higher allocative efficiency.
It will be appreciated that, it is only for illustrative purposes that data flow diagram DFG is divided in Fig. 8 two subgraphs, the number dividing subgraph is not defined by this embodiment, in actual applications, according to restructural cipher processor ardware feature and common factor redundancy, data flow diagram can be divided into other quantity subgraphs, such as, data flow diagram can divide three subgraphs, or four subgraphs etc..
Fig. 9 is multiple according to an embodiment of the invention reconfigurable arithmetic unit flow chart as the diversification configuration information compression method of overall configuration compress mode.
Much more relatively it should be noted that for some cyclic parts cryptographic algorithm, in order to ensure the efficiency of encryption pile line operation, cyclic part in cryptographic algorithm can be carried out expansion and be mapped on RCA, the configuration information that cyclic part is corresponding is often the same.Even sometimes acyclic part, after mapping is abstracted into DFG, still can, by DFG is carried out subgraph division, a part of RC be made as a whole, having duplicate reconfigurable arithmetic unit structure and interconnection architecture between different entirety, they have same configuration information.Such DFG divides can provide compression stroke well.
S91, plans cryptographic algorithm and generates the data flow diagram that cryptographic algorithm is corresponding.
Being appreciated that when doing Algorithm mapping planning, generally requiring the scale characteristic of associative array, design data flow diagram corresponding to algorithm (DFG), data flow diagram can show mapping structure very intuitively.
S92, extracts common factor according to the repeat property of data flow diagram, and determines the common factor redundancy of common factor.
Specifically, first cryptographic algorithm planned and obtain corresponding data flow diagram, then for the repeat property of the data flow diagram of gained the part that multiplicity in data flow diagram is higher extracted and namely extract common factor, and determine the common factor redundancy of the common factor extracted.
S93, carries out subgraph division according to restructural cipher processor ardware feature and common factor redundancy to data flow diagram.
S94, for each subgraph, the row configuration information of a line is compressed and is stored in configuration memorizer, and preserve the corresponding relation of line number and the call number of row configuration information, wherein, row configuration information includes the configuration information of the interconnection between the configuration information of reconfigurable arithmetic unit and each reconfigurable arithmetic unit.
nullThe diversification configuration information compression method of the embodiment of the present invention，Corresponding data flow diagram is obtained by cryptographic algorithm is carried out planning，Then extract common factor according to the repeat property of data flow diagram and determine common factor redundancy，Further according to restructural cipher processor ardware feature and common factor redundancy, data flow diagram is carried out subgraph division，Structure feature information and interconnection features information finally according to ready-portioned subgraph determine that configuration compress mode is that the configuration information of the reconfigurable arithmetic unit corresponding to subgraph and the configuration information of interconnection are compressed configuring by multiple reconfigurable arithmetic unit as overall configuration compress mode，The calculating feature of the method combining cipher algorithm carrys out option and installment Information Compression mode，And based on selected configuration information compress mode, configuration information is compressed，Remove the configuration information of redundancy，And then the execution efficiency of restructural cipher processor can be improved.
Figure 10 is multiple according to an embodiment of the invention reconfigurable arithmetic unit schematic diagram as overall configuration compress mode.
As shown in Figure 10, simplest situation is for loop unrolling, RPU_CRYPTO configures AES, DFG is divided into subgraph 1 and subgraph 2, performs the once-through operation after cyclic part launches respectively, and each letter in figure (A, B ... .) represent a kind of arithmetical operation, the structure of two subgraphs is just the same, being mapped on RCA, the 1st～3 row RC performs subgraph 1, and the 4th～6 row RC performs subgraph 2.They required configuration parameters are duplicate, in this case it is stored in configuration memorizer once circulating required configuration information (including arithmetic element configuration information and interconnection configuration information), therefore, the mode adopting index just can realize sharing this loop configuration information, has greatly reduced configuration information amount.
It will be appreciated that, it is only for illustrative purposes that data flow diagram DFG is divided in Figure 10 two subgraphs, the number dividing subgraph is not defined by this embodiment, in actual applications, according to restructural cipher processor ardware feature and common factor redundancy, data flow diagram can be divided into other quantity subgraphs, such as, data flow diagram can divide three subgraphs, or four subgraphs etc..
In order to realize above-described embodiment, the application also proposed a kind of diversification configuration information compressor.
Figure 11 is the structural representation of diversification configuration information compressor according to an embodiment of the invention.As shown in figure 11, this diversification configuration information compressor includes: generation module 110, first determines module 111, divide module 112, second determine module 113 and compression module 114, wherein:
Generation module 110 is for planning cryptographic algorithm and generating the data flow diagram that cryptographic algorithm is corresponding.
First determines that module 111 extracts common factor for the repeat property according to data flow diagram, and determines the common factor redundancy of common factor.
Divide module 112 for data flow diagram being carried out subgraph division according to restructural cipher processor ardware feature and common factor redundancy.
Second determines that module 113 determines configuration compress mode for the structure feature information according to the subgraph after dividing and interconnection features information.
Compression module 114 for being compressed configuration by configuring compress mode to the configuration information of the reconfigurable arithmetic unit corresponding to subgraph and the configuration information of interconnection.
In one embodiment of the invention, configuration compress mode includes: reconfigurable arithmetic unit configuration compress mode, row configuration compress mode and multiple reconfigurable arithmetic unit are as overall configuration compress mode.
In one embodiment of the invention, diversification configuration information compressor, for each subgraph after dividing, if the arithmetic operation of all reconfigurable arithmetic units in subgraph is identical, and interconnection architecture is identical, then second determines that module 113 is reconfigurable arithmetic unit configuration compress mode according to structure feature information and the determined configuration compress mode of interconnection features information of the subgraph after dividing, wherein, compression module 114 specifically for: for each subgraph, interconnection configuration information between configuration information and each reconfigurable arithmetic unit of corresponding reconfigurable arithmetic unit is stored in configuration memorizer, and preserve the call number of configuration information and the corresponding relation of the numbering of the reconfigurable arithmetic unit using configuration information.
In one embodiment of the invention, diversification configuration information compressor, diversification configuration information compression method, if the structure of each subgraph after dividing is all identical, then second determines that module 113 is row configuration compress mode according to structure feature information and the determined configuration compress mode of interconnection features information of the subgraph after dividing, wherein, compression module 114 specifically for: the subgraph configuration information of a subgraph is stored in configuration memorizer in, and preserve the corresponding relation of the numbering of subgraph and the call number of subgraph configuration information, wherein, subgraph configuration information includes the configuration information of the interconnection between the configuration information of reconfigurable arithmetic unit and each reconfigurable arithmetic unit.
In one embodiment of the invention, diversification configuration information compressor, for each subgraph after dividing, if the row in subgraph is identical with the arithmetic operation between row, and go identical with the interconnection architecture between row, then second determines that module 113 is that multiple reconfigurable arithmetic unit is as overall configuration compress mode according to structure feature information and the interconnection features information determined configuration compress mode of the subgraph after dividing, compression module 114 specifically for: for each subgraph, the row configuration information of a line is compressed and is stored in configuration memorizer, and preserve the corresponding relation of line number and the call number of row configuration information, wherein, row configuration information includes the interconnection configuration information between the configuration information of reconfigurable arithmetic unit and each reconfigurable arithmetic unit.
It should be noted that the aforementioned explanation to diversification configuration information compression method embodiment is also applied for the diversification configuration information compressor of this embodiment, repeat no more herein.
The diversification configuration information compressor of the embodiment of the present invention, by generation module, cryptographic algorithm is carried out planning and obtain corresponding data flow diagram, then first determines that module is extracted common factor according to the repeat property of data flow diagram and determines common factor redundancy, divide module, further according to restructural cipher processor ardware feature and common factor redundancy, data flow diagram is carried out subgraph division, the second last determines according to structure feature information and the interconnection features information of ready-portioned subgraph, module determines that configuration compress mode utilizes compression module that the configuration information of the reconfigurable arithmetic unit of subgraph and the configuration information of interconnection are compressed configuration, the method achieve the configuration information compress mode that can select the best, allocative efficiency is improved while reducing configuration information amount.
In describing the invention, it is to be understood that term " first ", " second " only for descriptive purposes, and it is not intended that instruction or hint relative importance or the implicit quantity indicating indicated technical characteristic.Thus, define " first ", the feature of " second " can express or implicitly include at least one this feature.In describing the invention, " multiple " are meant that at least two, for instance two, three etc., unless otherwise expressly limited specifically.
In the description of this specification, specific features, structure, material or feature that the description of reference term " embodiment ", " some embodiments ", " example ", " concrete example " or " some examples " etc. means in conjunction with this embodiment or example describe are contained at least one embodiment or the example of the present invention.In this manual, the schematic representation of above-mentioned term is necessarily directed to identical embodiment or example.And, the specific features of description, structure, material or feature can combine in one or more embodiments in office or example in an appropriate manner.Additionally, when not conflicting, the feature of the different embodiments described in this specification or example and different embodiment or example can be carried out combining and combining by those skilled in the art.
Describe in flow chart or in this any process described otherwise above or method and be construed as, represent and include the module of code of executable instruction of one or more step for realizing specific logical function or process, fragment or part, and the scope of the preferred embodiment of the present invention includes other realization, wherein can not press order that is shown or that discuss, including according to involved function by basic mode simultaneously or in the opposite order, performing function, this should be understood by embodiments of the invention person of ordinary skill in the field.
Should be appreciated that each several part of the present invention can realize with hardware, software, firmware or their combination.In the above-described embodiment, multiple steps or method can realize with the storage software or firmware in memory and by suitable instruction execution system execution.Such as, if realized with hardware, the same in another embodiment, can realize by any one in following technology well known in the art or their combination: there is the discrete logic of logic gates for data signal realizes logic function, there is the special IC of suitable combination logic gate circuit, programmable gate array (PGA), field programmable gate array (FPGA) etc..
Those skilled in the art are appreciated that realizing all or part of step that above-described embodiment method carries can be by the hardware that program carrys out instruction relevant and complete, described program can be stored in a kind of computer-readable recording medium, this program upon execution, including the step one or a combination set of of embodiment of the method.
Additionally, each functional unit in each embodiment of the present invention can be integrated in a processing module, it is also possible to be that unit is individually physically present, it is also possible to two or more unit are integrated in a module.Above-mentioned integrated module both can adopt the form of hardware to realize, it would however also be possible to employ the form of software function module realizes.If described integrated module is using the form realization of software function module and as independent production marketing or use, it is also possible to be stored in a computer read/write memory medium.
Storage medium mentioned above can be read only memory, disk or CD etc..Although above it has been shown and described that embodiments of the invention, it is understandable that, above-described embodiment is illustrative of, it is impossible to be interpreted as limitation of the present invention, and above-described embodiment can be changed, revises, replace and modification by those of ordinary skill in the art within the scope of the invention.
Claims (10)
1. a diversification configuration information compression method, it is characterised in that comprise the following steps:
Cryptographic algorithm is planned and generates the data flow diagram that described cryptographic algorithm is corresponding；
Repeat property according to described data flow diagram extracts common factor, and determines the common factor redundancy of described common factor；
According to restructural cipher processor ardware feature and described common factor redundancy, described data flow diagram is carried out subgraph division；And
Structure feature information and interconnection features information according to the subgraph after dividing determine configuration compress mode, and are compressed configuring to the configuration information of reconfigurable arithmetic unit corresponding to described subgraph and the configuration information of interconnection by described configuration compress mode.
2. diversification configuration information compression method as claimed in claim 1, it is characterised in that described configuration compress mode includes:
Reconfigurable arithmetic unit configuration compress mode, row configuration compress mode and multiple reconfigurable arithmetic unit are as overall configuration compress mode.
3. diversification configuration information compression method as claimed in claim 2, it is characterized in that, for each subgraph after dividing, if the arithmetic operation of all reconfigurable arithmetic units in subgraph is identical, and interconnection architecture is identical, it is then described reconfigurable arithmetic unit configuration compress mode according to the structure feature information of subgraph after dividing and interconnection features information determined configuration compress mode, wherein
The described configuration information of reconfigurable arithmetic unit corresponding to described subgraph and the configuration information of interconnection being compressed by described configuration compress mode is configured, including:
For each subgraph, the configuration information of the interconnection between configuration information and each reconfigurable arithmetic unit of corresponding reconfigurable arithmetic unit is stored in configuration memorizer, and preserves the call number of described configuration information and the corresponding relation of the numbering of the described reconfigurable arithmetic unit using described configuration information.
4. diversification configuration information compression method as claimed in claim 2, it is characterized in that, if the structure of each subgraph after dividing is all identical, be then described row configuration compress mode according to the structure feature information of the subgraph after dividing and interconnection features information determined configuration compress mode, wherein
The described configuration information of reconfigurable arithmetic unit corresponding to described subgraph and the configuration information of interconnection being compressed by described configuration compress mode is configured, including:
The subgraph configuration information of one subgraph is stored in configuration memorizer, and preserve the numbering of subgraph and the corresponding relation of the call number of described subgraph configuration information, wherein, described subgraph configuration information includes the configuration information of the interconnection between the configuration information of reconfigurable arithmetic unit and each reconfigurable arithmetic unit.
5. diversification configuration information compression method as claimed in claim 2, it is characterized in that, for each subgraph after dividing, if the row in subgraph is identical with the arithmetic operation between row, and go identical with the interconnection architecture between row, then according to the structure feature information of subgraph after dividing and interconnection features information determined configuration compress mode be the plurality of reconfigurable arithmetic unit as overall configuration compress mode, wherein
The described configuration information of reconfigurable arithmetic unit corresponding to described subgraph and the configuration information of interconnection being compressed by described configuration compress mode is configured, including:
For each subgraph, the row configuration information of a line is compressed and is stored in configuration memorizer, and preserve the corresponding relation of line number and the call number of described row configuration information, wherein, described row configuration information includes the configuration information of the interconnection between the configuration information of reconfigurable arithmetic unit and each reconfigurable arithmetic unit.
6. a diversification configuration information compressor, it is characterised in that including:
Generation module, for planning cryptographic algorithm and generating the data flow diagram that described cryptographic algorithm is corresponding；
First determines module, extracts common factor for the repeat property according to described data flow diagram, and determines the common factor redundancy of described common factor；
Divide module, for described data flow diagram being carried out subgraph division according to restructural cipher processor ardware feature and described common factor redundancy；
Second determines module, determines configuration compress mode for the structure feature information according to the subgraph after dividing and interconnection features information；
Compression module, for being compressed configuring to the configuration information of reconfigurable arithmetic unit corresponding to described subgraph and the configuration information of interconnection by described configuration compress mode.
7. diversification configuration information compressor as claimed in claim 6, it is characterised in that described configuration compress mode specifically includes:
Reconfigurable arithmetic unit configuration compress mode, row configuration compress mode and multiple reconfigurable arithmetic unit are as overall configuration compress mode.
8. diversification configuration information compressor as claimed in claim 7, it is characterized in that, for each subgraph after dividing, if the arithmetic operation of all reconfigurable arithmetic units in subgraph is identical, and interconnection architecture is identical, then described second determines that module is described reconfigurable arithmetic unit configuration compress mode according to structure feature information and the interconnection features information determined configuration compress mode of the subgraph after dividing, wherein
Described compression module, specifically for:
For each subgraph, the configuration information of the interconnection between configuration information and each reconfigurable arithmetic unit of corresponding reconfigurable arithmetic unit is stored in configuration memorizer, and preserves the call number of described configuration information and the corresponding relation of the numbering of the described reconfigurable arithmetic unit using described configuration information.
9. diversification configuration information compressor as claimed in claim 7, it is characterized in that, diversification configuration information compression method, it is characterized in that, if the structure of each subgraph after dividing is all identical, then described second determines that module is described row configuration compress mode according to structure feature information and the interconnection features information determined configuration compress mode of the subgraph after dividing, wherein
Described compression module, specifically for:
The subgraph configuration information of one subgraph is stored in configuration memorizer, and preserve the numbering of subgraph and the corresponding relation of the call number of described subgraph configuration information, wherein, described subgraph configuration information includes the configuration information of the interconnection between the configuration information of reconfigurable arithmetic unit and each reconfigurable arithmetic unit.
10. diversification configuration information compressor as claimed in claim 7, it is characterized in that, for each subgraph after dividing, if the row in subgraph is identical with the arithmetic operation between row, and go identical with the interconnection architecture between row, then described second determines that module is the plurality of reconfigurable arithmetic unit configuration compress mode as entirety according to structure feature information and the interconnection features information determined configuration compress mode of the subgraph after dividing, wherein
Described compression module, specifically for:
For each subgraph, the row configuration information of a line is compressed and is stored in configuration memorizer, and preserve the corresponding relation of line number and the call number of described row configuration information, wherein, described row configuration information includes the configuration information of the interconnection between the configuration information of reconfigurable arithmetic unit and each reconfigurable arithmetic unit.
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