CN105426314A - Process mapping method for FPGA memory - Google Patents
Process mapping method for FPGA memory Download PDFInfo
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Abstract
The present invention relates to a process mapping method for an FPGA memory. The method comprises: performing classification and packaging according to original information of a logic netlist of the memory to generate a port group set; constructing a memory macro according to the number of port groups and parameters of the port groups comprised in the port group set; segmenting a data space and an address space of the memory macro according to a scale of resources in a target process library to obtain a memory assembly, wherein the memory assembly comprises functional parameters, and the functional parameters are specifically the port group parameters of the port groups constructing the memory macro; performing bit extension and address extension on the memory assembly to generate a memory assembly extension group; according to each memory assembly comprised in the memory assembly extension group, performing exact matching on the type of the memory assembly; and performing mapping in a device process mapping library according to a connection relationship and the functional parameters of the memory assembly subjected to the exact matching to generate the FPGA memory.
Description
Technical field
The present invention relates to the integrated circuit (IC) design technical field in microelectronic, the particularly process mapping method of field programmable gate array (FieldProgrammableGateArray, FPGA) storer.
Background technology
FPGA a kind ofly has the logical device enriching hardware resource, powerful parallel processing capability and flexible reconfigurable ability.These features make FPGA obtain increasing widespread use in a lot of field such as data processing, communication, network.
Storer is the elementary cell of FPGA, and Technology Mapping (TechnologyMapping) is that FPGA relates in flow process, connects the important bridge of the comprehensive and rear end placement-and-routing of front end logic.At this one-phase, the circuit meshwork list had nothing to do with technique, under certain hardware constraint, is mapped to the dependency structure of technology library, and process mapping method directly has influence on the performance of FPGA.
Summary of the invention
The invention provides a kind of process mapping method of FPGA storer, a kind of Technology Mapping supporting the FPGA storer of many scales, many read-write modes and multiport can be realized.
Embodiments provide a kind of process mapping method of FPGA storer, comprising:
Raw information according to memory logic net table carries out a point class wrapper, generates port set set;
The quantity of the port set comprised according to described port set set and port set parameter, structure memory macro;
According to the resource extent in target process storehouse, cutting is carried out to the data space of described memory macro and address space, obtain memory assembly; Described memory assembly comprises functional parameter, and described functional parameter is specially: the port set parameter constructing the port set of described memory macro;
Described memory assembly is pressed Bits Expanding and address extension generation memory assembly expanded set;
According to each memory assembly that described memory assembly expanded set comprises, then carry out the exact matching of memory component types;
According to annexation and the described functional parameter of the described memory assembly after described exact matching, map at device technology mapping library, generate described FPGA storer.
Preferably, the quantity of the described port set comprised according to described port set set and port set parameter, structure memory macro comprises:
Whether the quantity determining described port set is 1 or 2;
If be 1, grand according to described port set parametric configuration one-port memory;
If be 2, according to the full dual-ported memory of described port set parametric configuration is grand or pseudo-dual port memories is grand; Wherein, when the port set parameter of two described port set is read-only, or during another read-write read-only, construct full dual-ported memory grand; When the port set parameter of a described port set is for only to write, when the port set parameter of port set described in another is read-only, structure pseudo-dual port memories is grand;
If the quantity of described port set is 3 or more, then according to the dual-port read-write mode pairing rules preset, port set in described port set set is matched, and construct according to the port set of successful matching that full dual-ported memory is grand or pseudo-dual port memories is grand, grand according to the port set structure one-port memory of non-successful matching.
Preferred further, the dual-port read-write mode pairing rules that described basis is preset, carries out pairing to the port set in described port set set and is specially:
Be read-only port set by described port set parameter be that the port set read and write is matched successively with port set parameter, until the port set that described port set parameter is read-write is all paired, or described port set parameter is that read-only port set is all paired;
When also to deposit the described port set parameter be not paired be read-only port set, be read-only port set by the described port set parameter be not paired be that the port set only write is matched successively with port set parameter, all be paired until described port set parameter is the port set only write, or described port set parameter is that read-only port set is all paired;
When also to there is the described port set parameter be not paired be read-only port set, be that read-only port set is matched between two by the described port set parameter be not paired.
Preferably, describedly according to the resource extent in target process storehouse, cutting is carried out to the data space of described memory macro and address space, obtains memory assembly and be specially:
Described memory macro scale is calculated according to the data depth of described memory macro and address width;
In target process storehouse, obtain and to be greater than and closest to the component type of resource extent of described memory macro scale as first cutting component type, or the component type obtaining the resource extent equal with described memory macro scale is as first cutting component type;
Memory macro according to the cutting of described first cutting component type, structure memory assembly.
Preferred further, when in described target process storehouse, when whole resource extent is all less than described memory macro scale, described method also comprises:
The component type that in acquisition target process storehouse, resource extent is maximum is as first cutting component type.
Preferred further, described exact matching comprises:
Calculating utilizes described first cutting component type to construct the first cost of described memory assembly;
Obtain in target process storehouse, be less than other component type of the resource extent of described first cutting component type;
Calculating successively utilizes other component type to construct the cost of described memory assembly, and wherein minimum cost is the second cost;
When described second cost is less than the first cost, using the optimum component type of component type corresponding for described second cost as the described memory assembly of structure;
Otherwise, using the optimum component type of described first cutting component type as the described memory assembly of structure.
The process mapping method of the FPGA storer that the embodiment of the present invention provides, by carrying out a point class wrapper to the raw information of memory logic net table, generates port set set; The quantity of the port set comprised according to described port set set and port set parameter, structure memory macro; According to the resource extent in target process storehouse, cutting is carried out to the data space of described memory macro and address space, obtain memory assembly; After exact matching is carried out to memory component types, again according to annexation and the described functional parameter of the described memory assembly after exact matching, map at device technology mapping library, generate described FPGA storer, thus achieve a kind of process mapping method supporting the FPGA storer of many scales, many read-write modes and multiport.
Accompanying drawing explanation
The process flow diagram of the process mapping method of the FPGA storer that Fig. 1 provides for the embodiment of the present invention;
The schematic diagram of the port set set pin that Fig. 2 provides for the embodiment of the present invention;
The method flow diagram of the structure memory macro that Fig. 3 provides for the embodiment of the present invention;
The cutting method process flow diagram of the memory assembly that Fig. 4 provides for the embodiment of the present invention;
The method flow diagram of the exact matching of the memory assembly that Fig. 5 provides for the embodiment of the present invention.
Embodiment
Below by drawings and Examples, technical scheme of the present invention is described in further detail.
The process flow diagram of the process mapping method of the FPGA storer that Fig. 1 provides for the embodiment of the present invention.As shown in Figure 1, described method comprises the steps:
Step 110, the raw information according to memory logic net table carries out a point class wrapper, generates port set set;
Concrete, when carrying out FPGA Technology Mapping, first need the raw information input of logic netlist.For the raw information of logic netlist of input, carry out a point class wrapper, generating with address pins is one group of relevant pins and optimum configurations set, the i.e. form of port set of major key.Described port set set refers to the set of multiple port set of access same storer.Port set set can as shown in Figure 2, and in figure, PORTGROUP0 is first port set in port set set, and PORTGROUPi is the i-th+1 port set in port set set.
Port set in port set set has identical template class, and they have identical pin framework.
Each port set has some port set parameters, in one example in which can shown in table 1 specific as follows.
| Port set parameter | Parameter attribute value |
| Synchronous mode | Output is deposited, and address is deposited |
| Control signal | Sheet is enable, writes enable, reads enable, resets enable |
| Read/write conflict pattern | First read, write logical, keep, bypass |
| Data-out port reset values | >＝0 |
Table 1
For the set of port set shown in Fig. 2, each port set comprises clock signal pin CLK, chip selection signal pin EN, write enable signal pin WE, reset signal pin RST, data input signal pin DIN (data width), address signal pin ADDR (the address degree of depth) and data output signal pin DOUT.
It should be noted that, in port set set, the parameter attribute value of each port set can be different.
Step 120, the quantity of the port set comprised according to described port set set and port set parameter, structure memory macro;
Concrete, memory macro take port mode as feature, according to the difference reading and writing enable and address pins, all of the port group in port set set divided, and the logical layer obtained that matches encapsulates.Port mode can specifically be categorized as: single port, pseudo-double port, full dual-port and a few kind of multiport.
The concrete grammar of structure memory macro can as shown in Figure 3, comprise the steps:
Step 301, determines whether the quantity of described port set is 1;
If be 1, perform step 302; Otherwise perform step 303;
Step 302, when port set quantity is 1, grand according to described port set parametric configuration one-port memory.
Step 303, determines whether the quantity of described port set is 2;
If be 2, perform step 304; Otherwise perform step 307;
Step 304, when port set quantity is 2, determines that whether the port set parameter of two described port set is for being a read-only or read-only read-write;
Step 305, if the port set parameter of two described port set is a read-only or read-only read-write, grand according to the full dual-ported memory of described port set parametric configuration;
Step 306, if the port set parameter of a described port set is for only to write, the port set parameter of port set described in another is read-only, grand according to described port set parametric configuration pseudo-dual port memories;
Step 307, when port set quantity is 3 or more, according to the dual-port read-write mode pairing rules preset, port set in described port set set is matched, and construct according to the port set of successful matching that full dual-ported memory is grand or pseudo-dual port memories is grand, grand according to the port set structure one-port memory of non-successful matching.
Concrete, if when having 3 port set in port set set at least, need first to classify to port set, whole port set in the set of traversal port set, according to the port set parameter of each port set, whole port set is divided according to parameter attribute that is read-write, read-only, that only write, is categorized as read-write port set subclass, read-only port set subclass and only write port group subclass.Then, the port set in all subclass is matched.
Certain matched rule is followed in pairing, as shown in table 2 below.
Table 2
Further, two port set of coupling need to be two port set accessing same storer.
In a concrete example, matching process can be specially:
Choose a port set in read-only port set subclass successively, first a port set in read-only port set subclass and the port set in read-write port set subclass are matched, if successful matching, two of successful matching port set are removed respectively from read-only port set subclass and read-write port set subclass, and, full dual-ported memory is constructed grand according to two port set of pairing, until the port set in described read-write port set subclass is all paired, or the port set in described read-only port set subclass is all paired.
After above-mentioned pairing process completes, if also deposit the port set be not paired in read-only port set subclass, the port set be not paired in read-only port set subclass is matched with the port set of only write port group subclass successively, if successful matching, two of successful matching port set are removed respectively from read-only port set subclass and a write port group subclass, further, grand according to two port set structure pseudo-dual port memories of pairing.Until the port set in described write port group subclass is all paired, or the port set in described read-only port set subclass is all paired.
After above-mentioned pairing process completes, if also deposit the port set be not paired in read-only port set subclass, be that read-only port set is matched between two by the described port set parameter be not paired.Further, full dual-ported memory is constructed according to two port set of pairing grand.Until there is no the port set that can match.
After above-mentioned pairing process completes, grand according to residue unpaired port set structure one-port memory.
Step 130, carries out cutting according to the resource extent in target process storehouse to the data space of described memory macro and address space, obtains memory assembly;
Concrete, memory assembly is that the data space of memory macro and address space are carried out the logical layer encapsulation in the matched target process storehouse that cutting obtains according to target process base resource scale.Described memory assembly comprises functional parameter, and described functional parameter is specially: the port set parameter constructing the port set of described memory macro.
Target process base resource can comprise multiple assembly, such as block storage, distributed memory etc., and each assembly can by sizes scale.Such as block storage can be 5K, 9K, 18K etc., and distributed memory can be 32 × 2S, 32 × 2D, 32 × 2T, 32 × 2Q etc.
Previous step is constructed to the memory macro obtained, there is a certain size grand scale, the size scale of the assembly of target process base resource can be utilized to set threshold value, determine the first cutting component type of the data space of described memory macro and address space being carried out to cutting, carry out cutting according to first cutting component type, and then carry out optimum assembly type matching.Specifically as shown in Figure 4, comprise the steps:
Step 401, calculates described memory macro scale according to the data depth of described memory macro and address width;
Step 402, determines whether to exist in target process storehouse the assembly that size scale is greater than memory macro scale;
Step 403, if existed, obtains size scale and equals, or is greater than and closest to the component type of described memory macro scale as first cutting component type;
Step 404, if there is no, then obtains the component type that in target process storehouse, size is largest as first cutting component type;
Step 405, memory macro according to the cutting of described first cutting component type, structure memory assembly.
Step 140, presses Bits Expanding by described memory assembly and address extension generates memory assembly expanded set;
Concrete, in aforesaid port set set, the address degree of depth and data width are defined, after determining memory assembly, need carry out address extension and Bits Expanding according to the address degree of depth and data width, make the address degree of depth of memory assembly expanded set and data width consistent with the memory macro that port set set constructs.
Such as, the address degree of depth of port set set is 2K, the address degree of depth of the memory assembly that front step is determined is 1K, data width is 18bit, then, in the degree of depth of address, need memory assembly to expand, be extended to two, by EN gating, when EN high effectively time gating one of them memory assembly access, when EN low effective time gating another memory assembly access.
Method according to above object lesson, according to the parameter of port set set, can expand memory assembly, is configured to the memory assembly expanded set corresponding with port set set.
Step 150, according to each memory assembly that described memory assembly expanded set comprises, then carries out the exact matching of memory component types;
Concrete, for each memory assembly that expanded set comprises, the exact matching of component type can be carried out again.Specific as followsly state step:
Step 501, calculates the first cost utilizing described first cutting component type structure memory assembly;
Step 502, obtains in target process storehouse, is less than other component type of the resource extent of described first cutting component type;
Step 503, calculate the cost utilizing described other component type structure memory assembly successively, wherein minimum cost is the second cost;
Above-mentioned steps 501 can perform after step 502 or 503, also can with step 502 or 503 executed in parallel.
Step 504, judges that whether described first cost is higher than the second cost;
Step 505, when the first cost is higher than the second cost, using the optimum component type of component type corresponding for described second cost as structure memory assembly;
Step 506, otherwise, using the optimum component type of first cutting component type as structure memory assembly.
The memory assembly that described optimum component type is namely finally determined.
Each memory assembly comprised for expanded set determines its optimum component type, thus each memory assembly finally determined in the group that is expanded.
Step 160, according to annexation and the described functional parameter of the memory assembly after exact matching in described memory assembly expanded set, maps at device technology mapping library, generates described FPGA storer.
Concrete, by the mapping of memory assembly to memory entities, its line can be followed different configuration relation rules and carry out.When according to memory assembly expanded set structure FPGA storer, in constructor, store the information of different component selection mode, according to the different mode selected, carry out corresponding annexation configuration.And according to functional parameter, map at device technology mapping library, construct required FPGA storer.
By the method that the embodiment of the present invention provides, the Technology Mapping of the FPGA storer of many scales, many read-write modes and multiport can be supported.
Professional should recognize further, in conjunction with unit and the algorithm steps of each example of embodiment disclosed herein description, can realize with electronic hardware, computer software or the combination of the two, in order to the interchangeability of hardware and software is clearly described, generally describe composition and the step of each example in the above description according to function.These functions perform with hardware or software mode actually, depend on application-specific and the design constraint of technical scheme.Professional and technical personnel can use distinct methods to realize described function to each specifically should being used for, but this realization should not thought and exceeds scope of the present invention.
The software module that the method described in conjunction with embodiment disclosed herein or the step of algorithm can use hardware, processor to perform, or the combination of the two is implemented.Software module can be placed in the storage medium of other form any known in random access memory (RAM), internal memory, ROM (read-only memory) (ROM), electrically programmable ROM, electrically erasable ROM, register, hard disk, moveable magnetic disc, CD-ROM or technical field.
Above-described embodiment; object of the present invention, technical scheme and beneficial effect are further described; be understood that; the foregoing is only the specific embodiment of the present invention; the protection domain be not intended to limit the present invention; within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (6)
1. a process mapping method for on-site programmable gate array FPGA storer, is characterized in that, described method comprises:
Raw information according to memory logic net table carries out a point class wrapper, generates port set set;
The quantity of the port set comprised according to described port set set and port set parameter, structure memory macro;
According to the resource extent in target process storehouse, cutting is carried out to the data space of described memory macro and address space, obtain memory assembly; Described memory assembly comprises functional parameter, and described functional parameter is specially: the port set parameter constructing the port set of described memory macro;
Described memory assembly is pressed Bits Expanding and address extension generation memory assembly expanded set;
According to each memory assembly that described memory assembly expanded set comprises, then carry out the exact matching of memory component types;
According to annexation and the described functional parameter of the described memory assembly after described exact matching, map at device technology mapping library, generate described FPGA storer.
2. method according to claim 1, is characterized in that, the quantity of the described port set comprised according to described port set set and port set parameter, and structure memory macro comprises:
Whether the quantity determining described port set is 1 or 2;
If be 1, grand according to described port set parametric configuration one-port memory;
If be 2, according to the full dual-ported memory of described port set parametric configuration is grand or pseudo-dual port memories is grand; Wherein, when the port set parameter of two described port set is read-only, or during another read-write read-only, construct full dual-ported memory grand; When the port set parameter of a described port set is for only to write, when the port set parameter of port set described in another is read-only, structure pseudo-dual port memories is grand;
If the quantity of described port set is 3 or more, then according to the dual-port read-write mode pairing rules preset, port set in described port set set is matched, and construct according to the port set of successful matching that full dual-ported memory is grand or pseudo-dual port memories is grand, grand according to the port set structure one-port memory of non-successful matching.
3. method according to claim 2, is characterized in that, the dual-port read-write mode pairing rules that described basis is preset, and carries out pairing be specially the port set in described port set set:
Be read-only port set by described port set parameter be that the port set read and write is matched successively with port set parameter, until the port set that described port set parameter is read-write is all paired, or described port set parameter is that read-only port set is all paired;
When also to deposit the described port set parameter be not paired be read-only port set, be read-only port set by the described port set parameter be not paired be that the port set only write is matched successively with port set parameter, all be paired until described port set parameter is the port set only write, or described port set parameter is that read-only port set is all paired;
When also to there is the described port set parameter be not paired be read-only port set, be that read-only port set is matched between two by the described port set parameter be not paired.
4. method according to claim 1, is characterized in that, describedly carries out cutting according to the resource extent in target process storehouse to the data space of described memory macro and address space, obtains memory assembly and is specially:
Described memory macro scale is calculated according to the data depth of described memory macro and address width;
In target process storehouse, obtain and to be greater than and closest to the component type of resource extent of described memory macro scale as first cutting component type, or the component type obtaining the resource extent equal with described memory macro scale is as first cutting component type;
Memory macro according to the cutting of described first cutting component type, structure memory assembly.
5. method according to claim 4, is characterized in that, when in described target process storehouse, when whole resource extent is all less than described memory macro scale, described method also comprises:
The component type that in acquisition target process storehouse, resource extent is maximum is as first cutting component type.
6. the method according to claim 4 or 5, is characterized in that, described exact matching comprises:
Calculating utilizes described first cutting component type to construct the first cost of described memory assembly;
Obtain in target process storehouse, be less than other component type of the resource extent of described first cutting component type;
Calculating successively utilizes other component type to construct the cost of described memory assembly, and wherein minimum cost is the second cost;
When described second cost is less than the first cost, using the optimum component type of component type corresponding for described second cost as the described memory assembly of structure;
Otherwise, using the optimum component type of described first cutting component type as the described memory assembly of structure.
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| CN106407535A (en) * | 2016-09-06 | 2017-02-15 | 北京深维科技有限公司 | Field-programmable gate array chip-based process mapping method |
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