CN112948324A - Memory mapping processing method and device and FPGA chip - Google Patents
Memory mapping processing method and device and FPGA chip Download PDFInfo
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Abstract
The invention provides a memory mapping processing method and device and an FPGA chip. In the memory mapping processing method, a memory set is obtained, wherein a memory included in the memory set is mapped by a preset circuit; detecting whether the storage space of the memory set exceeds the storage space of the chip memory; in the case that the storage space of the memory set is detected to exceed the storage space of the chip memory, the memory is split from the memory set until the storage space of the split remaining memory set does not exceed the storage space of the chip memory. When the resources of the memory set in the design exceed the designated resources corresponding to the memory set in the chip, the exceeded part of the memory is disassembled, so that the integrated user design resources do not exceed the designated resources in the chip, the user design can normally pass through the chip in the subsequent steps, and the disassembled memory can be represented by using other resources.
Description
Technical Field
The invention relates to the field of FPGA comprehensive development, in particular to a memory mapping processing method and device and an FPGA chip.
Background
The FPGA is designed to be closer to a framework of a hardware bottom layer as a universal programmable logic device, has a large number of memory resources, DSP resources and the like, has the characteristics of excellence in data parallel computation, flexibility and low delay, and has the characteristics of low power consumption, programmability, flexibility in design and the like, so that the FPGA is widely used in a plurality of application fields.
For example, patent application No. 201911007758.7, "a system on a chip and a memory" discloses a memory implemented based on FPGA logic, which is used to improve resource sharing and multiplexing of a system on the upper side, and has good expandability and usability.
With the development of the FPGA industry, the scale of user designs is getting larger and larger, and due to the diversity of user designs, the integration process is also becoming especially important, and different user designs need to be identified and expressed using the most reasonable resources. When a user defines and describes a memory in a hardware design circuit, it is reasonable for the synthesis tool to map the memory into the memory, but when the memory in the hardware design circuit is more defined and exceeds the memory resource in a specified chip, if all the defined memories are synthesized out of the memory, the subsequent steps of laying out and routing and the like are failed.
Disclosure of Invention
The invention mainly aims to provide a memory mapping processing method, a memory mapping processing device and an FPGA chip, and aims to solve the problem that in the prior art, the synthesized memory resources exceed the resources of a specified chip, so that the subsequent steps fail.
In order to achieve the above object, according to an aspect of the present invention, there is provided a memory mapping processing method, acquiring a memory set, wherein memories included in the memory set are mapped by a predetermined circuit; detecting whether the storage space of the memory set exceeds the storage space of the chip memory; in the case that the storage space of the memory set is detected to exceed the storage space of the chip memory, the memory is split from the memory set until the storage space of the split remaining memory set does not exceed the storage space of the chip memory.
The memory set comprises a plurality of memory sets, each of the memory sets has a corresponding chip memory, wherein a first memory set and a second memory set are any two memory sets in the memory sets, the first memory set corresponds to a first chip memory, the second memory set corresponds to a second chip memory, and the storage space of the first chip memory is larger than that of the second chip memory; and detecting whether the storage space of the second storage set exceeds the storage space of the second chip storage, and processing the first storage according to the detection result.
Further, detecting whether the storage space of the second memory set exceeds the storage space of the second chip memory, and processing the first memory according to the detection result, including: for each split first memory, in the case of detecting that the storage space of the second memory set does not exceed the storage space of the second chip memory, splitting the split first memory into the second memory set.
Further, detecting whether the storage space of the second memory set exceeds the storage space of the second chip memory, and processing the first memory according to the detection result, including: and for each split first memory, taking the split first memory as a register under the condition that the storage space of the second chip memory is detected to be exceeded.
Further, the method further comprises: and dividing a plurality of memories obtained by mapping a plurality of preset circuits according to the storage space threshold value to obtain a plurality of memory sets.
Further, splitting the memory from the memory set until the storage space of the split remaining memory set does not exceed the storage space of the chip memory, comprising: and splitting the memories included in the memory set according to the sequence of the memory spaces from small to large until the memory space of the rest split memory set does not exceed the memory space of the chip memory.
Further, the method further comprises: and taking the split memory as a register.
According to another aspect of the present invention, there is provided a memory mapping processing apparatus, including an obtaining module, configured to obtain a memory set, where memories included in the memory set are mapped by a predetermined circuit; the detection module is used for detecting whether the storage space of the memory set exceeds the storage space of the chip memory; and the splitting module is used for splitting the memory from the memory set under the condition that the storage space of the memory set is detected to exceed the storage space of the chip memory until the storage space of the rest split memory set does not exceed the storage space of the chip memory.
According to another aspect of the present invention, there is also provided an FPGA chip, including: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to execute the instructions to implement the memory mapping processing method as described above.
According to another aspect of the present invention, there is also provided a computer-readable storage medium, wherein instructions of the computer-readable storage medium, when executed by a processor of an electronic device, enable the electronic device to perform the memory mapping processing method as described above.
According to another aspect of the present invention, there is also provided a computer program product comprising a computer program which, when executed by a processor, implements the memory mapping processing method described above.
The technical scheme of the invention is applied to provide a memory mapping processing method, which comprises the steps of firstly obtaining a memory set, wherein a memory included in the memory set is obtained by mapping a preset circuit, then detecting whether the storage space of the memory set exceeds the storage space of a chip memory, and under the condition that the storage space of the memory set exceeds the storage space of the chip memory, splitting the memory from the memory set until the storage space of the split remaining memory set does not exceed the storage space of the chip memory. When the resources of the memory set in the design exceed the designated resources corresponding to the memory set in the chip, the exceeded part of the memory is disassembled, so that the integrated user design resources do not exceed the designated resources in the chip, the user design can normally pass through the chip in the subsequent steps, and the disassembled memory can be represented by using other resources.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
fig. 1 is a block diagram illustrating a hardware configuration of a computer terminal for implementing a form processing method according to an exemplary embodiment;
FIG. 2 is a flow diagram illustrating a method of memory mapping processing in accordance with an exemplary embodiment;
fig. 3 is an apparatus block diagram of a table processing apparatus according to embodiment 2 of the present invention;
fig. 4 is an apparatus block diagram of a terminal according to an embodiment of the present invention.
Detailed Description
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict. The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged under appropriate circumstances in order to facilitate the description of the embodiments of the invention herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Example 1
In accordance with an embodiment of the present invention, there is provided a memory mapping process method embodiment, it is noted that the steps illustrated in the flowchart of the figure may be performed in a computer system such as a set of computer executable instructions, and that while a logical order is illustrated in the flowchart, in some cases the steps illustrated or described may be performed in an order different than here.
The method provided by the embodiment 1 of the present application can be executed in a mobile terminal, a computer terminal or a similar computing device. Fig. 1 shows a hardware configuration block diagram of a computer terminal (or mobile device) for implementing a memory mapping processing method. As shown in fig. 1, the computer terminal 10 (or mobile device) may include one or more (shown as 102a, 102b, … …, 102 n) processors 102 (the processors 102 may include, but are not limited to, a processing device such as a microprocessor MCU or a programmable logic device FPGA, etc.), memories 104 for storing data, and a transmission device for communication functions. Besides, the method can also comprise the following steps: a display, an input/output interface (I/O interface), a Universal Serial BUS (USB) port (which may be included as one of the ports of the BUS), a network interface, a power source, and/or a camera. It will be understood by those skilled in the art that the structure shown in fig. 1 is only an illustration and is not intended to limit the structure of the electronic device. For example, the computer terminal 10 may also include more or fewer components than shown in FIG. 1, or have a different configuration than shown in FIG. 1.
It should be noted that the one or more processors 102 and/or other data processing circuitry described above may be referred to generally herein as "data processing circuitry". The data processing circuitry may be embodied in whole or in part in software, hardware, firmware, or any combination thereof. Further, the data processing circuit may be a single stand-alone processing module, or incorporated in whole or in part into any of the other elements in the computer terminal 10 (or mobile device). As referred to in the embodiments of the application, the data processing circuit acts as a processor control (e.g. selection of a variable resistance termination path connected to the interface).
The memory 104 may be used to store software programs and modules of application software, such as program instructions/data storage devices corresponding to the memory mapping processing method in the embodiment of the present invention, and the processor 102 executes various functional applications and data processing by running the software programs and modules stored in the memory 104, that is, implements the memory mapping processing method of the application program. The memory 104 may include high speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include memory located remotely from the processor 102, which may be connected to the computer terminal 10 via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The transmission device is used for receiving or transmitting data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider of the computer terminal 10. In one example, the transmission device includes a Network adapter (NIC) that can be connected to other Network devices through a base station to communicate with the internet. In one example, the transmission device may be a Radio Frequency (RF) module, which is used for communicating with the internet in a wireless manner.
The display may be, for example, a touch screen type Liquid Crystal Display (LCD) that may enable a user to interact with a user interface of the computer terminal 10 (or mobile device).
Under the above operating environment, the present application provides a memory mapping processing method as shown in fig. 2. Fig. 2 is a flowchart of a memory mapping processing method according to embodiment 1 of the present invention, and as shown in fig. 2, the method includes the steps of:
step S202, a memory set is obtained, wherein the memory included in the memory set is obtained by mapping a preset circuit;
step S204, detecting whether the storage space of the memory set exceeds the storage space of the chip memory;
in step S206, when it is detected that the storage space of the memory set exceeds the storage space of the chip memory, the memory is split from the memory set until the storage space of the split remaining memory set does not exceed the storage space of the chip memory.
In the embodiment of the invention, when the resources of the memory set in the design exceed the specified resources corresponding to the memory set in the chip, the exceeded part of the memory is removed, so that the integrated user design resources do not exceed the specified resources in the chip, the user design can normally pass through the chip in the subsequent steps, and the separated memory can be represented by using other resources.
Memory collection it is understood that a user writes a circuit design that may be represented as a memory, which may be numerous and may constitute one or more collections.
A chip memory may be understood as a memory model on a chip that may represent the functionality of the memory.
The memory set resource may be understood as a sum of storage spaces of all memories in one memory set, each memory in the memory set is mapped in a chip through a synthesis tool, if one memory set completes mapping in the chip and causes failure of other subsequent steps, it is determined that the memory set resource exceeds a specified resource corresponding to the memory set in the chip, a memory model having the specified resource in the chip is defined as a chip memory corresponding to the memory set, and the specified resource may be understood as a storage space of a corresponding memory model in the chip.
In the memory mapping processing method, a set of all circuit designs representing a memory in a user design is obtained, and each circuit in the set can be mapped into a memory model; mapping all circuits in the set into a memory model at first; calculating the size of the storage space represented by all the mapped memory models, if the storage space of the memory models mapped by all the circuits in the same set exceeds the storage space of the corresponding memory model in the chip, arranging the memory models from small to large according to the respective represented storage spaces, and then sequentially splitting the memory models into common circuits until the storage space of the remaining memory models is not larger than the storage space of the chip.
As an optional embodiment, the memory set includes a plurality of memory sets, each of the plurality of memory sets has a corresponding chip memory, where the first memory set and the second memory set are any two memory sets in the plurality of memory sets, the first memory set corresponds to the first chip memory, the second memory set corresponds to the second chip memory, and a storage space of the first chip memory is greater than a storage space of the second chip memory, where, when it is detected that the storage space of the first memory set exceeds the storage space of the first chip memory, the first memory is split from the first memory set until a storage space of the split first memory set does not exceed the storage space of the first chip memory; and detecting whether the storage space of the second memory exceeds the storage space of the second chip memory, and processing the first memory according to the detection result.
In the above optional embodiment, by splitting the first memories in the first memory set one by one and simultaneously determining whether the storage space of the first memory set exceeds the storage space of the first chip memory, not only the storage space of the split memory set can be made smaller than the storage space of the corresponding chip memory, thereby avoiding that the subsequent steps after mapping cannot normally pass, but also the split memory set can have a storage space closer to the corresponding chip memory, thereby avoiding that the storage space of the mapped memory set in the chip is insufficient due to the excessive split number of the memories in the memory set.
In the above optional embodiment, the memory may be divided into a first memory set to an nth memory set, first determining whether the storage space of the first memory set exceeds the storage space of the first chip memory, in case that the storage space of the first memory set exceeds the storage space of the first chip memory, splitting the first memory from the first memory set into any one of a second memory set to the nth memory set or into a register, then determining whether the storage space of the second memory set exceeds the storage space of the second chip memory, in case that the storage space of the second memory set exceeds the storage space of the second chip memory, splitting the second memory from the second memory set into any one of a third memory set to the nth memory set or into a register, and repeating the steps until judging whether the storage space of the Nth memory set exceeds the storage space of the Nth chip memory or not, and splitting the Nth memory into the register from the Nth memory set under the condition that the storage space of the Nth memory set is detected to exceed the storage space of the Nth chip memory.
In the foregoing optional embodiment, detecting whether the storage space of the split first memory exceeds the storage space of the second chip memory, and processing the first memory according to the detection result may include: for each split first memory, in the case of detecting that the storage space of the second memory set does not exceed the storage space of the second chip memory, splitting the split first memory into the second memory set. And when the second memory is split from the second memory set into any one of a third memory set to an Nth memory set or into a register from the second memory set, judging the new second memory set.
In the above optional embodiment, detecting whether the storage space of the split first memory exceeds the storage space of the second chip memory, and processing the first memory according to the detection result, may further include: and for each split first memory, taking the split first memory as a register under the condition that the storage space of the second chip memory is detected to be exceeded.
Since splitting the first memory in the first memory set into the second memory set in the case that the storage space of the second memory set exceeds the storage space of the second chip memory may result in an increase in the number of second memories to be split in a later step, thereby resulting in a decrease in processing efficiency, by detecting whether the storage space of the original second memory set exceeds the storage space of the second chip memory before splitting the first memory in the first memory set into the second memory set, splitting the first memory in the first memory set into the second memory set in the case that it is detected that the storage space of the new second memory set does not exceed the storage space of the second chip memory, and splitting the excess first memory into other memory sets or registers if the storage space of the second chip memory is exceeded, thereby enabling to secure the processing efficiency.
In the above optional embodiment, the plurality of memories mapped by the plurality of predetermined circuits may be divided according to the storage space threshold, so as to obtain a plurality of memory sets. By dividing the memory space threshold, the plurality of memory sets can be sequentially detected in the descending order of the memory space.
As an alternative embodiment, splitting the memory from the memory set until the storage space of the split remaining memory set does not exceed the storage space of the chip memory, includes: and splitting the memories included in the memory set according to the sequence of the memory spaces from small to large until the memory space of the rest split memory set does not exceed the memory space of the chip memory.
In the optional embodiment, the memory with the larger memory space is ensured to be used for mapping by splitting the memory spaces from small to large, and the memory with the smaller memory space is split into other forms, so that the memory space of the finally mapped memory does not exceed the corresponding chip memory, the memory resources of the chip are reasonably used, and the utilization rate of the memory resources is improved.
In the above-mentioned embodiment and optional embodiments, the memories in the same memory set may be arranged in the same array according to the ascending order of the storage space, and the method for calculating the size of the storage space of each memory is as follows:
the address width of the memory is denoted as m, the data width of the memory is denoted as n, and the size of the memory space is 2m*n。
Based on the above embodiments and alternative embodiments, an alternative implementation is provided.
In this alternative embodiment, the memory designed by the user is divided into the set of memories 1 and the set of memories 2 according to the memory space threshold, and at this time, the memory mapping processing method includes:
acquiring all memories 1 in design, storing the memories 1 in an array, and sequencing each array according to the size of a storage space of the memory 1;
checking whether the sum of the storage space of the memory 1 exceeds the storage space of the corresponding chip memory, splitting the redundant memory 1 when the sum of the storage space of the memory 1 exceeds the corresponding chip memory, and splitting the redundant memory 1 according to the sequence of the storage spaces from small to large in the splitting process until the sum of the storage space of the memory 1 does not exceed the corresponding chip memory any more. When splitting, firstly checking whether the sum of the storage spaces of the memories 2 exceeds the storage space of the corresponding chip memory, when the storage space of the memory 2 exceeds, splitting the redundant memory 1 into the memories 2, and when the sum of the storage spaces of the memories 2 also exceeds the storage space of the corresponding chip memory, splitting the memory 1 into registers by using a mode of splitting and checking;
acquiring all memories 2 in the design, storing the memories 2 in an array, sequencing each array according to the size of the storage space of the memory 2, and arranging the calculated memory 2 in the same size as the memory 1 according to the ascending order of the sizes of the storage spaces of the memories;
checking whether the sum of the storage space of the memory 2 exceeds the storage space of the corresponding chip memory, splitting the redundant memory 2 when the sum of the storage space of the memory 2 exceeds the corresponding chip memory, and directly splitting the redundant memory into registers according to the sequence of the storage spaces from small to large in the splitting process until the sum of the storage space of the memory 2 does not exceed the corresponding chip memory any more.
Example 2
According to an embodiment of the present invention, there is also provided an apparatus for implementing the above memory mapping processing method, and fig. 3 is a block diagram of a memory mapping processing apparatus according to embodiment 2 of the present invention, the apparatus including: an acquisition module 302, a detection module 304, and a splitting module 306, which are described in detail below:
an obtaining module 302, configured to obtain a memory set, where memories included in the memory set are mapped by a predetermined circuit;
a detection module 304, configured to detect whether a storage space of the memory set exceeds a storage space of the chip memory;
the splitting module 306 is configured to, in a case that it is detected that the storage space of the memory set exceeds the storage space of the chip memory, split the memory from the memory set until the storage space of the split remaining memory set does not exceed the storage space of the chip memory.
It should be noted here that the acquiring module 302, the detecting module 304 and the splitting module 306 correspond to steps S202 to S206 in embodiment 1, and the modules are the same as the corresponding steps in the implementation example and application scenarios, but are not limited to the disclosure in embodiment 1.
Example 3
The embodiment of the invention can provide an FPGA chip which can be any one computer terminal device in a computer terminal group.
Optionally, in this embodiment, the FPGA chip may be located in at least one network device of a plurality of network devices of a computer network.
Optionally, fig. 4 is a block diagram illustrating a structure of an FPGA chip according to an exemplary embodiment. As shown in fig. 4, the FPGA chip may include: one or more processors 41 (only one shown), a memory 42 for storing processor-executable instructions; wherein the processor is configured to execute the instructions to implement any of the memory mapped processing methods described above.
The memory may be used to store software programs and modules, such as program instructions/modules corresponding to the memory mapping processing method and apparatus in the embodiments of the present invention, and the processor executes various functional applications and data processing by running the software programs and modules stored in the memory, that is, implements the memory mapping processing method. The memory may include high speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory may further include memory located remotely from the processor, and these remote memories may be connected to the computer terminal through a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The processor can call the information and application program stored in the memory through the transmission device to execute the following steps: acquiring a memory set, wherein memories included in the memory set are mapped by a preset circuit; detecting whether the storage space of the memory set exceeds the storage space of the chip memory; in the case that the storage space of the memory set is detected to exceed the storage space of the chip memory, the memory is split from the memory set until the storage space of the split remaining memory set does not exceed the storage space of the chip memory.
Optionally, the memory sets obtained in the memory mapping processing method and apparatus include a plurality of memory sets, each of the plurality of memory sets has a corresponding chip memory, where the first memory set and the second memory set are any two memory sets in the plurality of memory sets, the first memory set corresponds to the first chip memory, the second memory set corresponds to the second chip memory, and a storage space of the first chip memory is greater than a storage space of the second chip memory, and the processor may further execute the program code of the following step: under the condition that the storage space of the first memory set is detected to exceed the storage space of the first chip memory, splitting the first memory from the first memory set until the storage space of the rest first memory set is not more than the storage space of the first chip memory; and detecting whether the storage space of the second storage set exceeds the storage space of the second chip storage, and processing the first storage according to the detection result.
Optionally, the processor may further execute the program code of the following steps: detecting whether the storage space of the second storage set exceeds the storage space of the second chip storage, and processing the first storage according to the detection result, wherein the method comprises the following steps: for each split first memory, in the case of detecting that the storage space of the second memory set does not exceed the storage space of the second chip memory, splitting the split first memory into the second memory set.
Optionally, the processor may further execute the program code of the following steps: detecting whether the storage space of the second storage set exceeds the storage space of the second chip storage, and processing the first storage according to the detection result, wherein the method comprises the following steps: and for each split first memory, taking the split first memory as a register under the condition that the storage space of the second chip memory is detected to be exceeded.
Optionally, the processor may further execute the program code of the following steps: and dividing a plurality of memories obtained by mapping a plurality of preset circuits according to the storage space threshold value to obtain a plurality of memory sets.
Optionally, the processor may further execute the program code of the following steps: and splitting the memories included in the memory set according to the sequence of the memory spaces from small to large until the memory space of the rest split memory set does not exceed the memory space of the chip memory.
Optionally, the processor may further execute the program code of the following steps: and taking the split memory as a register.
Those of ordinary skill in the art will appreciate that the configuration shown in FIG. 4 is merely illustrative. Fig. 4 is not intended to limit the structure of the FPGA chip. For example, it may also include more or fewer components (e.g., network interfaces, display devices, etc.) than shown in FIG. 4, or have a different configuration than shown in FIG. 4.
Those skilled in the art will appreciate that all or part of the steps in the methods of the above embodiments may be implemented by a program instructing hardware associated with the terminal device, where the program may be stored in a computer-readable storage medium, and the storage medium may include: flash disks, Read-Only memories (ROMs), Random Access Memories (RAMs), magnetic or optical disks, and the like.
Example 4
In an exemplary embodiment, there is also provided a computer-readable storage medium including instructions that, when executed by a processor of a terminal, enable the terminal to perform the memory mapping processing method of any one of the above. Alternatively, the computer readable storage medium may be a non-transitory computer readable storage medium, for example, the non-transitory computer readable storage medium may be a ROM, a Random Access Memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, and the like.
Alternatively, in this embodiment, the computer-readable storage medium may be used to store the program code executed by the memory mapping processing method provided in embodiment 1.
Optionally, in this embodiment, the computer-readable storage medium may be located in any one of a group of computer terminals in a computer network, or in any one of a group of mobile terminals.
Optionally, in this embodiment, the computer readable storage medium is configured to store program code for performing the following steps: acquiring a memory set, wherein memories included in the memory set are mapped by a preset circuit; detecting whether the storage space of the memory set exceeds the storage space of the chip memory; in the case that the storage space of the memory set is detected to exceed the storage space of the chip memory, the memory is split from the memory set until the storage space of the split remaining memory set does not exceed the storage space of the chip memory.
Optionally, in this embodiment, the memory sets obtained in the memory mapping processing method and apparatus include a plurality of memory sets, each of the plurality of memory sets has a corresponding chip memory, where the first memory set and the second memory set are any two memory sets in the plurality of memory sets, the first memory set corresponds to the first chip memory, the second memory set corresponds to the second chip memory, and a storage space of the first chip memory is greater than a storage space of the second chip memory, and the computer-readable storage medium is configured to store program codes for performing the following steps: under the condition that the storage space of the first memory set is detected to exceed the storage space of the first chip memory, splitting the first memory from the first memory set until the storage space of the rest first memory set is not more than the storage space of the first chip memory; and detecting whether the storage space of the second storage set exceeds the storage space of the second chip storage, and processing the first storage according to the detection result.
Optionally, in this embodiment, the computer readable storage medium is configured to store program code for performing the following steps: detecting whether the storage space of the second storage set exceeds the storage space of the second chip storage, and processing the first storage according to the detection result, wherein the method comprises the following steps: for each split first memory, in the case of detecting that the storage space of the second memory set does not exceed the storage space of the second chip memory, splitting the split first memory into the second memory set.
Optionally, in this embodiment, the computer readable storage medium is configured to store program code for performing the following steps: detecting whether the storage space of the second storage set exceeds the storage space of the second chip storage, and processing the first storage according to the detection result, wherein the method comprises the following steps: and for each split first memory, taking the split first memory as a register under the condition that the storage space of the second chip memory is detected to be exceeded.
Optionally, in this embodiment, the computer readable storage medium is configured to store program code for performing the following steps: and dividing a plurality of memories obtained by mapping a plurality of preset circuits according to the storage space threshold value to obtain a plurality of memory sets.
Optionally, in this embodiment, the computer readable storage medium is configured to store program code for performing the following steps: splitting the memory from the memory set until the storage space of the split remaining memory set does not exceed the storage space of the chip memory, comprising: and splitting the memories included in the memory set according to the sequence of the memory spaces from small to large until the memory space of the rest split memory set does not exceed the memory space of the chip memory.
Optionally, in this embodiment, the computer readable storage medium is configured to store program code for performing the following steps: and taking the split memory as a register.
In an exemplary embodiment, there is also provided a computer program product, which, when the computer program in the computer program product is executed by a processor of an FPGA chip, enables the FPGA chip to perform the memory mapping processing method of any one of the above.
The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.
In the above embodiments of the present invention, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
In the embodiments provided in the present application, it should be understood that the disclosed technology can be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, a division of a unit is merely a division of a logic function, and an actual implementation may have another division, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, units or modules, and may be in an electrical or other form.
Units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that it is obvious to those skilled in the art that various modifications and improvements can be made without departing from the principle of the present invention, and these modifications and improvements should also be considered as the protection scope of the present invention.
Claims (11)
1. A memory mapping processing method is characterized in that,
acquiring a memory set, wherein memories included in the memory set are mapped by a preset circuit;
detecting whether the storage space of the memory set exceeds the storage space of a chip memory;
in the case that the storage space of the memory set is detected to exceed the storage space of the chip memory, splitting the memory from the memory set until the storage space of the rest of the split memory set does not exceed the storage space of the chip memory.
2. The method according to claim 1, wherein the memory set comprises a plurality of memory sets, each of the plurality of memory sets has a corresponding chip memory, wherein the first memory set and the second memory set are any two memory sets of the plurality of memory sets, the first memory set corresponds to a first chip memory, the second memory set corresponds to a second chip memory, and a storage space of the first chip memory is larger than a storage space of the second chip memory, wherein,
in the case that the storage space of the first memory set is detected to exceed the storage space of the first chip memory, splitting the first memory from the first memory set until the storage space of the remaining first memory set is not more than the storage space of the first chip memory;
and detecting whether the storage space of the second storage set exceeds the storage space of the second chip storage, and processing the first storage according to the detection result.
3. The method of claim 2, wherein detecting whether the storage space of the second memory set exceeds the storage space of the second chip memory, and processing the first memory according to the detection result comprises:
for each split one of the first memories, splitting the split first memory into the second memory set in case it is detected that the storage space of the second memory set does not exceed the storage space of the second chip memory.
4. The method of claim 2, wherein detecting whether the storage space of the second memory set exceeds the storage space of the second chip memory, and processing the first memory according to the detection result comprises:
and for each split first memory, taking the split first memory as a register under the condition that the storage space of the second chip memory is detected to be exceeded.
5. The method of claim 2, further comprising:
and dividing a plurality of memories obtained by mapping a plurality of preset circuits according to a storage space threshold value to obtain a plurality of memory sets.
6. The method of claim 1, wherein splitting memory from the memory set until the memory space of the split remaining memory set does not exceed the memory space of the chip memory comprises:
and splitting the memories included in the memory set according to the sequence of the memory spaces from small to large until the memory space of the rest split memory set does not exceed the memory space of the chip memory.
7. The method of any of claims 1 to 6, further comprising:
and taking the split memory as a register.
8. A memory map processing apparatus, characterized in that,
the device comprises an acquisition module, a storage module and a control module, wherein the acquisition module is used for acquiring a storage set, and the storage included in the storage set is obtained by mapping a preset circuit;
the detection module is used for detecting whether the storage space of the memory set exceeds the storage space of a chip memory;
and the splitting module is used for splitting the memory from the memory set under the condition that the storage space of the memory set is detected to exceed the storage space of the chip memory until the storage space of the rest split memory set does not exceed the storage space of the chip memory.
9. An FPGA chip, comprising:
a processor;
a memory for storing the processor-executable instructions;
wherein the processor is configured to execute the instructions to implement the memory mapping processing method of any of claims 1 to 7.
10. A computer-readable storage medium, wherein instructions in the computer-readable storage medium, when executed by a processor of an electronic device, enable the electronic device to perform the memory mapping processing method of any of claims 1 to 7.
11. A computer program product comprising a computer program, characterized in that the computer program realizes the memory mapping processing method of any of claims 1 to 7 when executed by a processor.
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