CN105760335A - Spacecraft universal interface controller - Google Patents
Spacecraft universal interface controller Download PDFInfo
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Abstract
A spacecraft universal interface controller comprises a bus HOST interface processing unit, a UART interface processing unit, a TDM arbitration processing unit, an instruction parse processing unit, a time sequence parallel interface processing unit, non-time-sequence parallel interface processing unit, a serial data output interface processing unit, a serial data input interface processing unit, a serial data collection interface processing unit and a remote measuring status framing processing unit.The universal controller achieves protocol processing and time sequence control of a time sequence parallel interface, a non-time-sequence parallel interface, a serial data output interface, a serial data input interface and a serial data collection interface through a replaceable processer, data interaction and protocol processing among the interfaces such as a satellite-borne bus and a UARAT interface, the bus system structure of a traditional spacecraft comprehensive electronic computer, information interaction between the processor and the interfaces is simplified, and the overall performance of a spacecraft comprehensive electronic system.
Description
Technical field
The invention belongs to spacecraft composite elctronics technical field, relate to the interface controller used on a kind of spacecraft.
Background technology
Integrated Electronic System is the maincenter of spacecraft information processing, and has substantial amounts of spacecraft communication interface between other subsystems of spacecraft.
In traditional Spacecraft Electronic Interface design, difference due to circuit design and software design, the time sequential routine of spacecraft communication interface and speed are in different spacecrafts and incomplete same, these interface major parts are nonstandard self defined interface, cause the problems such as interface shape is special and of a great variety, poor reliability, fault mode are many, significantly limit Spacecraft Electronic parts and the reliability of hardware module, versatility and durability；These interfaces are controlled by processor completely simultaneously, it is usually how many spacecraft communication interfaces of needs, need exist for how many communication interfaces to be directly connected on a processor, and one by one these spacecraft communication interfaces are written and read by processor the operation purpose to reach sequencing contro.But owing to the communication interface of every kind of spacecraft is different, so the read-write operation sequential of processor and protocol processes are different, causing between processor and spacecraft communication interface must special designs, it is impossible to realize general, multiplexing, can the purpose of flexible expansion.Additionally along with the continuous lifting of the multiformity of spacecraft communication Interface Controller sequential and interface quantity and speed, the control of these interfaces is needed to be operated by various control software by processor, the control software design that each data communication interface is corresponding different, and the multiformity of control software design not only brings the increase of workload, also more fault mode is brought, when the control of these interfaces is occupied a large amount of machine by simultaneous processor, the operation rate of every kind of data communication interface is different, processor must set access speed according to the slowest data communication interface, thus drag slowly the operating rate of processor, cause waste during machine, the control of physical layer interface only be can't bear the heavy load by processor, the calculating resource of processor cannot be given full play to meet the demand of the high-level task of spacecraft.
Therefore, at present in the urgent need to a kind of spacecraft Integrated Electronic System general-purpose interface controller, can contain and realize the function of various spacecraft external interface, processor is made only to communicate at once with general-purpose interface controller, sequencing contro and protocol processes to various different spacecraft external interfaces are then replaced processor to realize by general-purpose interface controller, to improve the work efficiency of Integrated Electronic System.
Summary of the invention
Present invention solves the technical problem that and be: overcome the deficiencies in the prior art, processor is replaced to complete the sequencing contro to various spacecraft communication interfaces and protocol processes with a kind of spacecraft general-purpose interface controller, achieve standardization and the generalization of spacecraft communication interface, simultaneous processor only needs the communication realizing between general-purpose interface controller by standard universal bus, without the operation being concerned about various spacecraft communication interfaces, simplify and unified the information interactive interface of processor, decrease kind and the complexity of processor software, and without considering quick and spacecraft communication interface operation speed at a slow speed compatibility, improve utilization rate during processor machine.
The technical solution of the present invention is: a kind of spacecraft general-purpose interface controller, including bus HOST interface processing unit, UART interface processing unit, TDM arbitration process unit, instruction dissection process unit, sequential parallel interface processing unit, non-sequential parallel interface processing unit, serial data output interface processing unit, serial date transfer interface processing unit, serial data collection interface processing unit, telemetering state framing processing unit, wherein:
nullBus HOST interface processing unit: obtain instruction dissection process unit via TDM arbitration process unit、Sequential parallel interface processing unit、Non-sequential parallel interface processing unit、Serial data output interface processing unit、Serial date transfer interface processing unit、Serial data collection interface processing unit or telemetering state framing processing unit are to the operating control signal of satellite-bone bus and address signal，From satellite-bone bus, read director data accordingly and carry out information feedback via TDM arbitration process unit，Or obtain instruction dissection process unit via TDM arbitration process unit、Sequential parallel interface processing unit、Non-sequential parallel interface processing unit、Serial data output interface processing unit、Serial date transfer interface processing unit、Serial data collection interface processing unit、Reply data in telemetering state framing processing unit also writes satellite-bone bus output；
UART interface processing unit: adopt the mode of asynchronous serial to carry out data transmission, UART interface link layer command protocols data cell is received, and verification territory is judged, verification numeric field data verification that and if only if produces UART interface time correct and controls signal to instruction dissection process unit；Instruction dissection process unit is obtained via TDM arbitration process unit via TDM arbitration process unit, sequential parallel interface processing unit, non-sequential parallel interface processing unit, serial data output interface processing unit, serial date transfer interface processing unit, serial data collection interface processing unit or telemetering state framing processing unit are to the operating control signal of UART interface and address data signal, UART interface application layer command protocols unit is delivered to instruction dissection process unit via TDM arbitration process unit, sequential parallel interface processing unit, non-sequential parallel interface processing unit, serial data output interface processing unit, serial date transfer interface processing unit, serial data collection interface processing unit or telemetering state framing processing unit；The UART interface application layer response protocol unit of instruction dissection process unit, sequential parallel interface processing unit, non-sequential parallel interface processing unit, serial data output interface processing unit, serial date transfer interface processing unit, serial data collection interface processing unit, telemetering state framing processing unit is obtained via TDM arbitration process unit, and form UART interface link layer response protocol unit on this basis, export to UART interface after carrying out parallel-serial conversion；
Instruction dissection process unit: the time-triggered signal of response satellite-bone bus and UART interface control signal, the control domain information director data is obtained from satellite-bone bus or UART interface processing unit, and carry out resolving and decoding, read control signal or write control signal is produced according to instruction type, read-write latent period control signal is produced according to latent period, read-write bit wide control signal is produced according to reading and writing data bit wide, data length control signal is produced according to data length, initial address control signal is produced according to peripheral hardware address, and export to sequential parallel interface processing unit, non-sequential parallel interface processing unit, serial data output interface processing unit, serial date transfer interface processing unit, serial data collection interface processing unit or telemetering state framing processing unit；
TDM arbitration process unit: be the access window that each interface processing unit distributes to bus HOST interface processing unit and UART interface processing unit according to the strategy of " first first " combinations " priority "；Request signal for bus HOST interface processing unit and UART interface processing unit is separately constituted an one-dimension array, priority is distributed according to bit to two the request arrays produced, it is simultaneous for bus HOST interface processing unit and UART interface processing unit produces an one-dimension array for response respectively, each bit and each bit one_to_one corresponding in request one-dimension array in response one-dimension array；When asking one-dimension array only has a bit request signal and being effective, then it is effective by bit position corresponding in corresponding response one-dimension array；When asking one-dimension array has many bits request signal effective simultaneously, extract effective request signal that priority is the highest, and be that effectively the answer signal that other effective request signals are corresponding will not be set to effectively by bit position corresponding in response one-dimension array；When the request signal in request one-dimension array is effective, and corresponding answer signal is set to after effectively, now the request signal of higher priority becomes effectively, then keep that effectively answer signal is constant, after cancelling until corresponding request signal, then process the request signal of higher priority；When response one-dimension array exists effective answer signal, then select bus HOST interface unit according to effective answer signal or UART interface processing unit carries out response；
nullSequential parallel interface processing unit: control for realizing the read and write access to parallel I/O interface，When receiving effective read control signal，Data in initial address control signal are read address directly as parallel I/O interface，The reading data width of parallel I/O interface is controlled according to read-write bit wide control signal，The time that read access operation is required is controlled according to read-write latent period control signal，Carry out latch in the time that latent period specifies to the rear data that parallel I/O interface is read and complete read access operation，Afterwards the reading address of parallel I/O interface is added 1 automatically，Continue the operation of read access next time，Until after completing the data read accesses operation of data length control signal specific length，File a request signal to TDM arbitration process unit，After obtaining answer signal，For bus HOST interface unit data，Obtain bus base address，Bus HOST interface processing unit is given for initial address by the data of reading with bus base address；For UART interface data, give UART interface processing unit using the data of reading as UART interface application layer response protocol unit；When receiving effective write control signal, for UART interface data, to TDM arbitration process unit, UART interface request signal is proposed, after obtaining answer signal, from UART interface processing unit, read the data in the valid data territory in UART interface application layer command protocols unit according to data length control signal；For bus HOST interface unit data, to TDM arbitration process unit, bus request signal is proposed, after obtaining answer signal, obtain bus base address, using bus base address as initial address according to data length control signal from bus HOST interface processing unit read designated length director data valid data numeric field data；Read the write address directly as parallel I/O interface of the data initial address control signal from UART interface processing unit or bus HOST interface processing unit after the data in complete valid data territory, according to read-write bit wide control signal control parallel I/O interface write data width, the time needed for a number of write access operations is controlled according to read-write latent period control signal, the time that latent period specifies to after complete a number of write access operations, afterwards the write address of parallel I/O interface is added 1 automatically, continue number of write access operations next time, until completing the data number of write access operations of data length control signal specific length；
Non-sequential parallel interface processing unit: the input of fixed level signal and output are carried out independent operation, and the output of signal is realized by the write operation of sequential parallel interface, carries out after step-by-step two from three operation the data write as final outputs level signals；The level signal of externally input is carried out data latch by the input of signal, and the data of latch are as a part of telemetering state data of telemetering state framing processing unit；
Serial date transfer interface processing unit: serial input data is sampled and serioparallel exchange, according to read control signal, judge whether complete frame data, if existed, to TDM arbitration process unit, bus or UART interface request signal are proposed according to read control signal, after obtaining corresponding answer signal, for bus HOST interface unit data, according to the bus base address obtained, using bus base address as initial address by all complete frame data write bus HOST interface processing unit, for UART interface data, all complete frame data are write UART interface processing unit according to the form of UART interface application layer response protocol unit；
Serial data output interface processing unit: according to write control signal, bus or UART interface request signal are proposed to TDM arbitration process unit, after obtaining corresponding answer signal, according to the bus base address obtained, using bus base address as initial address according to from bus HOST interface processing unit read data length control signal specific length data, or read the data of data length control signal specific length from UART interface processing unit according to the valid data territory form in UART interface application layer command protocols unit, afterwards the data of reading are carried out parallel-serial conversion, and the serial data after conversion is pressed bit serial output, until the data of data length control signal specific length all export complete；
Serial data collection interface processing unit: according to read control signal, serial data is acquired, and undertaken going here and there and walking around by the serial data of collection, after the data acquisition completing data length control signal specific length, bus or UART interface request signal are proposed to TDM arbitration process unit, after obtaining corresponding answer signal, according to the bus base address obtained, the data write bus HOST interface processing unit that bus base address will be gathered as initial address, or write UART interface processing unit according to the form of UART interface application layer response protocol unit；
Telemetering state framing processing unit: according to read control signal, running state data in each processing unit is latched, bus or UART interface request signal are proposed to TDM arbitration unit, after obtaining corresponding request signal, according to the bus base address obtained, the telemetering state write bus HOST interface processing unit that bus base address will be latched as initial address, or write UART interface processing unit according to the form of UART interface application layer response protocol unit.
Described director data includes functional domain and valid data territory, and wherein functional domain includes again instruction type, latent period, reading and writing data bit wide, data length and read/write address, and valid data territory is concrete write operation data.
Described UART interface link layer command protocols unit includes frame head, address field, length field, data field and verification territory, and wherein said data field includes instruction type, latent period, data bit width, operation address and valid data.Described UART interface link layer response protocol unit includes frame head, address field, instruction type, length field, data field and verification territory, and wherein said data field only comprises valid data.
Described satellite-bone bus is ARINC659 bus.
Present invention advantage compared with prior art is in that:
(1) various spacecraft communication interfaces are carried out unified sequencing contro and protocol processes by general-purpose interface controller of the present invention, overcome communication interface between the different spacecrafts that the dedicated separation circuit design mode of conventional aerospace device causes can not the shortcoming of general and multiplexing, enhance the versatility of spacecraft communication interface and the durability of corresponding circuits and module；
(2) general-purpose interface controller of the present invention adopts ARINC659 bus and UART interface as the communication bus between processor, make processor be only oriented to standard universal bus to communicate with general-purpose interface controller, without the operation being concerned about diversified spacecraft communication interface, simplify processor to the operation of spacecraft communication interface and software design complexity；
(3) general-purpose interface controller of the present invention adopts ARINC659 bus and UART interface as the communication bus between processor, for the spacecraft that spacecraft communication interface quantity demand is different, processor is all the time towards standard universal bus, and namely the general-purpose interface controller that only need to configure respective numbers in ARINC659 bus or UART interface is suitable for the demand to spacecraft communication interface quantity, reach the purpose of spacecraft communication interface flexible extension；
(4) general-purpose interface controller of the present invention is when adopting ARINC659 bus to communicate with processor, by the arbitration mechanism within general-purpose interface controller, multiple spacecraft communication interface can be made to access ARINC659 bus simultaneously, reach the purpose of concurrent working between multiple spacecraft communication interface, improve the communication efficiency of spacecraft interface；
(5) general-purpose interface controller of the present invention arranges sequential parallel interface and non-sequential parallel interface, may replace the parallel interface of processor, realize the purpose all controlled by other all of peripheral circuits outside spacecraft communication interface by general-purpose interface controller, simplify the design of processor peripheral circuit, make processor no longer by the impact of peripheral circuit operating rate, improve utilization rate during the machine of processor；
(6) general-purpose interface controller of the present invention adopts the director data form adopted when ARINC659 bus and UART interface communication consistent, it is to avoid the processor numerous and diverse problem of layout to different data format, the multiplexing for processor software provides base support；
(7) general-purpose interface controller of the present invention is no matter with ARINC659 bus or using UART interface as communication interface, all can pass through ARINC659 bus and the running status of UART interface acquisition controller, grasp the fault mode of controller when being easy to fault in time, strengthen Fault Identification and recovery capability.
Accompanying drawing explanation
Fig. 1 is the connection between general-purpose interface controller of the present invention and processor and Extended Principle Diagram；
Fig. 2 is general-purpose interface controller structure theory of constitution figure of the present invention；
Fig. 3 is general-purpose interface controller instruction dissection process schematic diagram of the present invention；
Fig. 4 is general-purpose interface controller TDM arbitration process schematic diagram of the present invention；
Fig. 5 is general-purpose interface controller UART interface command protocols cell format of the present invention；
Fig. 6 is general-purpose interface controller UART interface response protocol cell format of the present invention.
Detailed description of the invention
The invention provides a kind of spacecraft general-purpose interface controller, using ARINC659 bus and UART interface as IEEE, wherein ARINC659 bus is as " Time Triggered " standard rear panel bus, there is high reliability and fault-tolerance, UART interface, as " event triggering " interface, has feature easy to use.General-purpose interface controller of the present invention can pass through the communication of any one realization in ARINC659 bus or UART interface and processor, by mounting the general-purpose interface controller of the multi-disc present invention in ARINC659 bus or UART interface, the configuration to varying number spacecraft communication interface can be realized, specifically as shown in Figure 1.
General-purpose interface controller of the present invention is using ARINC659 bus as communication interface, or using UART interface as communication interface, interface selects control signal to be controlled, and selects ARINC659 bus as communication interface when interface selects control signal to be high level.Select UART interface as communication interface when interface selects control signal to be low level.
As shown in Figure 2, the spacecraft general-purpose interface controller of the present invention mainly includes ARINC659 bus HOST interface processing unit, UART interface processing unit, TDM arbitration process unit, instruction dissection process unit, sequential parallel interface processing unit, non-sequential parallel interface processing unit, serial data output interface processing unit, serial date transfer interface processing unit, serial data collection interface processing unit, telemetering state framing processing unit, can realize sequential parallel interface simultaneously, non-sequential parallel interface, serial data output interface, serial date transfer interface, the operation of the spacecraft external interfaces such as serial data collection interface controls.
When general-purpose interface controller is using ARINC659 bus as communication interface, the time-triggered signal of ARINC659 bus is responded by instruction dissection process unit, and ARINC659 bus, obtain director data by ARINC659 bus HOST interface processing unit, control signal is produced after carrying out instruction parsing, and it is sent to each spacecraft interface processing unit, exported by spacecraft interface after processing from acquisition data ARINC659 bus by TDM arbitration process unit and ARINC659 bus HOST interface processing unit according to the kind of read-write control signal by each interface processing unit, or reading data deliver to output in ARINC659 bus after processing from spacecraft interface.
When general-purpose interface controller is using UART interface as communication interface, completed the reception of data on UART by UART interface processing unit, and carried out instruction parsing by instruction dissection process unit after receiving, and produce corresponding control signal and deliver to each spacecraft interface processing unit, obtained from UART interface processing unit after data process by TDM arbitration process unit according to the kind of read-write control signal by each interface processing unit and exported by spacecraft interface, or reading data deliver to UART interface processing unit after processing from spacecraft interface, exported by UART interface again.
nullAs shown in Figure 3，ARINC659 bus HOST interface processing unit passes through address bus，Data/address bus，Control bus and carry out data interaction with ARINC659 bus，Complete the read-write operation of data in ARINC659 bus，ARINC659 bus is as the communication bus of " Time Triggered " form simultaneously，Time-triggered signal can be produced according to time planning timing，After instruction resolution unit receives the ARINC659 bus time triggering signal of Low level effective，To TDM arbitration process unit, ARINC659 bus request signal is proposed，And wait answer signal，After obtaining effective ARINC659 bus answer signal，Time Triggered code as shown in table 1 in ARINC659 bus is read by ARINC659 bus HOST interface processing unit，Tabling look-up according to the spacecraft communication interface that Time Triggered code is corresponding, (space between two base address determines interface and takies ARINC659 bus space size in acquisition corresponding base address as shown in table 2，It is 1024 bytes to the maximum)，Data further according to the functional domain part in director data form as shown in table 3 in base address reading ARINC659 bus，Instruction parsing and decoding is carried out afterwards according to the data of functional domain part，Instruction type according to table 3 produces read control signal or the write control signal of each spacecraft communication interface，Latent period according to table 3 produces read-write latent period control signal，Reading and writing data bit wide according to table 3 produces read-write bit wide control signal，Data length according to table 3 produces data length control signal，Peripheral hardware address according to table 3 produces initial address control signal，After producing each spacecraft communication interface control signal corresponding to ARINC659 bus as shown in Figure 3，Docking port selects control signal to carry out judging (to come outside self-controller，See Fig. 2，It is by controller pin input)，If interface selects control signal to be high level，Then the interface control signal of generation is exported to corresponding interface control unit，Wherein sequential parallel interface control unit comprises the instruction dissection process unit all 6 kinds of control signals of generation，And serial data output interface processing unit only comprises write control signal and data length control signal，Serial data collection interface processing unit only comprises read control signal and data length control signal，Serial date transfer interface processing unit and telemetering state framing processing unit only comprise read control signal，If interface selects control signal to be low level，Then will not to the interface control signal output produced.
Table 1ARINC659 bus time trigger code
| Time Triggered code | Implication |
| 1 | Sequential parallel interface 1 Time Triggered code |
| …… | …… |
| i | Sequential parallel interface i Time Triggered code |
| i+1 | Serial data output interface 1 Time Triggered code |
| …… | …… |
| i+j | Serial data output interface j Time Triggered code |
| i+j+1 | Serial date transfer interface 1 Time Triggered code |
| …… | …… |
| i+j+m | Serial date transfer interface m Time Triggered code |
| i+j+m+1 | Serial data collection interface 1 Time Triggered code |
| …… | …… |
| i+j+m+n | Serial data collection interface n Time Triggered code |
| i+j+m+n+1 | Telemetering state framing Time Triggered code |
Table 2ARINC659 bus base address
| Base address | Implication |
| Base address 1 | Sequential parallel interface 1 corresponding A RINC659 bus base address |
| …… | |
| Base address i | Sequential parallel interface i corresponding A RINC659 bus base address |
| Base address i+1 | Serial data output interface 1 corresponding A RINC659 bus base address |
| …… | |
| Base address i+j | Serial data output interface j corresponding A RINC659 bus base address |
| Base address i+j+1 | Serial date transfer interface 1 corresponding A RINC659 bus base address |
| …… | |
| Base address i+j+m | Serial date transfer interface m corresponding A RINC659 bus base address |
| Base address i+j+m+1 | Serial data collection interface 1 corresponding A RINC659 bus base address |
| Base address i+j+m+n | Serial data collection interface n corresponding A RINC659 bus base address |
| Base address i+j+m+n+1 | Telemetering state framing corresponding A RINC659 bus base address |
Table 3 director data form
UART interface adopts asynchronous serial data transmission, and the transmission of every byte data comprises 1bit start bit, 8bit data bit, 1bit check bit, 1bit stop bits.As it is shown on figure 3, UART interface processing unit passes through Serial data receiving signal, serial data sends signal and realizes the transmitting-receiving of serial data on asynchronous serial bus, string are also operated with parallel-serial conversion, solution frame and framing etc..nullFirst the frame head of UART interface link layer command protocols data cell as shown in Figure 5 is detected by UART interface processing unit，When completing the reception in data field and verification territory in UART interface link layer command protocols data cell as shown in Figure 5 after frame head " EB90 " being detected according to address field and length field，Data in data field are carried out exclusive or check calculating by reception process，And judgement that the checking data of calculating and the verification numeric field data received are compared，This frame data are abandoned when Inspection mistake，Produce UART interface when Inspection is correct and control signal to instruction dissection process unit，Instruction dissection process unit proposes UART interface request signal to TDM arbitration process unit after receiving UART interface control signal，And wait answer signal，After obtaining effective UART interface answer signal，Read in UART interface processing unit the functional domain part data in UART interface application layer command protocols data cell as shown in Figure 5，Instruction parsing is carried out according to the data of functional domain part，Wherein functional domain part data are identical with analysis mode with form shown in table 1 with instruction analysis mode，And producing after corresponding to each communication interface control signal of spacecraft of UART interface，Docking port selects control signal to judge，If interface selects control signal to be low level，Then the interface control signal of generation is exported to corresponding interface control unit，If interface selects control signal to be high level，Then will not to the interface control signal output produced.
Carry out in instruction resolving at instruction dissection process unit, have a kind of exception is no matter interface selects control signal to be high level or low level, as long as the instruction type for telemetering state framing processing unit being detected, telemetering state framing control signal from ARINC659 bus or the telemetering state framing control signal from UART interface are exported by capital, cannot under signal intelligence in ARINC659 bus, UART interface can be passed through and obtain the running status of general-purpose interface controller in time, or cannot under signal intelligence in UART interface, ARINC659 bus can be passed through and obtain the running status of general-purpose interface controller in time, it is beneficial to process and the identification of fault.
As shown in Figure 4, TDM arbitration process unit is time-sharing multiplex arbitration unit, is each interface processing unit distribution access window to ARINC659 bus HOST interface processing unit and UART interface processing unit according to the strategy of " first obtaining first " combination " priority ".The instruction dissection process unit being connected with TDM arbitration process unit, the request signal for ARINC659 bus HOST interface processing unit and UART interface processing unit is comprised respectively between telemetering state framing processing unit and each interface processing unit, answer signal, operation control/address/data signal, owing to the operation signal of ARINC659 bus HOST interface processing unit and UART interface processing unit is separate, therefore the arbitration of ARINC659 bus HOST interface processing unit and UART interface processing unit can be carried out and be independent of each other by TDM arbitration unit parallel.Instruction dissection process unit, the request signal of ARINC659 bus HOST interface processing unit and UART interface processing unit is packaged into an one-dimension array by telemetering state framing processing unit and each spacecraft communication interface processing unit respectively, the two one-dimension array is lowest order and has limit priority, and from lowest order to highest order, priority reduces successively, TDM arbitration process unit also can produce an one-dimension array for response for ARINC659 bus HOST interface processing unit and UART interface processing unit respectively simultaneously, each bit and each bit one_to_one corresponding in request one-dimension array in response one-dimension array.
When asking one-dimension array only has a bit request signal and being effective, then it is effective by bit position corresponding in corresponding response one-dimension array；When asking one-dimension array has many bits request signal effective simultaneously, TDM arbitration process unit extracts effective request signal of lowest bit, and be effective by bit position corresponding in response one-dimension array, the answer signal that other effective request signals are corresponding will not be set to effectively；When the request signal in request one-dimension array is effective, and corresponding answer signal is set to after effectively, now more the request signal of low bit becomes effectively, then effectively answer signal is constant for the maintenance of TDM arbitration process unit, after cancelling until corresponding request signal, just can process the request signal of more low bit again, it is ensured that do not interrupt the operation having obtained answer signal processing unit, ensure that any time response one-dimension array only has a bit answer signal effective simultaneously.When response one digit number group exists effective answer signal, then control to select corresponding control/address/data signal according to effective answer signal and be connected to ARINC659 bus HOST interface unit or UART interface processing unit.
When TDM arbitration process unit is filed a request signal by each interface processing unit, and after obtaining answer signal, data can be read and write from ARINC659 bus HOST interface processing unit or UART interface processing unit in units of 32 byte datas, after 32 byte read-writes, discharge a request signal, make TDM arbitration process unit that answer signal can be distributed to other interfaces, signal of more than 2 clock cycle again filing a request is waited after releasing request signal, circulate repeatedly until the reading and writing data of specific length is complete with this, the problem that an interface takies arbitration passage for a long time can be avoided in this way, make what total interface can be parallel to enjoy arbitration passage, reach the purpose of total interface concurrent working.
Sequential parallel interface processing unit controls for realizing the read and write access to parallel I/O interface, and the control signal between instruction dissection process unit comprises read control signal, write control signal, initial address control signal, data length control signal, read-write bit wide control signal, read-write latent period control signal, as shown in Figure 3, these control signals both can correspond to UART interface, it is also possible to corresponding to ARINC659 bus.
When sequential parallel interface processing unit receives effective read control signal, data in initial address control signal are read address directly as parallel I/O interface, the reading data width of parallel I/O interface is controlled according to read-write bit wide control signal, the time that read access operation is required is controlled according to read-write latent period control signal, carry out latch in the time that latent period specifies to the rear data that parallel I/O interface is read and complete read access operation, afterwards the reading address of parallel I/O interface is added 1 automatically, continue the operation of read access next time, until after completing the data read accesses operation of data length control signal specific length, file a request signal to TDM arbitration process unit shown in Fig. 4.nullIf the control signal that instruction dissection process unit provides is for UART interface，Then to TDM arbitration process unit, UART interface request signal is proposed，After obtaining UART interface answer signal，UART interface processing unit is given as the UART interface application layer response protocol unit shown in Fig. 6 using the data of reading，UART interface processing unit adds frame head " EB90 " on the basis of UART interface application layer response protocol unit afterwards，Adding address field is the address field data extracted from the command protocols unit of UART interface link layer shown in Fig. 5，Adding instruction type is the instruction type extracted from the command protocols unit of UART interface application layer shown in Fig. 5，Afterwards data field content is calculated exclusive or check data and forms UART interface link layer responder link level agreement unit as shown in Figure 6 as the data in verification territory，Exported by UART interface after carrying out parallel-serial conversion；If the control signal that instruction dissection process unit provides is for ARINC659 bus, then to TDM arbitration process unit, ARINC659 bus request signal is proposed, after obtaining ARINC659 bus answer signal, the ARINC659 bus base address that interface is corresponding is obtained by shown in table 2, give ARINC659 bus HOST interface processing unit with ARINC659 bus base address for initial address by the data of reading form shown in table 4, ARINC659 bus HOST interface processing unit write data into and ARINC659 bus exports.
Table 4 general-purpose interface controller response data format
nullWhen sequential parallel interface receives effective write control signal，If write control signal is for UART interface，Then to TDM arbitration process unit, UART interface request signal is proposed，After obtaining UART interface answer signal，From UART interface processing unit, the data (form is identical with valid data territory form in table 3) in the valid data territory in UART interface application layer command protocols unit as shown in Figure 5 are read according to data length control signal，If write control signal is for ARINC659 bus，Then to TDM arbitration process unit, ARINC659 bus request signal is proposed，After obtaining ARINC659 bus answer signal，The ARINC659 bus base address that interface is corresponding is obtained by table 2，Data as shown in table 3 valid data territory are read according to data length control signal from ARINC659 bus HOST interface processing unit as initial address using ARINC659 bus base address.Read the write address directly as parallel I/O interface of the data in initial address control signal after the data in complete valid data territory, according to read-write bit wide control signal control parallel I/O interface write data width, the time needed for a number of write access operations is controlled according to read-write latent period control signal, the time that latent period specifies to after complete a number of write access operations, afterwards the write address of parallel I/O interface is added 1 automatically, continue number of write access operations next time, until completing the data number of write access operations of data length control signal specific length.
Non-sequential parallel interface processing unit realizes the input-output operation to fixed level signal, and wherein input and output signal is separate.The output of signal is controlled by the write operation of sequential parallel interface with 16 bits for a unit, the signal output of every 16 bits is undertaken exporting after step-by-step two from three operates by 3 16 Bit datas, therefore every 16 bit signal outputs need 3 write operations of sequential parallel interface just to complete, once complete non-sequential parallel interface processing unit is exported the write operation of signal, the output interface of non-sequential parallel interface processing unit will maintain the level state write always, until it is carried out write operation next time；The input of signal carries out data latch with 16bit for a unit, the data latched are directly sent to telemetering state framing processing unit, it is bundled in telemetry frame as a part of telemetering state data by telemetering state framing processing unit and processes, every pair of telemetering state framing processing unit carries out a read operation, and external input signal is just once latched by non-sequential parallel interface.
Serial date transfer interface processing unit realizes the reception of synchronous serial data, serioparallel exchange etc. are operated.nullThe reception of serial data is passive by serial date transfer interface processing unit，And in units of frame，The greatest length of frame is 1024 bytes，Control signal between serial date transfer interface processing unit and instruction dissection process unit only comprises read control signal，When there is effective read control signal，Serial date transfer interface processing unit judges whether complete frame data，If existed, to TDM arbitration process unit, ARINC659 bus or UART interface request signal are proposed according to the kind of read control signal，After obtaining corresponding answer signal，The ARINC659 bus base address that interface is corresponding is obtained according to table 2，Using ARINC659 bus base address as initial address by all complete frame data shown in table 4 form write ARINC659 bus HOST interface processing unit，Maybe by all complete frame data according to the form write UART interface processing unit of UART interface Protocol layer data unit in Fig. 6，ARINC659 bus HOST interface processing unit or UART interface processing unit are identical with the data processing method of sequential parallel interface processing unit to the processing mode of data.
Serial data output interface processing unit realizes the output of synchrodata, parallel-serial conversion etc. are operated.The output of serial data is actively by serial data output interface processing unit, the data of maximum exportable 1018 bytes.nullControl signal between serial data output interface processing unit and instruction dissection process unit includes write control signal and data length control signal，When there is effective write control signal，The serial data output interface processing unit kind according to write control signal，ARINC659 bus or UART interface request signal are proposed to TDM arbitration process unit，After obtaining corresponding answer signal，Obtain, shown in table 2, the ARINC659 bus base address that interface is corresponding，Using ARINC659 bus base address as initial address shown in table 3 form in valid data territory from ARINC659 bus HOST interface processing unit read data length control signal specific length data，Or the valid data territory form in UART interface application layer command protocols unit shown in Fig. 5 reads the data of data length control signal specific length from UART interface processing unit，Afterwards the data of reading are carried out parallel-serial conversion，And the serial data after conversion is pressed bit serial output，Until the data of data length control signal specific length all export complete.
The operations such as serial data collection interface processing unit realizes the collection of synchronous serial data is received, serioparallel exchange, it is on one's own initiative that the collection of data is received by serial data collection interface processing unit, the maximum data gathering 1024 bytes.nullControl signal between serial data collection interface processing unit and instruction dissection process unit includes read control signal and data length control signal，When there is effective read control signal，Serial data is acquired by serial data collection interface processing unit，And undertaken going here and there and walking around by the serial data of collection，After the data acquisition completing data length control signal specific length，Kind according to read control signal，ARINC659 bus or UART interface request signal are proposed to TDM arbitration process unit，After obtaining corresponding answer signal，Obtain, shown in table 2, the ARINC659 bus base address that interface is corresponding，Using ARINC659 bus base address as initial address by gather data shown in table 4 form write ARINC659 bus HOST interface processing unit，Or the form write UART interface processing unit of UART interface application layer response protocol unit shown in Fig. 6，ARINC659 bus HOST interface processing unit or UART interface processing unit are identical with the data processing method of sequential parallel interface processing unit to the processing mode of data.
Telemetering state framing processing unit, for the running state data that general-purpose interface controller various places inside is managed in unit is carried out Real-time Collection, the status signal lines that the running state data of each interface processing unit is connected between each interface processing unit with telemetering state framing processing unit is transmitted.nullControl signal between telemetering state framing processing unit and instruction dissection process unit comprises read control signal，When there is effective read control signal，Telemetering state framing processing unit first directly will latch with the data in the status signal lines being connected between each processing unit，Backward TDM arbitration unit ARINC659 bus or UART interface request signal are proposed，After obtaining corresponding request signal，The ARINC659 bus base address of correspondence is obtained according to table 2，Telemetering state data form write ARINC659 bus HOST interface processing unit shown in table 4 that ARINC659 bus base address will be latched as initial address，Or the form write UART interface processing unit of UART interface application layer response protocol unit shown in Fig. 6，Wherein the telemetering state data of the latch of write ARINC659 bus HOST interface processing unit and UART interface processing unit are with 16bit for ultimate unit，When the integral multiple of all of inadequate 16bit of telemetering state data，Then in the end the higher bit position filling 0 of telemetering state data carrys out polishing 16bit data.
Instruction type in Fig. 5, latent period, data bit width, operation address and valid data are corresponding with the functional domain in table 3 and valid data territory, content is consistent, instruction type, latent period, data bit width, operation address corresponding function territory, valid data correspondence valid data territory, because instruction dissection process unit only one of which, therefore no matter it is be from ARINC659 bus or the data form from UART, the valid data territory in valid data correspondence table 4 in Fig. 6, content is consistent.UART simply encapsulates again the agreement of one layer of link layer on the basis of ARINC659 bus data form (corresponding UART interface application layer protocol unit).
Address field in UART interface link layer response protocol unit is consistent with the address field in UART interface link layer command protocols unit.Instruction type in UART interface link layer response protocol unit is consistent with the instruction type in UART interface link layer command protocols cell data territory.
The content not being described in detail in description of the present invention belongs to the known technology of those skilled in the art.
Claims (6)
1. a spacecraft general-purpose interface controller, it is characterized in that: include bus HOST interface processing unit, UART interface processing unit, TDM arbitration process unit, instruction dissection process unit, sequential parallel interface processing unit, non-sequential parallel interface processing unit, serial data output interface processing unit, serial date transfer interface processing unit, serial data collection interface processing unit, telemetering state framing processing unit, wherein:
nullBus HOST interface processing unit: obtain instruction dissection process unit via TDM arbitration process unit、Sequential parallel interface processing unit、Non-sequential parallel interface processing unit、Serial data output interface processing unit、Serial date transfer interface processing unit、Serial data collection interface processing unit or telemetering state framing processing unit are to the operating control signal of satellite-bone bus and address signal，From satellite-bone bus, read director data accordingly and carry out information feedback via TDM arbitration process unit，Or obtain instruction dissection process unit via TDM arbitration process unit、Sequential parallel interface processing unit、Non-sequential parallel interface processing unit、Serial data output interface processing unit、Serial date transfer interface processing unit、Serial data collection interface processing unit、Reply data in telemetering state framing processing unit also writes satellite-bone bus output；
UART interface processing unit: adopt the mode of asynchronous serial to carry out data transmission, UART interface link layer command protocols data cell is received, and verification territory is judged, verification numeric field data verification that and if only if produces UART interface time correct and controls signal to instruction dissection process unit；Instruction dissection process unit is obtained via TDM arbitration process unit via TDM arbitration process unit, sequential parallel interface processing unit, non-sequential parallel interface processing unit, serial data output interface processing unit, serial date transfer interface processing unit, serial data collection interface processing unit or telemetering state framing processing unit are to the operating control signal of UART interface and address data signal, UART interface application layer command protocols unit is delivered to instruction dissection process unit via TDM arbitration process unit, sequential parallel interface processing unit, non-sequential parallel interface processing unit, serial data output interface processing unit, serial date transfer interface processing unit, serial data collection interface processing unit or telemetering state framing processing unit；The UART interface application layer response protocol unit of instruction dissection process unit, sequential parallel interface processing unit, non-sequential parallel interface processing unit, serial data output interface processing unit, serial date transfer interface processing unit, serial data collection interface processing unit, telemetering state framing processing unit is obtained via TDM arbitration process unit, and form UART interface link layer response protocol unit on this basis, export to UART interface after carrying out parallel-serial conversion；
Instruction dissection process unit: the time-triggered signal of response satellite-bone bus and UART interface control signal, the control domain information director data is obtained from satellite-bone bus or UART interface processing unit, and carry out resolving and decoding, read control signal or write control signal is produced according to instruction type, read-write latent period control signal is produced according to latent period, read-write bit wide control signal is produced according to reading and writing data bit wide, data length control signal is produced according to data length, initial address control signal is produced according to peripheral hardware address, and export to sequential parallel interface processing unit, non-sequential parallel interface processing unit, serial data output interface processing unit, serial date transfer interface processing unit, serial data collection interface processing unit or telemetering state framing processing unit；
TDM arbitration process unit: be the access window that each interface processing unit distributes to bus HOST interface processing unit and UART interface processing unit according to the strategy of " first first " combinations " priority "；Request signal for bus HOST interface processing unit and UART interface processing unit is separately constituted an one-dimension array, priority is distributed according to bit to two the request arrays produced, it is simultaneous for bus HOST interface processing unit and UART interface processing unit produces an one-dimension array for response respectively, each bit and each bit one_to_one corresponding in request one-dimension array in response one-dimension array；When asking one-dimension array only has a bit request signal and being effective, then it is effective by bit position corresponding in corresponding response one-dimension array；When asking one-dimension array has many bits request signal effective simultaneously, extract effective request signal that priority is the highest, and be that effectively the answer signal that other effective request signals are corresponding will not be set to effectively by bit position corresponding in response one-dimension array；When the request signal in request one-dimension array is effective, and corresponding answer signal is set to after effectively, now the request signal of higher priority becomes effectively, then keep that effectively answer signal is constant, after cancelling until corresponding request signal, then process the request signal of higher priority；When response one-dimension array exists effective answer signal, then select bus HOST interface unit according to effective answer signal or UART interface processing unit carries out response；
nullSequential parallel interface processing unit: control for realizing the read and write access to parallel I/O interface，When receiving effective read control signal，Data in initial address control signal are read address directly as parallel I/O interface，The reading data width of parallel I/O interface is controlled according to read-write bit wide control signal，The time that read access operation is required is controlled according to read-write latent period control signal，Carry out latch in the time that latent period specifies to the rear data that parallel I/O interface is read and complete read access operation，Afterwards the reading address of parallel I/O interface is added 1 automatically，Continue the operation of read access next time，Until after completing the data read accesses operation of data length control signal specific length，File a request signal to TDM arbitration process unit，After obtaining answer signal，For bus HOST interface unit data，Obtain bus base address，Bus HOST interface processing unit is given for initial address by the data of reading with bus base address；For UART interface data, give UART interface processing unit using the data of reading as UART interface application layer response protocol unit；When receiving effective write control signal, for UART interface data, to TDM arbitration process unit, UART interface request signal is proposed, after obtaining answer signal, from UART interface processing unit, read the data in the valid data territory in UART interface application layer command protocols unit according to data length control signal；For bus HOST interface unit data, to TDM arbitration process unit, bus request signal is proposed, after obtaining answer signal, obtain bus base address, using bus base address as initial address according to data length control signal from bus HOST interface processing unit read designated length director data valid data numeric field data；Read the write address directly as parallel I/O interface of the data initial address control signal from UART interface processing unit or bus HOST interface processing unit after the data in complete valid data territory, according to read-write bit wide control signal control parallel I/O interface write data width, the time needed for a number of write access operations is controlled according to read-write latent period control signal, the time that latent period specifies to after complete a number of write access operations, afterwards the write address of parallel I/O interface is added 1 automatically, continue number of write access operations next time, until completing the data number of write access operations of data length control signal specific length；
Non-sequential parallel interface processing unit: the input of fixed level signal and output are carried out independent operation, and the output of signal is realized by the write operation of sequential parallel interface, carries out after step-by-step two from three operation the data write as final outputs level signals；The level signal of externally input is carried out data latch by the input of signal, and the data of latch are as a part of telemetering state data of telemetering state framing processing unit；
Serial date transfer interface processing unit: serial input data is sampled and serioparallel exchange, according to read control signal, judge whether complete frame data, if existed, to TDM arbitration process unit, bus or UART interface request signal are proposed according to read control signal, after obtaining corresponding answer signal, for bus HOST interface unit data, according to the bus base address obtained, using bus base address as initial address by all complete frame data write bus HOST interface processing unit, for UART interface data, all complete frame data are write UART interface processing unit according to the form of UART interface application layer response protocol unit；
Serial data output interface processing unit: according to write control signal, bus or UART interface request signal are proposed to TDM arbitration process unit, after obtaining corresponding answer signal, according to the bus base address obtained, using bus base address as initial address according to from bus HOST interface processing unit read data length control signal specific length data, or read the data of data length control signal specific length from UART interface processing unit according to the valid data territory form in UART interface application layer command protocols unit, afterwards the data of reading are carried out parallel-serial conversion, and the serial data after conversion is pressed bit serial output, until the data of data length control signal specific length all export complete；
Serial data collection interface processing unit: according to read control signal, serial data is acquired, and undertaken going here and there and walking around by the serial data of collection, after the data acquisition completing data length control signal specific length, bus or UART interface request signal are proposed to TDM arbitration process unit, after obtaining corresponding answer signal, according to the bus base address obtained, the data write bus HOST interface processing unit that bus base address will be gathered as initial address, or write UART interface processing unit according to the form of UART interface application layer response protocol unit；
Telemetering state framing processing unit: according to read control signal, running state data in each processing unit is latched, bus or UART interface request signal are proposed to TDM arbitration unit, after obtaining corresponding request signal, according to the bus base address obtained, the telemetering state write bus HOST interface processing unit that bus base address will be latched as initial address, or write UART interface processing unit according to the form of UART interface application layer response protocol unit.
2. a kind of spacecraft general-purpose interface controller according to claim 1, it is characterized in that: described director data includes functional domain and valid data territory, wherein functional domain includes again instruction type, latent period, reading and writing data bit wide, data length and read/write address, and valid data territory is concrete write operation data.
3. a kind of spacecraft general-purpose interface controller according to claim 1 and 2, it is characterised in that: described UART interface link layer command protocols unit includes frame head, address field, length field, data field and verification territory.
4. a kind of spacecraft general-purpose interface controller according to claim 3, it is characterised in that: described data field includes instruction type, latent period, data bit width, operation address and valid data.
5. a kind of spacecraft general-purpose interface controller according to claim 1 and 2, it is characterised in that: described UART interface link layer response protocol unit includes frame head, address field, instruction type, length field, data field and verification territory.
6. a kind of spacecraft general-purpose interface controller according to claim 1 and 2, it is characterised in that: described satellite-bone bus is ARINC659 bus.
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