CN112802537A

CN112802537A - Testing device and chip module

Info

Publication number: CN112802537A
Application number: CN202011613428.5A
Authority: CN
Inventors: 李海洋
Original assignee: Haiguang Information Technology Co Ltd
Current assignee: Haiguang Information Technology Co Ltd
Priority date: 2020-12-30
Filing date: 2020-12-30
Publication date: 2021-05-14
Anticipated expiration: 2040-12-30
Also published as: CN112802537B

Abstract

The application provides a testing arrangement and chip module, the device includes: the first collector is used for collecting chip selection signals of the interface of the module to be detected; the signal processor is connected with the first collector and used for widening the chip selection signal to generate a widened chip selection signal; the second collector is used for collecting the address control signal of the module interface to be detected; the time sequence detector is respectively connected with the first collector, the signal processor and the second collector and is used for detecting the time sequence information of the chip selection signal, the address control signal and the widened chip selection signal; and the state machine is connected with the time sequence detector and used for verifying whether the time sequence information meets a preset time sequence rule or not. The method and the device realize the sharing of one set of circuit to carry out time sequence inspection on the CS and CA sequences so as to accelerate the test and the rapid debugging of the chip controller.

Description

Testing device and chip module

Technical Field

The application relates to the technical field of memories, in particular to a testing device and a chip module.

Background

DDRx SDRAM (Synchronous Dynamic Random Access Memory, SDRAM for short) is the main Memory of computer system, and has been developed to the fifth generation, DDR5 SDRAM through years of development. The DDR5 SDRAM is a fifth generation double data rate synchronous dynamic random access memory chip particle, compared with DDR4, the IO interface voltage is reduced, the interface rate is greatly improved, the memory capacity is larger, and the interface signals are reduced, so that a memory system with low power consumption, high bandwidth and high capacity can be provided. However, as the transmission speed increases and the interface voltage decreases, greater challenges are presented to the integrity of SDRAM signal transmission. Therefore, compared with DDR4, DDR5 has made a great innovation on CA signals, SDRAM uses one CS, one CKE and 26 CA lines for 28 CA lines from DDR4, and uses one CS and 14 CA lines for 15 CA lines from DDR5, and reduces the number of IO interfaces and wiring resources by reducing 13 CA lines, thereby reducing signal crosstalk and saving power consumption and further improving signal transmission speed.

Due to the high transfer rate of the DDR5, signal integrity is greatly challenged, the command protocol is complex, and it is necessary to perform a post-silicon test on the DDR5 test to test that the command sequence sent by the chip controller meets the DDR5 protocol specification.

Disclosure of Invention

An object of the embodiment of the present application is to provide a testing apparatus and a chip module, which implement sharing a set of circuits to perform timing sequence inspection on CS and CA sequences, so as to accelerate testing and rapid debugging of a chip controller.

A first aspect of an embodiment of the present application provides a command scheduling method, including: the first collector is used for collecting chip selection signals of the interface of the module to be detected; the signal processor is connected with the first collector and used for widening the chip selection signal to generate a widened chip selection signal; the second collector is used for collecting the address control signal of the module interface to be detected; the time sequence detector is respectively connected with the first collector, the signal processor and the second collector and is used for detecting the time sequence information of the chip selection signal, the address control signal and the widened chip selection signal; and the state machine is connected with the time sequence detector and used for verifying whether the time sequence information meets a preset time sequence rule or not.

In one embodiment, the signal processor includes: the first delayer is connected with the first collector and used for delaying the chip selection signal and then generating a chip selection delay signal; and the logic AND gate is respectively connected with the first collector and the first delayer and is used for performing logic AND operation on the chip selection signal and the chip selection delay signal to generate the widened chip selection signal.

In one embodiment, the timing detector comprises: and the high level time detection circuit is connected with the first delayer and used for detecting and obtaining the time for maintaining the high level of the chip selection delay signal.

In one embodiment, the timing detector comprises: and the mode detection circuit is connected with the first delayer and used for detecting and obtaining the current signal change mode of the chip selection delay signal.

In one embodiment, the timing detector comprises: and the low level time detection circuit is connected with the logic AND gate and is used for detecting whether the low level duration of the widening chip selection signal is within a preset duration or not and sending out prompt information when the low level duration of the widening chip selection signal is not within the preset duration.

In one embodiment, the timing detector comprises: and the continuous high detection circuit is connected with the second collector and is used for detecting whether the address control signal accords with a preset high level or not and sending prompt information when the address control signal does not accord with the preset high level.

In an embodiment, the state machine is respectively connected to the high level time detection circuit, the mode detection circuit, the low level time detection circuit, and the high duration detection circuit, and is configured to verify whether the timing information conforms to a preset timing rule according to the timing information reported by the high level time detection circuit, the mode detection circuit, the low level time detection circuit, and the high duration detection circuit.

In one embodiment, the method further comprises: and the input end of the decoder is respectively connected with the first collector and the second collector, and the output end of the decoder is connected with the signal processor and is used for decoding the chip selection signal and the address control signal to generate a decoding signal.

In one embodiment, the signal processor includes: the second delayer is connected with the decoder and used for delaying the decoding signal and then generating a decoding delayed signal; and the logic OR gate is respectively connected with the decoder and the second delayer and is used for carrying out logic OR operation on the decoding signal and the decoding delay signal to generate a stretched decoding signal.

In one embodiment, the timing detector further comprises: and the first counter is respectively connected with the decoder and the logic OR gate and is used for counting the deselected command in the decoded signal to be high level to obtain first counting information, and the time sequence information comprises the first counting information.

In one embodiment, the timing detector further comprises: and the second counter is connected with the decoder and is used for counting the idle operation command in the decoded signal to be high level to obtain second counting information, and the time sequence information comprises the second counting information.

In an embodiment, the state machine is respectively connected to the first counter and the second counter, and configured to verify whether the timing information conforms to a preset timing rule according to the first count information and the second count information, and control enabling states of the first counter and the second counter.

In one embodiment, the method further comprises: and the state register is connected with the time sequence detector and is used for triggering the time sequence detector to start detection when the module to be detected is in a self-refreshing state.

In one embodiment, the method further comprises: and the module type register is connected with the state machine and used for sending the module type information of the module to be tested to the state machine.

In one embodiment, the first collector includes: the chip selection signal interface is connected with a chip selection signal pin of the module interface to be tested and is accessed to an initial chip selection signal; and the first sampling register is connected with the chip selection signal interface and is used for sampling the initial chip selection signal to obtain the chip selection signal.

In one embodiment, the second collector includes: the address control line interface is connected with an address command line pin of the module interface to be tested and is accessed to an initial address command signal; and the second sampling register is connected with the address control line interface and is used for sampling the initial address command signal to obtain the address control signal.

In one embodiment, the method further comprises: and the idle operation command detection circuit is respectively connected with the signal processor and the state machine and is used for detecting whether an idle operation command is received.

In one embodiment, the method further comprises: and the clock detection circuit is respectively connected with the module interface to be detected and the state machine and is used for detecting the shutdown state of the clock signal of the module interface to be detected.

A second aspect of the embodiments of the present application provides a chip module, including: the test device of the first aspect of the embodiments of the present application and any embodiment thereof; and the module to be tested is connected with the testing device, and the testing device is used for carrying out signal time sequence testing on the interface of the module to be tested.

The application provides a testing arrangement and chip module, through two way collectors gather respectively the chip selection signal and the address control signal of module interface that awaits measuring to adopt signal processor to widen the processing to the chip selection signal, then carry out the chronogenesis detection to widening chip selection signal and address control signal by sequential detection circuit, verify the chronogenesis information that detects through the state machine at last. Therefore, the method realizes the sequential inspection of the SRX command sequences of various CA rate modes and various CS modes under various modules by sharing one set of circuit, so as to accelerate the test and the rapid debugging of the chip controller.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and that those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.

Fig. 1 is a schematic structural diagram of a chip module according to an embodiment of the present application;

FIG. 2 is a schematic circuit diagram of a testing apparatus according to an embodiment of the present application;

FIG. 3 is a schematic circuit diagram of a testing apparatus according to an embodiment of the present application;

fig. 4 is a schematic circuit structure diagram of a testing apparatus according to an embodiment of the present application.

1-chip module, 10-module under test, 20-test device, 21-first collector, 22-signal processor, 23-second collector, 24-timing detector, 25-state machine, 211-chip selection signal interface, 212-first sampling register, 221-first delay, 222-logic AND gate, 231-address control line interface, 232-second sampling register, 241-mode detection circuit, 242-low level time detection circuit, 243-continuous high detection circuit, 244-high level time detection circuit, 245-state register, 246-module type register, 247-null operation command detection circuit, 26-decoder, 248-second delay, 249-logic OR gate, 2410-first counter, 2411-second counter, 26-clock detection circuit.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. In the description of the present application, the terms "first," "second," and the like are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.

For clarity of describing aspects of the present embodiment, the terms referred to are now defined as follows:

DDR: double Data Rate, i.e., both clock rising and falling edges, transfers Data.

SDR: the Single Data Rate transfers Data only on the rising or falling edge of the clock.

SDRAM, Synchronous Dynamic Random Memory.

DDR 5: the abbreviation DDR5 SDRAM, the fifth generation double data Rate synchronous dynamic random Access memory.

MC: memory Controller, Memory Controller.

RCD: register Clock Driver, Register Clock buffer.

CS: and chip selection signals.

CA: control and Address, the Address Control signal line.

DIMM: dual In-line Memory, Memory module.

RDIMM: register DIMM (dual inline memory module), a Register memory module, is a DIMM with RCD for buffering CA signals.

UDIMM, Un-buffer DIMM, unbuffered memory modules.

DQ: SDRAM data signal lines.

DQS: the SDRAM data Strobe signal line is a differential signal, DQ Strobe.

Rank: a storage array.

SR: Self-Refresh, Self-Refresh.

SRX: Self-Refresh Exit, Self-Refresh Exit.

SRE: Self-Refresh Entry.

PDE: and entering a Power Down Entry mode of the interface.

PDX: and the Power Down Exit mode of the interface exits.

PA, Protocol Analyzer, test unit 20.

NOP: no operation, no operation instruction.

CLK: the clock at which the SDRAM operates.

CKE: a clock enable signal.

1N mode: 1N Mode, CA samples every clock cycle.

2N mode: 2N Mode, CA samples every two clock cycles.

As shown in fig. 1, which is a schematic structural diagram of a chip module 1 according to an embodiment of the present disclosure, the chip module 1 includes: the test device comprises a module to be tested 10 and a test device 20, wherein the module to be tested 10 is connected with the test device 20, and the test device 20 is used for performing interface signal time sequence test on the module to be tested 10.

In one embodiment, the testing device 20 may be embedded in the chip module 1.

In one embodiment, the testing device 20 can also perform a protocol test on the input interface signal of the module under test 10 in the external circuit mode independently of the chip module 1.

In an embodiment, the chip module 1 may be a DDR5 SDRAM, and the interface protocol of the module to be tested 10 may be RDIMM or UDIMM interface protocol.

In an embodiment, taking DDR5 SDRAM chipset 1 as an example, the SRX command of DDR5 is complex and is a command sequence. The input interface SRX command sequence of the SDRAM of UDIMM is as follows: first the CS jumps up from low to high, then maintains the CS high for a time tCSH (fixed minimum allowed 13ns, maximum allowed 30ns, noted tCSH), then the CS pulls down for a period of time and sends a continuous NOP command that is a minimum of 3 SDRAM clock cycles and no more than 30ns at maximum (noted tCSL), then the CS jumps up to high and maintains, which is the SRX command sequence. The last segment of NOP may be a continuous NOP or a sequence with intervals of one beat CS with low NOP and one beat CS with high DES.

Whereas the input interface SRX exit for DDR5 RDIMM is slightly more complex than the UDIMM interface. UDIMM constitutes a memory module using only SDRAM arrays, with SDRAM and memory controller connected directly by 14 CA lines, so SRX retirement is a sequence defined by the DDR5 specification. The RDIMM is composed of an SDRAM granule array and RCD granules, a CA line of the SDRAM is connected with a QCA output of the RCD, and a CA input of the RCD is reduced to half of CA signal lines of the SDRAM, namely 7 lines, in order to save power consumption and increase the speed. The SRX exit command sequence of RDIMM requires that the RCD input IO first exit the low power state, then the output IO exit the low power state, and thereafter the command sequence timing requirements are the same as the SRX command sequence timing requirements of the SDRAM.

Specifically, when the RDIMM is in the SR state, there are two situations, one is a clock stop mode and one is a clock always-on mode. In the clock stop mode, after the SRE command, DCS is low after waiting for tcpd time, and the differential clock is pulled low or floated after waiting for tCKoff time. If the SR state needs to be exited, the SRX sequence is as follows, CS is pulled high first, after waiting for tCKACT time, the clock input is valid, and after waiting for tSTAB01 time, a CS low pulse is sent to open the output port IO of the RCD. During the time of tSTAB01, DCA [6:0] must remain high. After the second NOP command is sent, after the DCS keeps high signal time as tSRX2SRX (in the period of tSRX2SRX, DCA [6:0] only needs to be VALID, and does not need to be kept high), a continuous CS low or pulse CS low mode is sent on the DCS, and DCA [6:0] is kept high all the time. The continuous CS low or pulse CS low time is above 3 clock cycles and within 30ns, then CS is continuously pulled high, the SRX sequence of RDIMM is ended, and the DRAM particle can exit from the refresh state.

In addition, because the DDR5 CA command lines are reduced from 26 to 14 SDRAM and 7 RCD, and the capacity and addressing number are larger, the original single-cycle command of DDR4 needs to be sent by DDR5 through a single-cycle or double-cycle command. For RCD, the two-cycle command requires 2 falling edges at two rising edges of the RCD clock for 2 clock cycles in the 1N mode, i.e. the CA input signal of RCD operates in DDR mode. In 2N mode, a two-cycle command requires 4 DRAM clock cycles, the first half takes 2 clock cycles, and the second half takes 2 clock cycles to ensure adequate setup and hold time for CA sampling, and the RCD input requires 4 clock cycles to sample 4 times on the rising edge for a total of 28-bit CA.

Due to the high transfer rate of the DDR5, signal integrity is greatly challenged, the command protocol is complex, and for testing the DDR5, it is necessary to test the signal timing of the DDR5 so as to test that the command sequence sent by the chip controller meets the protocol specification of the DDR 5.

Because the DDR5 cancels the CKE which is a signal line for controlling the low power consumption mode of the DRAM, the original four low power consumption mode entering and exiting commands of the SRE (self-refresh entering), the SRX (self-refresh exiting), the PDE (interface power down mode entering) and the PDX (interface power down mode exiting) on the DDR4 are decoded by the CKE/CS, and are changed into the low power consumption entering and exiting command or command sequence which is formed by decoding the CS (chip select signal) and the CA (address control signal line) on the DDR 5.

Based on the above principle, please refer to fig. 2, which is a testing apparatus 20 according to an embodiment of the present application, including: a first collector 21, a signal processor 22, a second collector 23, a timing detector 24, and a state machine 25, wherein:

the first collector 21 is configured to collect a chip select signal of the interface of the module 10 to be tested. The interface of the module under test 10 may be an RDIMM interface or a UDIMM interface.

And the signal processor 22 is connected to the first collector 21 and configured to perform stretching processing on the chip selection signal to generate a stretched chip selection signal.

And the second collector 23 is configured to collect an address control signal of the interface of the module 10 to be tested.

And the timing detector 24 is respectively connected to the first collector 21, the signal processor 22 and the second collector 23, and is configured to detect timing information of the chip select signal, the address control signal and the extended chip select signal.

And the state machine 25 is connected with the timing detector 24 and used for verifying whether the timing information meets the preset timing rule.

The testing device 20 respectively collects chip selection signals and address control signals through two collectors, widens the CS signal lines through the signal processor 22, and realizes that one set of circuit simultaneously carries out time sequence inspection on CS and CA sequences based on the processing.

In an embodiment, please refer to fig. 3, which is a testing apparatus 20 according to an embodiment of the present application, the first collector 21 includes: the chip selection signal interface 211 is connected with a chip selection signal pin of the interface of the module to be tested 10 and is connected with an initial chip selection signal, and the first sampling register 212 is connected with the chip selection signal interface 211. The first sampling register 212 is connected to the chip select signal interface 211, and is configured to sample an initial chip select signal to obtain a chip select signal. The first sampling register 212 may be a CS sampling flip-flop.

In one embodiment, the testing device 20 may further include: and the clock detection circuit 26 is respectively connected with the interface of the module to be detected 10 and the state machine 25 and is used for detecting the clock signal of the interface of the module to be detected 10. The clock signal line of the interface of the module to be tested 10 can be connected through the clock detection circuit 26, and the clock sampling result of the CS signal is obtained by using the input clock of the clock signal line as the clock. In the actual scenario, CS is low for NOP no-operation command, and CS is high for DES deselect command.

In one embodiment, the signal processor 22 may include: a first delayer 221 and a logical and gate 222, wherein:

the first delay 221 is connected to the first collector 21, and is configured to delay the chip select signal and generate a chip select delayed signal. For example, the first delay 221 may be a flip-flop that generates the chip select delay signal CS _ dly after delaying the input CS signal by one clock cycle.

And a logic and gate 222, respectively connected to the first collector 21 and the first delayer 221, for performing a logic and operation on the chip selection signal and the chip selection delay signal to generate a widened chip selection signal, that is, generating a widened chip selection signal CS _ op by performing a logic and operation on CS and CS _ dly. The output of the logical and gate 222 may be: stretch the continuous low CS signal by one beat (one clock cycle), and convert the pulsed CS to a continuous CS low signal.

In one embodiment, the timing detector 24 may further include: the pattern detection circuit 241 is connected to the first delay 221, and is configured to detect a current signal change pattern of the chip select delay signal. The signal variation pattern of the chip select delay signal may be a continuous CS pattern, or a pulsed CS pattern. The pattern detection circuit 241 may include a 2-bit counter, and when the tCSH (duration of high level of the CS signal) timing satisfies a predetermined timing condition and the CS is low, the count result of the counter is increased by 1, and when the CS is high and the count result is greater than 0, the count result of the counter is decreased by 1. If the counting result is 2 hours, the counting is finished, at this time, the current signal change mode of the chip selection delay signal is a continuous CS low mode, otherwise, the current signal change mode of the chip selection delay signal is a pulse type CS.

In one embodiment, the timing detector 24 may include: the low level time detection circuit 242 is connected to the logic and gate 222, and configured to detect whether the low level duration of the slice selection signal is within a preset duration, and send a prompt message when the low level duration of the slice selection signal is not within the preset duration. The preset duration may be a duration specified in the chip specification, that is, the low level time detection circuit 242 takes the output result of the logic and gate 222 as an input to detect whether the CS is low or the CS time of the pulse meets the specification requirements.

In one embodiment, the low time detection circuit 242 is a duration detection circuit with CS in continuous low mode or impulse type low and high continuous mode, and can count according to the low time of the input signal, and its counting end time depends on the input signal and timeout, if the input signal is high, or the counting exceeds the allowed maximum time, the counting is terminated. If the count exceeds the maximum time allowed, an error is reported and an error message is recorded.

In one embodiment, the low time detection circuit 242 may also report an error when the count exceeds the maximum time and continue counting until CS is high or the counter reaches the maximum threshold.

In one embodiment, the low-level time detection circuit 242 checks the low-level duration of the stretched chip select signal as follows:

and 1, reporting an error when the counting result is less than 4 and the current input signal is high, and recording the error type as not meeting the minimum time tCSL.

And 2, when the counting result is equal to 4 and the counting result of the counter of the mode detection circuit 241 is 0, indicating that the current signal change mode of the chip selection delay signal is the pulse mode CS, but only corresponding to 2 NOP signals, failing to meet the minimum 3 NOP commands required in the specification, reporting an error, and recording the error type as failing to meet the minimum time tCSL.

And 3, calculating a maximum threshold U of the counting result according to the configuration frequency f and the 30ns absolute time of the actual module to be measured 10, wherein U is f × 30 ns. When the count exceeds a maximum threshold U, it represents a maximum time over tCSL (duration of CS low), an error is reported, and the error type is recorded as the maximum time over tCSL.

4, if the counting result of the low level time detection circuit 242 is within the range defined by 4 to U +1 and the maximum threshold U is 30ns corresponding to the rounded-down count value of the configuration frequency f, the timing check is passed.

In one embodiment, the second collector 23 includes: an address control line interface 231 and a second sampling register 232, wherein the address control line interface 231 is connected to an address command line pin of the interface of the module to be tested 10 and receives an initial address command signal. The second sampling register 232 is connected to the address control line interface 231, and is configured to sample the initial address command signal to obtain an address control signal. The second sampling register 232 may be a CA sampling flip-flop. In an embodiment, the clock sampling result of the CA signal may be obtained by connecting a clock signal line of the interface of the module to be tested 10 and using the input clock of the clock signal line as a clock.

In one embodiment, the timing detector 24 includes: and a continuous high detection circuit 243 connected to the second collector 23 for detecting whether the address control signal meets the preset high level, and sending a prompt message when the address control signal does not meet the preset high level. The continuous high detection circuit 243 is used to detect whether the CA input signal is constantly high.

In one embodiment, the predetermined high level may be a requirement in the specification, assuming the detection rule is as follows: the CA signal needs to be constantly high during SRX state detection. In the SR state, and after the CS transition is high, when the interface of the module 10 to be tested is the UDIMM type, the 14-bit CA is always all 1 in each clock cycle. When the interface of the module 10 under test is of the RDIMM type, the 7-bit CA is always all 1's in each clock cycle. If the above rules are violated, an error is reported and recorded. Particularly, for the tSRX2SRX time sequence period of the RDIMM, if the CA [6:0] full-high mode is set for detection, the detection is carried out according to the mode; if no detection is set, then no full high detection of the level signal is made during this period, to accommodate CA [6:0] being only the active level mode during tSRX2 SRX.

In one embodiment, the detection rule may further be as follows: for CS low, it may be sufficient only to detect NOP commands, whose presence only requires: the CA [4:0] signal is full high and the CA [13:5] signal of the SDRAM is negligible.

In one embodiment, the timing detector 24 includes: the high time detection circuit 244 is connected to the first delay 221 and is used for detecting the time when the chip select delay signal maintains the high level. The high time detector circuit 244 is a tSTAB01 time and tCSH time detector circuit. When the module under test 10 interface is of the UDIMM type, only the tCSH detection is performed under the control of the state machine 25. When the interface of the module 10 to be tested is of RDIMM type, under the control of the state machine 25, in the clock stop mode, both tSTAB01 detection is performed, and after 1NOP is received subsequently, tcsh (tsrxrx) detection is performed; when the clock is in the normally-on mode, after 1NOP is received, the tCSH (tSRXSRX) detection is executed. The circuit is mainly a counting circuit, and the counting result is compared with a preset configuration value to judge whether the preset time sequence requirement is met. The pre-configured value is calculated according to the clock frequency and the absolute time.

In one embodiment, the testing device 20 may further include: the status register 245 is connected to the timing detector 24, and is used for triggering the timing detector 24 to start detection when the module 10 to be detected is in the self-refresh state. The status register 245 is an SR status register 245 that executes the SRX detection circuitry logic of the test apparatus 20 only when in the SR state.

In one embodiment, the testing device 20 may further include: the module type register 246 is connected to the test state machine 25, and is used for sending the module type information of the interface of the module 10 to be tested to the state machine 25. The register 246 is a DIMM type register, and the type of interface of the module 10 to be tested can be externally configured, such as configuring the DIMM to be of the RDIMM type or the UDIMM type, to determine which logic circuits need to be executed.

In one embodiment, the idle operation command detection circuit 247 is respectively connected to the signal processor 22 and the state machine 25 for detecting whether the idle operation command is received. When the interface of the module 10 to be tested is RDIMM type, the idle operation command detection circuit 247 is turned on. And a no-operation command detection circuit 247 respectively connected to the logic and gate 222 and the state machine 25, wherein in the RDIMM mode, since the input CS is the output from the logic and gate 222, when the CS is at a low level within two clock cycles, it indicates that a 1NOP command is received, otherwise, if the time of the CS low level is greater than 2 clock cycles, an error is reported and recorded.

In an embodiment, the state machine 25 is respectively connected to the high-level time detection circuit 244, the mode detection circuit 241, the low-level time detection circuit 242, and the high-duration detection circuit 243, and is configured to verify whether the timing information conforms to a predetermined timing rule according to the timing information reported by the high-level time detection circuit 244, the mode detection circuit 241, the low-level time detection circuit 242, and the high-duration detection circuit 243.

In one embodiment, the state machine 25 determines whether the SRX timing sequence meets the specification according to the detection information reported by the detection circuits, and if not, reports error result information. The state machine 25 can also control the execution of the above-described detection circuits and the corresponding detection range values.

In practical applications, the SRX exit time point in the continuous CS mode and the SRX exit time point in the pulse CS mode are determined in advance and used as the basis for timing detection. Since the DDR5 specification is ambiguous about the definitions of the two modes, the description of the timing diagram remains uncertain. Different DDR drivers (vendors) may take different ways to act as SRX exit points, such as receiving 3 consecutive NOPs or 3 consecutive pulses NOP as exit time points. The specification can be taken as a design criterion, and the circuit realization rationality is considered, for the continuous CS mode, the SRX exit time point is taken as the time point when the CS is high, and for the impulse CS mode, the SRX exit time point is taken as the time point when the CS is two high and is the DES command. Of course, the vendor may also fix two consecutive DES commands as the tCSL time checkpoint and the SRX exit time checkpoint.

In one embodiment, for example, CS goes high in the continuous CS mode as the SRX exit time point, and two DES commands in the pulse CS mode are the SRX exit time points. The low level time detection circuit 242 is the SRX exit point in the pulsed CS mode when CS is high. And the SRX exit point of time for the continuous CS low mode is to subtract 1 clock cycle from the current time that CS is high.

In one embodiment, the continuous CS low mode or the pulsed CS mode may be determined by a counter of the mode detection circuit 241. If the count result is 0, the mode is the pulse CS mode, and if the count result is greater than 1, the mode is the continuous CS low mode.

The test apparatus 20 delays the CS signal line by one beat to generate a signal CS _ dly, generates a CS _ op by a logical and operation of CS and CS _ dly, and decodes and checks a timing of the CS _ op and a CA sequence, thereby supporting the SRX command decoding and timing check of 4 different DIMM types and different CS pulse types. Thereby speeding up the test speed and problem location. The method can be applied to a protocol analyzer circuit of the silicon post-verification and can also be applied to a functional verification environment of front-end simulation.

In an embodiment, please refer to fig. 4, which is a testing apparatus 20 according to an embodiment of the present application, further including:

and the input end of the decoder 26 is connected with the first collector 21 and the second collector 23 respectively, and the output end of the decoder is connected with the signal processor 22 and is used for decoding the chip selection signal and the address control signal to generate a decoding signal. In the actual scenario, CS is low and CA [4:0] full high is a NOP no operation command, and CS is high is a DES deselect command. The chip select signals and the commands related to the address control signals may be decoded, such as decoding the generated signal NOP _ sig separately for NOP commands and DES _ sig separately for DES commands.

In one embodiment, the signal processor 22 includes: the second delay 248 is connected to the decoder 26 for delaying the decoded signal to generate a decoded delayed signal. The or gate 249 is connected to the decoder 26 and the second delay 248, respectively, and is configured to perform a logical or operation on the decoded signal and the decoded delayed signal to generate a stretched decoded signal. For example, nop _ sig is delayed by 1T to generate nop _ sig _ dly, and nop _ sig _ dly are used as logic or to generate nop _ sig _ op.

In one embodiment, the timing detector 24 further includes: the first counter 2410 is respectively connected to the decoder 26 and the or gate 249, and is configured to count a deselected command in the decoded signal as a high level to obtain first count information, where the timing information includes the first count information. For example, when Nop _ sig _ op is high, Nop _ sig is counted, and when the clock rising edge sampling Nop _ sig is high, Nop _ sig _ ctr is incremented by 1.

In one embodiment, the first counter 2410 is connected to the state machine 25, and the state machine 25 is further configured to control an enable state of the first counter 2410. I.e., the state machine 25 controls the counting and clearing of the first counter 2410.

In one embodiment, the timing detector 24 further includes: the second counter 2411, connected to the decoder 26, is configured to count that the no operation command in the decoded signal is at a high level, so as to obtain second count information, where the timing information includes the second count information. For example, when Des _ sig is counted and the clock rising edge sample Des _ sig is high, Des _ sig _ ctr is incremented by 1.

In one embodiment, the second counter 2411 is connected to the state machine 25, and the state machine 25 is further configured to control the enabling state of the second counter 2411. I.e., the state machine 25 controls the counting and clearing of the second counter 2411.

In an embodiment, the state machine 25 is respectively connected to the first counter 2410 and the second counter 2411, and is configured to verify whether the timing information meets a predetermined timing rule according to the first count information and the second count information. For example, after the SR state and the tCSH time satisfy the preset timing condition, the decoding and counting process is started, and the state machine 25 obtains the detection information and performs verification according to the following rule: if nop _ sig _ ctr is greater than or equal to 3 and less than or equal to 30ns corresponding clock cycles, and des _ sig _ ctr is equal to 1, which is the SRX exit time point of the continuous CS low mode, the first counter 2410 and the second counter 2411 are cleared. If nop _ sig _ ctr is greater than or equal to 3, des _ sig _ ctr is equal to nop _ sig _ ctr, des _ sig _ ctr is less than or equal to 15ns of the corresponding clock period number, and the current des _ sig is 1, it is the SRX exit time point of the pulse CS. If the SRX signal timing sequence does not meet the requirement of the predetermined timing sequence rule, the SRX signal timing sequence does not meet the requirement of the predetermined timing sequence rule.

In an embodiment, the clock detection circuit 26 is further configured to detect a shutdown state of a clock signal of the interface of the module under test 10.

In an embodiment, the state machine 25 may include an IDLE state (debug state), a TSTAB state, a tCSH detect state, and a SRX determine state, and the operation principle of the state machine 25 in each state is as follows:

IDLE state: if the SR state bit is true (1) and the error state is false (0), if the interface of the module to be tested 10 is of RDIMM type, the clock detection circuit 26 detects that the clock has been turned off in the SR state, and the state machine 25 enters the TSTAB detection state; if the interface of the module 10 to be tested is RDIMM type, the clock detection circuit 26 does not detect that the clock is turned off, and when the NOP command is detected, the state machine 25 enters the tCSH detection state; if the interface of the test module 10 is of the UDIMM type, and a DES command is detected, the state machine 25 enters the TCSH detection state.

TSTAB state: the high time detection circuit 244 is enabled, and the high time detection circuit 244 is provided with a high counter, in which state the state machine 25 enters the TCSH detection state when the NOP command is detected and the high count time is within the allowable range of tSTAB, i.e., within the corresponding clock cycle range of tSTAB. While clearing the high time counter. If a NOP command is detected and the high level count time is outside the tSTAB allowed range, or the high level count time exceeds the tSTAB maximum value, the state machine 25 reports a tSTAB detection error, and records the high level count value, returning to the IDLE state.

TCSH detection status: the first counter 2410(NOP counter) is enabled, and the high time detection circuit 244 is enabled. This state detection CS is high, i.e. it is verified whether tSRX2SRX at the time of the DES command in RDIMM interface type or tCSH at the time of the UDIMM interface type meets the timing configuration. And entering a TCSL detection state if the high-level time counter meets the configuration range when the NOP command is detected. If the high level counter is not in the tCSH configuration range when the NOP command is detected, or the high level counting time exceeds the maximum tCSH value, the state machine 25 reports an error, records the high level time, and the state machine 25 enters an IDLE state.

TCSL detection state: the first counter 2410(NOP counter) is enabled, and the second counter 2411(DES counter) is enabled. If nop _ sig _ op is not 1, the state machine 25 enters an SRX determination state and determines whether the current CS mode is the continuous CS mode or the pulse CS mode, the determination principle being: if DES count is less than or equal to 2, it is the continuous CS mode, otherwise, if DES count result is greater than or equal to NOP count result, it is the pulse CS mode. In this state, as long as the sum of the NOP count result and the DES count result is greater than the maximum allowable clock configuration, the state machine 25 reports an error, records error information, and returns to the IDLE state.

SRX judges the state: if the NOP counting result is less than 3, the state machine 25 reports an error and returns to the IDLE state; if the sum of the NOP count result and the DES count result is greater than the maximum allowed clock configuration, the state machine 25 reports an error and returns to the IDLE state. If the sum of the NOP counting result and the DES counting result is within the configuration interval, the state machine 25 returns to the IDLE state, marks the detection success, and sets the SR state to 0; otherwise, the flag detects an error and records the count result.

Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope defined by the appended claims.

Claims

1. A test apparatus, comprising:

the first collector is used for collecting chip selection signals of the interface of the module to be detected;

the signal processor is connected with the first collector and used for widening the chip selection signal to generate a widened chip selection signal;

the second collector is used for collecting the address control signal of the module interface to be detected;

the time sequence detector is respectively connected with the first collector, the signal processor and the second collector and is used for detecting the time sequence information of the chip selection signal, the address control signal and the widened chip selection signal;

and the state machine is connected with the time sequence detector and used for verifying whether the time sequence information meets a preset time sequence rule or not.

2. The apparatus of claim 1, wherein the signal processor comprises:

the first delayer is connected with the first collector and used for delaying the chip selection signal and then generating a chip selection delay signal;

and the logic AND gate is respectively connected with the first collector and the first delayer and is used for performing logic AND operation on the chip selection signal and the chip selection delay signal to generate the widened chip selection signal.

3. The apparatus of claim 2, wherein the timing detector comprises:

and the high level time detection circuit is connected with the first delayer and used for detecting and obtaining the time for maintaining the high level of the chip selection delay signal.

4. The apparatus of claim 3, wherein the timing detector comprises:

and the mode detection circuit is connected with the first delayer and used for detecting and obtaining the current signal change mode of the chip selection delay signal.

5. The apparatus of claim 4, wherein the timing detector comprises:

and the low level time detection circuit is connected with the logic AND gate and is used for detecting whether the low level duration of the widening chip selection signal is within a preset duration or not and sending out prompt information when the low level duration of the widening chip selection signal is not within the preset duration.

6. The apparatus of claim 5, wherein the timing detector comprises:

and the continuous high detection circuit is connected with the second collector and is used for detecting whether the address control signal accords with a preset high level or not and sending prompt information when the address control signal does not accord with the preset high level.

7. The apparatus according to claim 6, wherein the state machine is respectively connected to the high level time detection circuit, the mode detection circuit, the low level time detection circuit and the high duration detection circuit, and configured to verify whether the timing information complies with a preset timing rule according to the timing information reported by the high level time detection circuit, the mode detection circuit, the low level time detection circuit and the high duration detection circuit.

8. The apparatus of claim 1, further comprising:

and the input end of the decoder is respectively connected with the first collector and the second collector, and the output end of the decoder is connected with the signal processor and is used for decoding the chip selection signal and the address control signal to generate a decoding signal.

9. The apparatus of claim 8, wherein the signal processor comprises:

the second delayer is connected with the decoder and used for delaying the decoding signal and then generating a decoding delayed signal;

and the logic OR gate is respectively connected with the decoder and the second delayer and is used for carrying out logic OR operation on the decoding signal and the decoding delay signal to generate a stretched decoding signal.

10. The apparatus of claim 9, wherein the timing detector further comprises:

and the first counter is respectively connected with the decoder and the logic OR gate and is used for counting the deselected command in the decoded signal to be high level to obtain first counting information, and the time sequence information comprises the first counting information.

11. The apparatus of claim 10, wherein the timing detector further comprises:

and the second counter is connected with the decoder and is used for counting the idle operation command in the decoded signal to be high level to obtain second counting information, and the time sequence information comprises the second counting information.

12. The apparatus according to claim 11, wherein the state machine is respectively connected to the first counter and the second counter, and configured to verify whether the timing information complies with a preset timing rule according to the first count information and the second count information, and control an enable state of the first counter and the second counter.

13. The apparatus of claim 1, further comprising:

and the state register is connected with the time sequence detector and is used for triggering the time sequence detector to start detection when the module to be detected is in a self-refreshing state.

14. The apparatus of claim 1, further comprising:

and the module type register is connected with the state machine and used for sending the module type information of the module to be tested to the state machine.

15. The apparatus of claim 1, wherein the first collector comprises:

the chip selection signal interface is connected with a chip selection signal pin of the module interface to be tested and is accessed to an initial chip selection signal;

and the first sampling register is connected with the chip selection signal interface and is used for sampling the initial chip selection signal to obtain the chip selection signal.

16. The apparatus of claim 1, wherein the second collector comprises:

the address control line interface is connected with an address command line pin of the module interface to be tested and is accessed to an initial address command signal;

and the second sampling register is connected with the address control line interface and is used for sampling the initial address command signal to obtain the address control signal.

17. The apparatus of claim 1, further comprising:

and the idle operation command detection circuit is respectively connected with the signal processor and the state machine and is used for detecting whether an idle operation command is received.

18. The apparatus of claim 1, further comprising:

and the clock detection circuit is respectively connected with the module interface to be detected and the state machine and is used for detecting the shutdown state of the clock signal of the module interface to be detected.

19. A chip module, comprising: the test device of any one of claims 1 to 18;

and the module to be tested is connected with the testing device, and the testing device is used for carrying out signal time sequence testing on the interface of the module to be tested.