CN105760322A - Multi-target high-speed debug circuit - Google Patents
Multi-target high-speed debug circuit Download PDFInfo
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- CN105760322A CN105760322A CN201610113098.0A CN201610113098A CN105760322A CN 105760322 A CN105760322 A CN 105760322A CN 201610113098 A CN201610113098 A CN 201610113098A CN 105760322 A CN105760322 A CN 105760322A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/38—Universal adapter
- G06F2213/3852—Converter between protocols
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- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
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Abstract
The invention provides a multi-target high-speed debug circuit which comprises a multi-core CPU system, a time information unit, a time information control unit, a debug information acquisition unit, an ATB protocol conversion unit, an ATB mixing unit, an interface control unit, a configuration bus and a protocol analysis unit.The time information unit carries time information for each CPU and each cache circuit of the multi-core CPU system, and debug information is derived to observable IO of a chip through the debug information acquisition unit, the ATB protocol conversion unit, the ATB protocol conversion unit, the ATB mixing unit and the interface control unit in sequence.The protocol analysis unit controls all the modules through the configuration bus.Information interaction output between the multi-core CPUs arranged in an interaction mode in the multi-core CPU system can be achieved; meanwhile, besides an instruction pointer, processed output and CPU states can be printed in real time, and the requirements for the current high-performance soc chips developing at a high speed can be completely met.
Description
Technical field
The present invention relates to a kind of SOC, particularly to the high speed debug circuit of a kind of SOC.
Background technology
Along with the fast development of SOC technology, the CPU speed of service is increasingly faster, and the debug of chip is had higher requirement.
In traditional design, owing to chip is overall relatively simple and debug has only to arrange breakpoint and print debug pointer information, but the design being as chip complicates, performance and the speed of service are also more and more higher, traditional debug method for designing can not meet the demand of high-performance soc chip, speed is too slow, and the information of printing is very little, it is therefore desirable to improve further.
Summary of the invention
The technical problem to be solved in the present invention, it is in that to provide a kind of multiobject high speed debug circuit, the information arranged alternately between multinuclear cpu that can realize between multinuclear cpu exports alternately, simultaneously except instruction pointer, it is also possible to the output of real time print process and cpu state. the demand of the high-performance soc chip of current high speed development can be met completely.
The present invention is achieved in that a kind of multiobject high speed debug circuit, including a multi-core CPU system, a plurality of temporal information unit, a time information control unit, a plurality of debug information acquisition unit, a plurality of ATB protocol translation unit, an ATB mixed cell, an interface control unit, configuration bus and protocol analysis unit；
Described multi-core CPU system includes a plurality of CPU and one's cache circuit, and each CPU and cache circuit connects temporal information unit described in one and a debug information acquisition unit respectively；
Described temporal information control unit connects a plurality of temporal information unit, ATB mixed cell and interface control unit respectively；
Described a plurality of debug information acquisition unit is all corresponding connects an ATB protocol translation unit, and described a plurality of ATB protocol translation unit are sequentially connected to the Observable IO of chip each through described ATB mixed cell and interface control unit；
Described protocol analysis unit connects described a plurality of temporal information unit, described a plurality of debug information acquisition units, described ATB mixed cell and described interface control unit respectively by described configuration bus.
Wherein, described multi-core CPU system, a plurality of temporal information unit, temporal information control unit, a plurality of debug information acquisition unit, ATB protocol translation unit, ATB mixed cell, interface control unit, configuration bus and protocol analysis unit may be contained within the inside of chip；
The outside of described chip is additionally provided with an ATB and solves mixed cell and a plurality of ATB protocol analysis unit, the Observable IO of described chip solves mixed cell by this ATB and is respectively connecting to a plurality of ATB protocol analysis unit, and these a plurality of ATB protocol analysis unit are connected to computer.
Further, present invention additionally comprises other modules, other modules described are gpu or video_decoder, and these other modules pass sequentially through a time information unit, a debug information acquisition unit is connected to ATB protocol translation unit.
Present invention have the advantage that the mutual information arranged between multinuclear cpu that the present invention can realize between multinuclear cpu exports alternately, simultaneously except instruction pointer, can also real time print process output and cpu state, cache data derivation in real time etc. the demand of the high-performance soc chip of current high speed development can be met completely.
Accompanying drawing explanation
The present invention is further illustrated in conjunction with the embodiments with reference to the accompanying drawings.
Fig. 1 is the theory structure block diagram of high speed debug circuit of the present invention.
Detailed description of the invention
As shown in Figure 1, the multiobject high speed debug circuit of the present invention, including a multi-core CPU system 100, a plurality of temporal information unit 101, time information control unit 102, a plurality of debug information acquisition unit 103, a plurality of ATB protocol translation unit 104, ATB mixed cell 105, interface control unit 106, configuration bus 107 and a protocol analysis unit 108；
Described multi-core CPU system 100 includes a plurality of CPU and one's cache circuit, and each CPU and cache circuit connects temporal information unit 101 and a debug information acquisition unit 103 described in one respectively；
Described temporal information control unit 102 connects a plurality of temporal information unit 101, ATB mixed cell 105 and interface control unit 106 respectively；
Described a plurality of debug information acquisition unit 103 is all correspondingly connected to an ATB protocol translation unit 104, and described a plurality of ATB protocol translation unit 104 are sequentially connected to the Observable IO of chip each through described ATB mixed cell 105 and interface control unit 106；
Described protocol analysis unit 108 connects described a plurality of temporal information unit 101, described a plurality of debug information acquisition units 103, described ATB mixed cell 105 and described interface control unit 106 respectively by described configuration bus 107.
Wherein, described multi-core CPU system 100, a plurality of temporal information unit 101, temporal information control unit 102, a plurality of debug information acquisition unit 103, ATB protocol translation unit 104, ATB mixed cell 105, interface control unit 106, configuration bus 107 and protocol analysis unit 108 may be contained within the inside of chip；
The outside of described chip is additionally provided with an ATB and solves mixed cell 201 and a plurality of ATB protocol analysis unit 202, the Observable IO of described chip solves mixed cell 201 by this ATB and is respectively connecting to a plurality of ATB protocol analysis unit 202, and these a plurality of ATB protocol analysis unit 202 are connected to computer.
Wherein,
Described temporal information unit 101 is for producing the debug object that temporal information is sent to the free each other relation of correspondence, including CPU, cache, interface control unit 106；And when collecting each action of CPU corresponding temporal information be sent to temporal information control unit 102 do debug sequencing control；
Described temporal information control unit 102, for controlling coordinate the sequencing of each temporal information unit 101 and control the output priority of interface control unit 106；
In described multi-core CPU system 100, each CPU can be independently executing programs, it is possible to multi-core parallel concurrent works, the temporal information that receiving time information unit 101 is sent here, and the priority carrying out debug behavior controls, and debug information derivation action；
Described cache circuit is to cooperate with the buffer memory of cpu work, it is possible to data derived by debug information acquisition unit 103；
Described debug information acquisition unit 103 is responsible for gathering the debug information of debug object, and is sent to ATB conversion unit of protocol 104；
Described ATB conversion unit of protocol 104, after the debug inter-area traffic interarea receiving each debug source, is converted into ATB protocol data-flow, and by each data streaming of ATB agreement toward ATB mixed cell 105；
Described ATB mixed cell 105 is responsible for multiple ATB data streams are synthesized road ATB data, and is sent to interface control unit 106；
Described interface control unit 106 is according to configuration output debug information；
Described jtag protocol analysis unit 108 is responsible for that jtag agreement transfers to apb and is configured bus protocol, then passes through apb and controls each module in debug system；Its jtag is the boundary scan agreement of standard, it is possible to control all of module by protocol analysis unit 108.
The present invention may also include other modules 109, other modules 109 described are other modules outside cpu, for modules such as gpu or video_decoder, these other modules 109 are connected to ATB protocol translation unit by a debug information acquisition unit 103, to be derived by 103 debug information of debug information acquisition unit.
The workflow of the present invention:
(1), after circuit powers on and enter debug pattern, described jtag protocol analysis unit 108 configures bus 107 by jtag Interface Controller apb and all of temporal information unit 101 and temporal information control unit 102 is initialized；The priority of CPU is set, the output priority of interface control unit 106 is set simultaneously, the priority break point between multi-core CPU is set；Configuration debug information acquisition unit 103；
(2), after cpu starts working, each CPU is once occur that program pointer changes, or read-write operation, corresponding CPU monitor (DEBUG information acquisition unit 103) will gather once the debug information of this CPU, the debug information of corresponding CPU, including running pointer, run contents of program, read the value with write data, and it is sent to DEBUG information acquisition unit 103. together with the temporal information value sent here with temporal information generation unit simultaneously, the DEBUG information acquisition unit 103. of correspondence also can be sent in corresponding address and new data by each internal data change of cache
(3), temporal information unit 101 can produce temporal information and be sent to CPU, the temporal information of each for CPU action can be sent to temporal information control unit 102, it is possible to realize following functions simultaneously:
A) produce temporal information to CPU, allow each CPU behavior can bring temporal information when producing debug information data, can obtain, during to ensure in the end to export reduction debug information, the precedence information that between multinuclear, each instruction performs；
B) when the priority break point debug constraint that the priority arranged between multi-core CPU performs, the CPU that the CPU wait that priority performs to perform after in the CPU of constraint above performs is allowed after completing instruction, to start the execution of subsequent instructions again；Particularly as follows:
There is no that time of receipt (T of R) information control unit 102 sends here first carry out cpu instruction complement mark before, the CPU of rear execution is complete instruction and performs, then can halt instruction operation go to wait flag information, until first carrying out after cpu instruction completes, the CPU first carrying out instruction is completed the mark of instruction and is sent to temporal information control unit 102 by temporal information unit 101, in those CPU that temporal information control unit 102 performs after being distributed to by mark again, it is allowed to start to perform subsequent instructions；
C) debug information data excessive want save debug data bandwidth, or user without wishing to derive some debug source information time, ATB mixed cell 105 can be controlled by temporal information control unit 102 and corresponding passage is not carried out ATB married operation, thus realizing shielding certain debug source data. can also arrange the time period of shielding, according to the temporal information of temporal information unit 101, ATB mixed cell 105 can judge that whether temporal information that shielding passage is corresponding decides whether in the time period to assess this passage arranging simultaneously；
(4), after DEBUG information acquisition unit 103 receives all debug information, according to configuration, information package is sent to ATB conversion unit of protocol 104 and transfers ATB protocol data to；By temporal information during data packing, run pointer, operation program, data of reading, write the information such as data and pack according to configuration; if configuring some data not pack, these data not being done packing and processes. such as reading data during configuration operation and write data and do not pack, then the data after packing do not comprise and read data and write data. and can carry out data confidentiality protection according to user's request by this mode and save the target of debug data bandwidth；
(5), a plurality of ATB conversion unit of protocol 104 be sent to ATB mixed cell 105 again and mix, mixing time can according to temporal information control unit 102 arrange closing passage and the closing passage time period by shielding passage ATB information be not mixed in final debug data stream；
(6), debug data stream can export according to the control of temporal information control unit 102; temporal information control unit 102 can by configuring the time period controlling output; namely do not carry out debug information output in some time period, key message protection can be carried out in key instruction or program segment when performing according to user's request by this mode；
(7), after debug information pio chip, the external circuit board is by connecting solution mixed cell 201 and the ATB protocol analysis unit 202 of ATB, linking the debug information pool in computer memory, then debug software can will be analyzed for staff in the content real-time update of the debug information pool of each CPU to display screen.
Claims (3)
1. a multiobject high speed debug circuit, it is characterised in that: include a multi-core CPU system, a plurality of temporal information unit, a time information control unit, a plurality of debug information acquisition unit, a plurality of ATB protocol translation unit, an ATB mixed cell, an interface control unit, configuration bus and a protocol analysis unit；
Described multi-core CPU system includes a plurality of CPU and one's cache circuit, and each CPU and cache circuit connects temporal information unit described in one and a debug information acquisition unit respectively；
Described temporal information control unit connects a plurality of temporal information unit, ATB mixed cell and interface control unit respectively；
Described a plurality of debug information acquisition unit is all corresponding connects an ATB protocol translation unit, and described a plurality of ATB protocol translation unit are sequentially connected to the Observable IO of chip each through described ATB mixed cell and interface control unit；
Described protocol analysis unit connects described a plurality of temporal information unit, described a plurality of debug information acquisition units, described ATB mixed cell and described interface control unit respectively by described configuration bus.
2. the multiobject high speed debug circuit of one according to claim 1, it is characterised in that: described multi-core CPU system, a plurality of temporal information unit, temporal information control unit, a plurality of debug information acquisition unit, ATB protocol translation unit, ATB mixed cell, interface control unit, configuration bus and protocol analysis unit may be contained within the inside of chip；
The outside of described chip is additionally provided with an ATB and solves mixed cell and a plurality of ATB protocol analysis unit, the Observable IO of described chip solves mixed cell by this ATB and is respectively connecting to a plurality of ATB protocol analysis unit, and these a plurality of ATB protocol analysis unit are connected to computer.
3. the multiobject high speed debug circuit of one according to claim 1, it is characterized in that: also include other modules, other modules described are gpu or video_decoder, and these other modules pass sequentially through a time information unit, a debug information acquisition unit is connected to ATB protocol translation unit.
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| CN201610113098.0A CN105760322B (en) | 2016-02-29 | 2016-02-29 | A kind of high speed debug circuit of multiple target |
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| CN101770424A (en) * | 2010-01-05 | 2010-07-07 | 天津七一二通信广播有限公司 | Data acquisition and emulation system suitable for underlying protocol stack of digital communication terminal |
| CN204066120U (en) * | 2014-10-31 | 2014-12-31 | 成都朗锐芯科技发展有限公司 | A kind of FPGA based on CPLD chip encrypts and parameter configuring system |
| US9021306B2 (en) * | 2012-12-13 | 2015-04-28 | Apple Inc. | Debug access mechanism for duplicate tag storage |
| CN104991845A (en) * | 2015-06-24 | 2015-10-21 | 福州瑞芯微电子有限公司 | High-speed debug method and apparatus for multi-core chip |
| CN105068898A (en) * | 2015-06-24 | 2015-11-18 | 福州瑞芯微电子股份有限公司 | USB type-C high-speed debug method and device |
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2016
- 2016-02-29 CN CN201610113098.0A patent/CN105760322B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101770424A (en) * | 2010-01-05 | 2010-07-07 | 天津七一二通信广播有限公司 | Data acquisition and emulation system suitable for underlying protocol stack of digital communication terminal |
| US9021306B2 (en) * | 2012-12-13 | 2015-04-28 | Apple Inc. | Debug access mechanism for duplicate tag storage |
| CN204066120U (en) * | 2014-10-31 | 2014-12-31 | 成都朗锐芯科技发展有限公司 | A kind of FPGA based on CPLD chip encrypts and parameter configuring system |
| CN104991845A (en) * | 2015-06-24 | 2015-10-21 | 福州瑞芯微电子有限公司 | High-speed debug method and apparatus for multi-core chip |
| CN105068898A (en) * | 2015-06-24 | 2015-11-18 | 福州瑞芯微电子股份有限公司 | USB type-C high-speed debug method and device |
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Address after: 350000 building, No. 89, software Avenue, Gulou District, Fujian, Fuzhou 18, China Patentee after: Ruixin Microelectronics Co., Ltd Address before: 350000 building, No. 89, software Avenue, Gulou District, Fujian, Fuzhou 18, China Patentee before: Fuzhou Rockchips Electronics Co.,Ltd. |
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