The application be on September 6th, 2012, application No. is 201210327166.5, entitled " display surface the applying date
The divisional application of the patent application of plate and display device ".
Specific embodiment
Hereinafter with reference to correlative type, illustrate the display panel and display device according to present pre-ferred embodiments, wherein phase
Same element will be illustrated with identical reference marks.
A kind of display panel of present pre-ferred embodiments is an active matrix (active matrix) LCD display
Plate, and including a thin film transistor base plate 1, in this, the structure of thin film transistor base plate 1 is first discussed in detail.
It please refers to shown in Figure 1A, Figure 1B and Fig. 1 C, wherein Figure 1A is the schematic top plan view of thin film transistor base plate 1, Figure 1B
For the enlarged diagram of the region C of Figure 1A, and Fig. 1 C is the broken line B-B schematic cross-sectional view of Figure 1B.Need it is specifically intended that in order to
Facilitate explanation, the height of each element shown by Figure 1A to Fig. 1 C and the size relationship (ratio) of width are only to illustrate, not generation
The actual size relationship of table.
As shown in Figure 1A, thin film transistor base plate 1 can have multi-strip scanning line, multiple data lines and multiple pixel (Figure 1A
Only draw two scan lines and four data lines).Wherein, described in the scan line and the data line are formed in being staggered
Pixel array.The scan line can be made to be connected respectively when the scan line receives scan signal, and will corresponding every a line picture
One data-signal of element is sent to the pixel by the data line, makes display panel that can show picture.In Figure 1A, display
Data line be respectively in a broken line, but, others layout in, data line also with respectively be in a straight line or other.In addition, thin
Film transistor substrate 1 can more have a black-matrix layer BM, black-matrix layer BM to be set on scan line, to cover scanning
The region of line, and prevent the light leakage of pixel.Certainly, the opposite base in liquid crystal display panel also can be set in black-matrix layer BM
On plate, in this by taking black-matrix layer BM is set to thin film transistor base plate 1 as an example.
As shown in Figure 1 C, thin film transistor base plate 1 include a substrate S1, a thin film transistor (TFT) T, one first insulating layer 13,
One planarization layer 14, a second insulating layer 15, a pixel electrode layer 16 and community electrode layer 18.
Thin film transistor (TFT) T is set on substrate S1.On the implementation, substrate S1 can be the material of a light-permeable, for penetrating
Formula display device, e.g. glass, quartz or the like, plastic cement, rubber, glass fibre or other high molecular materials, preferably
Can be a borate alkali-free glass substrate (alumino silicate glass substrate).Substrate S1 also can be impermeable for one
The material of light, is used for self-luminous or reflective display, and e.g. metal-glass fiber composite plate, metal-ceramic is compound
Plate.
Thin film transistor (TFT) T has a grid G, a gate dielectric 11, a channel layer 12, a source S and a drain D.Grid
Pole G is set on substrate S1, and the material of grid G is made of metal (for example, aluminium, copper, silver, molybdenum or titanium) or its alloy
Single or multi-layer structure.Part can be used with grid G same layer and same manufacturing process transmitting the conducting wire of driving signal
Structure is electrical connected each other, such as scan line.Gate dielectric 11 is set in grid G, and gate dielectric 11 can be organic
Material is, for example, organo-siloxane compound or inorganic is, for example, silicon nitride, silica, silicon oxynitride, silicon carbide, oxidation
The multilayered structure of aluminium, hafnium oxide or above-mentioned material.Gate dielectric 11 need to completely cover grid G, and selectable portion or whole
Cover substrate S1.
12 position opposing gate G of channel layer is set on gate dielectric 11.On the implementation, channel layer 12 for example may include
Monoxide semiconductor.Wherein, oxide semiconductor above-mentioned includes oxide, and oxide include indium, gallium, zinc and tin wherein
One of, for example, indium gallium zinc (Indium Gallium Zinc Oxide, IGZO).
Source S and drain D are respectively arranged on channel layer 12, and source S and drain D are contacted with channel layer 12 respectively, in
When the channel layer of thin film transistor (TFT) T does not turn on, the two is electrically isolated.Wherein, the material of source S and drain D can for metal (such as
Aluminium, copper, silver, molybdenum or titanium) or the single or multi-layer structure that is constituted of its alloy.In addition, part is to transmit leading for driving signal
The structure with source S and drain D same layer and same manufacturing process, such as data line can be used in line.
It is noted that the source S of the thin film transistor (TFT) T of the present embodiment and drain D are also set to etching termination
On (etch stop) layer ES, and source S is contacted from the opening of etch stop layer ES with channel layer 12 respectively with one end of drain D.
Wherein, etch stop layer ES can be, for example, organo-siloxane compound or single-layer inorganic material such as silicon nitride, oxygen for organic material
SiClx, silicon oxynitride, silicon carbide, aluminium oxide, hafnium oxide or the multilayered structure of above-mentioned material combination.But, implement in others
In example, source S and drain D can also be directly arranged on channel layer 12, without etch stop layer ES.
In addition, the first insulating layer 13 is set in drain D as shown in Figure 1B and Fig. 1 C, and at least covering part drain D.
Wherein, the first insulating layer 13 has a first through hole V1 on drain D.Planarization layer 14 is set on the first insulating layer 13,
And there is one second through-hole V2 on drain D, and first through hole V1 and the size of the second through-hole V2 can be it is identical or not identical,
And it is without restriction.In this, the plan view shape of first through hole V1 and the second through-hole V2 are respectively by taking square as an example.Wherein, first
Through-hole V1 and the second through-hole V2 partially overlaps and forms an overlapping O (as shown in the dashed region O of Figure 1B), that is to say, that the
One through-hole V1 and projection of the second through-hole V2 on the substrate S1 of thin film transistor base plate 1 are overlapped, and the area of overlapping O
It can be between 4 to 49 square microns.
In addition, first through hole V1 can be situated between with the area of the overlapping O of the second through-hole V2 and the area ratio of first through hole V1
Between 0.14~0.78, and the area ratio of the area of the overlapping O of first through hole V1 and the second through-hole V2 and the second through-hole V2
Example also can be between 0.14~0.78, and in this, area can be explained with the area of section or the area of projection, such as the overlapping
The area for locating O is 9 square microns, and the area of first through hole V1 is 36 square microns.Compared to the prior art in compared with large through-hole
For the technology for etching another through-hole, the area of first through hole V1 of the invention and the second through-hole V2 overlapping O are compared with the prior art
Via area it is small, and do not have in the alignment issues for aligning another through-hole in large through-hole.In addition, also due to the face of overlapping O
Product is small compared with the via area of the prior art, therefore when black-matrix layer BM is set in scan line, opposite cover width can also
With more existing small, therefore the pixel aperture ratio of display panel can be improved.It is specifically intended that first through hole V1 and the second through-hole V2
The width of overlapping O is between 2 to 8 microns, in favor of subsequent manufacturing process.
Referring to figure 2. shown in A to Fig. 2 D, in this, the shape of the first through hole V1 and the second through-hole V2 of different aspects are listed
And its relativeness schematic diagram.
The shape of first through hole V1 and the second through-hole V2 can for example separately include polygon (Fig. 2A, Fig. 2 C), round (figure
2B), oval (Fig. 2 D) or irregular shape.In Fig. 2A to Fig. 2 D, the overlapping cases of first through hole V1 and the second through-hole V2 compared with
Good person is Fig. 2A, that is, first through hole V1 and the second through-hole V2 are rectangle, and the weight of first through hole V1 and the second through-hole V2
It is folded to be in central part.In this way, the problem of less having contraposition small through hole in existing large through-hole, and then after will not influence
In continuous manufacturing process, electrically conducting for transparency conducting layer (if contraposition is bad, may will affect the setting of transparency conducting layer, in turn
Influence drain electrode and the electrical connection of pixel electrode).
Referring again to shown in Fig. 1 C, second insulating layer 15 is set on planarization layer 14, and pixel electrode layer 16 is set to
In second insulating layer 15, in this, pixel electrode layer 16 is in pectination.In addition, pixel electrode layer 16 is set to first through hole V1 and
In two through-hole V2, and drain D can be electrically connected via the overlapping O of first through hole V1 and the second through-hole V2.Wherein, pixel electrode
The material of layer 16 may be, for example, indium tin oxide (ITO), indium-zinc oxide (IZO), aluminium zinc oxide (AZO), cadmium tin-oxide
(CTO), tin oxide (SnO2) or the transparent conductive materials such as zinc oxide (ZnO).
Special one is mentioned that, when prior art etching insulating layer, the side wall of through-hole is easy to produce right angle or chamfering and has
Offset exists, therefore when transparency conducting layer is set in through-hole, broken string situation will be easy to produce and influence yield.But of the invention
In the first side wall P1 of the overlapping O of one through-hole V1 and the second through-hole V2, wherein the one of the pixel electrode layer 16 of overlapping O is inserted
Part is located at the first side wall P1, and directly contacts (as shown in the right side wall of the through-hole of Fig. 1 C) with planarization layer 14.In addition, this hair
In the first side wall P2 of the overlapping O of bright first through hole V1 and the second through-hole V2, the second insulating layer 15 of overlapping O is inserted
A portion is located at second sidewall P2 and is directly contacted (as shown in the left side wall of the through-hole of Fig. 1 C) with planarization layer 14, second
The second insulating layer 15 of side wall P2 can be such that the upper and lower insulating layer positioned at planarization layer 14 connects, therefore offset is issuable
Quantity is few compared with the existing technology, and more gentle after the general etching of flatness layer 15, and the different layered relationship of this two kinds of side walls makes
When pixel electrode layer 16 must be arranged, the probability of broken string is also relatively small, and the yield of manufacturing process can be improved indirectly.
In addition, common electrode layer 18 is set between planarization layer 14 and second insulating layer 15.
It is further mentioned that, in other state sample implementations, as shown in figure 3, due to first through hole V1 of the invention and second
The area of the overlapping O of through-hole V2 is small compared with the through-hole of the prior art, therefore scan line can have one in the intersection of proximity data line
Recess portion U (scan line of recess portion U is hollowed out), and recess portion U can be correspondingly arranged in the overlapping of first through hole V1 and the second through-hole V2
(Fig. 3 only shows the part of the overlapping of first through hole V1 and the second through-hole V2, i.e. region O, does not show first through hole V1 and
The plan view shape of two through-hole V2).As noted previously, as first through hole V1 and the area of the overlapping O of the second through-hole V2 are more existing
The through-hole of technology is small, so scan line upper recess U is not too large and scan line is made to generate broken string, and only will cause with recess portion U
The line width of the scan line at place is smaller, therefore can reduce the coupled capacitor between scan line and data line whereby.
It then, is a kind of schematic cross-sectional view of display panel 2 of present pre-ferred embodiments shown in referring to figure 4..
Display panel 2 includes a thin film transistor base plate 1, an opposite substrate S2 and a liquid crystal layer L.
Thin film transistor base plate 1 in being described in detail among the above, repeats no more in this.Opposite substrate S2 and thin film transistor base plate
1 is oppositely arranged, and optionally has an an electrode layer E and alignment film A.Wherein, opposite substrate S2 can be a light-permeable
Material, e.g. glass, quartz or the like.In practice, the substrate S1 and opposite substrate S2 of thin film transistor base plate 1
Different materials can be selected, e.g. opposite substrate S2 uses potash glass substrate, and substrate S1 uses borate alkali-free glass base
Plate.In addition, electrode layer E is the side for being set to opposite substrate S2 and facing thin film transistor base plate 1, and alignment film A is then set to
Under electrode layer E.In addition, also can be inserted into a colored filter F between opposite substrate S2 and electrode layer E to show as colorization
It is used.In addition, liquid crystal layer L is set between thin film transistor base plate 1 and opposite substrate S2.
In addition, being a kind of schematic cross-sectional view of display device 3 of present pre-ferred embodiments shown in referring to figure 5..
Display device 3 includes a display panel 2 and a backlight module B.And display panel 2 includes a thin film transistor base plate
1, an an opposite substrate S2 and liquid crystal layer L.Thin film transistor base plate 1 in being described in detail among the above, repeats no more in this.
Opposite substrate S2 is oppositely arranged with thin film transistor base plate 1, and selecting property have an electrode layer E and an alignment film
A.Wherein, opposite substrate S2 can be the material of a light-permeable, e.g. glass, quartz or the like.In practice, film
Different materials can be selected in the substrate S1 and opposite substrate S2 of transistor base 1, and e.g. opposite substrate S2 uses potash glass base
Plate, and substrate S1 uses borate alkali-free glass substrate.In addition, electrode layer E is to be set to opposite substrate S2 in face of film crystal
The side of pipe substrate 1, and alignment film A is then set under electrode layer E.In addition, can also be inserted between opposite substrate S2 and electrode layer E
Enter a colored filter F to be used to show as colorization.In addition, liquid crystal layer L is set to thin film transistor base plate 1 and opposite base
Between plate S2.It needs it is specifically intended that the source S and drain D of the thin film transistor (TFT) T of Fig. 4 and Fig. 5 are set to etch stop layer ES
On, and source S is contacted from the opening of etch stop layer ES with channel layer 12 respectively with one end of drain D.Wherein, etch stop layer
ES can be, for example, organo-siloxane compound or single-layer inorganic material such as silicon nitride, silica, silicon oxynitride, carbon for organic material
SiClx, aluminium oxide, hafnium oxide or the multilayered structure of above-mentioned material combination.It but, in other examples, can also be by source S
It is directly arranged on channel layer 12 with drain D, and is contacted with channel layer 12.
In addition, backlight module B is set to the other side of the thin film transistor base plate 1 relative to opposite substrate S2, and issue light
Line projects light by liquid crystal layer L, then by opposite substrate S2 from the substrate S1 of thin film transistor base plate 1.
In conclusion because the thin film transistor base plate of a kind of display panel and display device according to the present invention has first
Insulating layer and planarization layer, and the first insulating layer has a first through hole on drain electrode, planarization layer has on drain electrode
One second through-hole, and first through hole is Chong Die with the second throughhole portions and forms an overlapping.In addition, pixel electrode layer is set to
On two insulating layers, and inserts overlapping and connect drain electrode.Whereby, it is compared with existing, first through hole of the present invention and the second through-hole
The size of overlapping is smaller, so that the shading-area of black-matrix layer is smaller, therefore display panel and display device of the invention can
With biggish pixel aperture ratio.
The foregoing is merely illustratives, rather than are restricted person.It is any without departing from spirit and scope of the invention, and to it
The equivalent modifications or change of progress, are intended to be limited solely by claim.