CN105988254B

CN105988254B - Display panel

Info

Publication number: CN105988254B
Application number: CN201510062053.0A
Authority: CN
Inventors: 余翊菱; 卓暐清; 朱夏青
Original assignee: Innolux Corp
Current assignee: Innolux Corp
Priority date: 2015-02-06
Filing date: 2015-02-06
Publication date: 2020-05-05
Anticipated expiration: 2035-02-06
Also published as: CN105988254A

Abstract

The display panel of the present invention includes: a first substrate; a scanning line located on the first substrate; a data line on the first substrate, wherein the data line and the scan line have a first overlap region; and an active layer disposed between the data line and the scan line, wherein the active layer, the data line, and the scan line have a second overlapping region, wherein the second overlapping region is disposed in the first overlapping region and has a via hole, the via hole connects the data line and the active layer, and wherein an edge of the scan line has a first length in a direction parallel to a substantial extension direction of the scan line in the first overlapping region; in the second overlapping area, the active layer has a second length in a direction parallel to the substantial extension direction of the scanning line; and the second length is greater than the first length.

Description

Display panel

Technical Field

The present invention relates to a display panel, and more particularly, to a display panel with reduced parasitic capacitance by changing the area, size and shape of a source.

Background

As display technologies have been advanced, all devices have been developed to be small, thin and light, and thus, the conventional cathode ray tube has been developed into a liquid crystal display device. In particular, liquid crystal display devices are used in a wide variety of fields, and most of display devices used in daily life, such as mobile phones, notebook computers, video cameras, music players, mobile navigation devices, and televisions, use liquid crystal display panels.

In the conventional lcd device, a liquid crystal layer is sandwiched between two electrodes, and the tilting of liquid crystal molecules between the liquid crystal layers is controlled by voltage, so that light emitted from a backlight module disposed below the lcd panel can penetrate or cannot penetrate the liquid crystal layer, thereby achieving the purpose of display. In addition, the purpose of presenting different colors is achieved through pixel definition.

Even though the development technology of the liquid crystal display device is becoming mature, manufacturers still strive to develop a display device with higher display quality to meet the requirement of the consumer on the display quality, and therefore, a display device with improved display quality is still required to be developed, and a more stable display effect is expected to be brought to the consumer.

Disclosure of Invention

The invention provides a display panel, which can reduce the parasitic capacitance between the overlapping areas of data lines and scanning lines by changing the area, size and shape of a source electrode.

The display panel of the present invention includes: a first substrate; a scanning line located on the first substrate; a data line on the first substrate, the data line and the scan line having a first overlap region; and an active layer disposed between the data line and the scan line, wherein the active layer, the data line, and the scan line have a second overlapping region, wherein the second overlapping region is disposed in the first overlapping region and has a via hole, the via hole connects the data line and the active layer, and wherein an edge of the scan line has a first length in a direction parallel to a substantial extension direction of the scan line in the first overlapping region; in the second overlapping area, the active layer has a second length in a direction parallel to the substantial extension direction of the scanning line; and the second length is greater than the first length.

In the display panel of the invention, the first overlapping area includes a first edge and a first concave edge, wherein the first edge is the edge of the scan line in the first overlapping area, and an end of the first concave edge is connected to an end of the first edge.

In the display panel of the invention, the first overlapping region further includes a second concave edge, wherein two end points of the first edge are respectively connected with one end point of the first concave edge and one end point of the second concave edge, and the curvature radii of the first concave edge and the second concave edge are different.

In the display panel of the present invention, a drain electrode is further included, and a predetermined distance is left from the data line to define a channel region; wherein the first concave edge is adjacent to the drain electrode relative to the second concave edge; the data line has a first data line edge and a second data line edge opposite to the first data line edge, and the first data line edge is adjacent to the drain electrode relative to the second data line edge; wherein the first concave edge has a first end point which is the intersection point of the scanning line and the data line, and a tangent line perpendicular to the extending direction of the scanning line along the outermost edge of the first data line is used as a first base line, and a first distance is arranged between the first end point and the first base line; the second concave edge has a third end point which is the intersection point of the scanning line and the data line, and the outermost edge of the second data line is taken as a second base line along a tangent line which is vertical to the extending direction of the scanning line, and a second distance is reserved between the third end point and the second base line; and the second distance is greater than the first distance.

In the display panel of the invention, the display panel further comprises a drain electrode which is arranged on the scanning line and is separated from the data line by a preset distance so as to define a channel region; the first overlapping area has a second edge, a first concave edge and a third concave edge, wherein the second edge is the edge of the data line in the first overlapping area, and the second edge is relatively adjacent to the drain electrode, wherein two end points of the second edge are respectively connected with one end point of the first concave edge and one end point of the third concave edge, and the radius of curvature of the first concave edge is different from that of the third concave edge.

In the display panel of the present invention, the scan line has a first scan line edge, the data line has a first data line edge, the active layer has a first active layer edge relatively adjacent to the first scan line edge and a second active layer edge relatively adjacent to the first active layer edge, wherein the first scan line edge intersects the first data line edge at a fifth end, the first active layer edge intersects the first data line edge at a sixth end, and the second active layer edge intersects the first data line edge at a second end; and a connecting line between the fifth end point and the sixth end point intersects with a connecting line between the second end point and the sixth end point and forms an angle, and the angle is not 180 degrees.

In the display panel of the invention, the data line further has a second data line edge opposite to the first data line edge, wherein the second data line edge intersects the first scan line edge at a seventh end, the second data line edge intersects the first active layer edge at an eighth end, and an included angle between a connection line of the fifth end and the sixth end and a substantial extending direction of the data line is smaller than an included angle between a connection line of the seventh end and the eighth end and the substantial extending direction of the data line.

In the display panel of the invention, the extending direction of the second edge is substantially the same as the extending direction of the data line.

In the display panel of the invention, the data line outside the first overlapping area has a third length in a direction parallel to the substantial extending direction of the scan line, and the second length is greater than the third length.

In the display panel of the present invention, further comprising: a plurality of scanning lines arranged on the first substrate; a plurality of data lines disposed on the first substrate and respectively intersecting the scan lines; and a plurality of sub-pixel units, which are arranged between the two adjacent scanning lines and the data lines, wherein each sub-pixel unit is respectively provided with a thin film transistor unit which comprises a source electrode and a drain electrode, the source electrode is electrically connected with the data line, and the drain electrode is arranged on the scanning line; in two adjacent sub-pixel units, the distance between the drain and the source of the corresponding sub-pixel unit is smaller than the distance between the drain and the source of the adjacent sub-pixel unit.

In the display panel of the present invention, the through hole has a non-perfect circular contour.

In the display panel of the present invention, the through hole has an elliptical shape when viewed from the data line toward the first substrate, and the elliptical shape has a major axis and a minor axis, and the major axis forms an angle of 0 to 10 degrees with a direction in which the data line substantially extends.

In the display panel of the present invention, the long axis is substantially parallel to the extending direction of the data line.

In the display panel of the invention, the parasitic capacitance between the overlapping areas of the data lines and the scanning lines can be reduced by changing the area, size and shape of the source electrode. In addition, the overlapping area is designed to have at least one concave edge, so that the data line is more matched with the design of the pixel electrode, the rotation angles of the liquid crystal are consistent, and the optical performance of the liquid crystal layer is improved. Furthermore, the electrical performance of the thin film transistor can be improved by reducing the distance of the channel region.

Drawings

To further illustrate the technical content of the present invention, the following detailed description is provided in conjunction with the embodiments and the accompanying drawings, in which:

fig. 1 is a top view of a thin film transistor substrate according to embodiment 1 of the present invention.

Fig. 2 is a schematic cross-sectional view of a thin film transistor substrate according to embodiment 1 of the present invention.

Fig. 3 is a top view of a thin film transistor of the thin film transistor substrate according to embodiment 1 of the present invention.

Fig. 4 is a schematic cross-sectional view of a display panel according to embodiment 1 of the present invention.

Fig. 5 is a schematic cross-sectional view of a display device according to embodiment 1 of the present invention.

Fig. 6 is a top view of a thin film transistor substrate according to embodiment 2 of the present invention.

Fig. 7 is a top view of a thin film transistor substrate according to embodiment 3 of the present invention.

Detailed Description

The following description of the embodiments of the present invention is provided by way of specific examples, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The invention is capable of other and different embodiments and its several details are capable of modification in various other respects, all without departing from the spirit and scope of the present invention.

Example 1

Fig. 1 is a top view of the thin film transistor substrate of the present embodiment, and fig. 2 is a schematic cross-sectional view of the thin film transistor substrate of the cross-sectional line QQ' in fig. 1. As shown in fig. 1 and 2, the thin film transistor substrate of the present embodiment includes: a first substrate 11; a scan line 12 disposed on the first substrate 11; a data line 151 disposed on the first substrate 11, wherein the data line 151 and the scan line 12 have a first overlap region A; an active layer 14 disposed between the data lines 151 and the scan lines 12, and the active layer 14, the data lines 151 and the scan lines 12 have a second overlapping area B, wherein the second overlapping area B is disposed in the first overlapping area A and has a via 150.

In the process of manufacturing the tft substrate of this embodiment, first, a first metal layer including a scan line 12 (serving as a gate electrode) is formed on a first substrate 11; then, a gate insulation layer 131 is formed on the first metal layer and the first substrate 11, and an active layer 14 is formed on the gate insulation layer 131 and above the gate 12 corresponding to the first metal layer; next, forming an etching barrier layer 132 on the active layer 14, wherein the etching barrier layer 132 includes a plurality of openings 1321 to expose a portion of the active layer 14; then, a second metal layer including the data line 151 (which is used as a source) and the drain 152 is formed on the etching barrier layer 132 and the active layer 14, thereby completing the fabrication of the thin film transistor unit of the present embodiment.

Then, a first insulating layer 133 and a planarization layer 134 are sequentially formed on the etching barrier layer 132 and the second metal layer, and the first insulating layer 133 and the planarization layer 134 are etched to have

openings

1331, 1341 to expose the drain 152. In addition, a common electrode layer 161, a second insulating layer 135 and a pixel electrode layer 162 are further sequentially formed on the planarization layer 134; the second insulating layer 135 is etched to have an opening 1351 corresponding to the

openings

1331, 1341 to expose the drain 152; the pixel electrode layer 162 further extends toward the sidewall of the opening 1351 to electrically connect to the drain 152.

In this embodiment, the first metal layer and the second metal layer may be formed of conductive materials commonly used in the art, such as metals, alloys, metal oxides, metal oxynitrides, or other electrode materials commonly used in the art; and preferably a metal material, but the present invention is not limited thereto. In addition, the first metal layer and the second metal layer of the present embodiment are not limited to a single material layer, and a composite layer structure of stacking multiple materials may also be used. In addition, the first substrate 11 can be made of a base material commonly used in the art, such as glass, plastic, flexible material, etc.; the gate insulating layer 131, the first insulating layer 133, the planarization layer 134, and the second insulating layer 135 may be made of insulating layer materials commonly used in the art; the active layer 14 may be made of a semiconductor material commonly used in the art, such as polysilicon (Poly-Silicon), Amorphous Silicon (Amorphous Silicon), Indium Gallium Zinc Oxide (IGZO), or the like; the pixel electrode layer 162 and the common electrode layer 161 can be made of transparent conductive electrode materials commonly used in the art, such as: indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO), and the like.

FIG. 3 is an enlarged view of one of the TFT cells shown in FIG. 1; as shown in fig. 3, in the first overlap area a, an edge of the scan line 12 (in this embodiment, the second scan line edge 12b, in another embodiment, the edge may refer to the first scan line edge 12a) has a first length L1 in the direction in which the parallel scan line 12 substantially extends; in the second overlapping area B, the active layer 14 has a second length L2 along the direction substantially extending parallel to the scan line 12; and the second length L2 is greater than the first length L1.

By designing the edge length L1 of the scan line 12 in the first overlap region a to be smaller than the second length L2 of the active layer 14 in the second overlap region B in the direction in which the scan line 12 substantially extends, the area where the data line 151 overlaps the scan line 12 is reduced, and the parasitic capacitance between the scan line 12 and the data line 151 is reduced. Here, only one edge (the second scan line edge 12b) of the scan lines 12 is taken as an example; in the first overlap area a, the length of the other edge of the scan line 12 (the first scan line edge 12a) in the direction in which the scan line 12 substantially extends is the same as the length of the active layer 14 in the second overlap area B in the direction in which the scan line 12 substantially extends (i.e., the second length L2).

As shown in FIG. 3, the scan line 12 has a first scan line edge 12a and a second scan line edge 12b on opposite sides thereof, and the data line 151 has a first data line edge 151a and a second data line edge 151b on opposite sides thereof. The first overlapping area a includes a region surrounded by a first edge 12b ', a second edge 151 a', a third edge 12a ', and a fourth edge 151 b'. The first edge 12b 'is an edge of the scan line 12 in the first overlap area a (in this embodiment, where the data line 151 overlaps the second scan line edge 12b), the second edge 151 a' is a first data line edge 151a of the data line 151 in the first overlap area a, the third edge 12a 'is another edge of the scan line 12 in the first overlap area a (in this embodiment, where the data line 151 overlaps the first scan line edge 12a), and the fourth edge 151 b' is a second data line edge 151b of the data line 151 in the first overlap area a.

The second overlapped region B includes a region surrounded by a first active layer edge 14a, a second edge 151a ', a fourth edge 151B', and a second active layer edge 14B. The first active layer edge 14a and the second active layer edge 14b are edges of the active layer 14 in the first overlap region a. Since the second overlapping area B is located in the first overlapping area a, the first active layer edge 14a is the edge of the second overlapping area B adjacent to the active layer 14 and substantially parallel to the third edge 12a ', and the second active layer edge 14B is the edge of the second overlapping area B adjacent to the active layer 14 and substantially parallel to the first edge 12B'.

In addition, the first overlapping area a further includes a first concave edge 155, a second concave edge 154, a third concave edge 157 and a fourth concave edge 156, wherein two end points of the first edge 12b 'are respectively connected to one end points of the first concave edge 155 and the second concave edge 154, two end points of the second edge 151 a' are respectively connected to one end points of the first concave edge 155 and the third concave edge 157, two end points of the third edge 12a 'are respectively connected to one end points of the third concave edge 157 and the fourth concave edge 156, and two end points of the fourth edge 151 b' are respectively connected to one end points of the second concave edge 154 and the fourth concave edge 156.

In addition, the first concave edge 155 has a first end P1 and a second end P2, wherein the first end P1 is the intersection of the scan line 12 and the data line 151, and the second end P2 is the intersection of the data line 151 and the active layer 14. The second flange 154 has a third end P3 and a fourth end P4, wherein the third end P3 is the intersection of the scan line 12 and the data line 151, and the fourth end P4 is the intersection of the data line 151 and the active layer 14. The third concave edge 157 has a fifth end P5 and a sixth end P6, wherein the fifth end P5 is the intersection of the scan line 12 and the data line 151, and the sixth end P6 is the intersection of the data line 151 and the active layer 14. The fourth concave edge 156 has a seventh end P7 and an eighth end P8, wherein the seventh end P7 is the intersection of the scan line 12 and the data line 151, and the eighth end P8 is the intersection of the data line 151 and the active layer 14.

In a preferred embodiment, the first concave edge 155 and the second concave edge 154 have different radii of curvature. More specifically, as shown in fig. 3, the drain electrode 152 is spaced apart from the data line 151 by a predetermined distance to define a channel region 153, and the first concave edge 155 is adjacent to the drain electrode 152 relative to the second concave edge 154. In addition, the data line 151 has a first data line edge 151a and a second data line edge 151b opposite to the first data line edge 151a, and the first data line edge 151a is adjacent to the drain electrode 152 with respect to the second data line edge 151 b. Here, a tangent line perpendicular to the extending direction of the scan line 12 along the outermost edge of the first data line edge 151a is used as a first baseline, and a first distance D1 is formed between the first end P1 and the first baseline; meanwhile, a second distance D2 is formed between the third end point P3 and the second base line by using a tangent line perpendicular to the extending direction of the scan line 12 and along the outermost edge of the second data line edge 151b as a second base line; and the second distance D2 is greater than the first distance D1. Similarly, the third concave edge 157 is adjacent to the drain 152 relative to the fourth concave edge 156, and the relationship between the third concave edge 157 and the fourth concave edge 156 is the same as the relationship between the first concave edge 155 and the second concave edge 154, and therefore, the description thereof is omitted.

Further, as shown in fig. 3, the first concave edge 155 and the third concave edge 157 have different radii of curvature; and the second concave edge 154 and the fourth concave edge 156 have different radii of curvature.

As shown in fig. 3, by designing the first concave edge 155, the second concave edge 154, the third concave edge 157 and the fourth concave edge 156 in the overlap region, the portion of the first overlap region a outside the second overlap region B can be reduced, and the parasitic capacitance between the scan line 12 and the data line 151 can be further reduced. In addition, the first concave edge 155, the second concave edge 154, the third concave edge 157 and the fourth concave edge 156 have different curvature radiuses, so that the shapes of the concave edges are more suitable for the patterns of the pixel electrode layers, the rotation angles of the liquid crystals are consistent, and the optical performance of the liquid crystal display is improved. In addition, the second distance is designed to be larger than the first distance, so that the first overlapping area a and the second overlapping area B are closer to the channel region, and the purpose of reducing the length of the channel region can be achieved, thereby improving the electrical performance of the thin film transistor unit.

In addition, the extending direction of the second edge 151 a' is substantially the same as the extending direction of the data line 151 for the purpose of making the length of the channel region uniform.

Furthermore, as shown in fig. 3, the active layer 14 has a first active layer edge 14a opposite to and adjacent to the first scan line edge 12a and a second active layer edge 14b opposite to the first active layer edge 14 a. Wherein the first scan line edge 12a intersects the first data line edge 151a at a fifth end point P5, the first active layer edge 14a intersects the first data line edge 151a at a sixth end point P6, and the second active layer edge 14b intersects the first data line edge 151a at a second end point P2; and the connection line of the fifth end point P5 and the sixth end point P6 intersects the connection line of the second end point P2 and the sixth end point P6 and forms an angle, the angle is not 180 degrees, that is, the two connection lines are not in a straight line. In addition, the second scan line edge 12b and the first data line edge 151a intersect at the first end P1, and the connection line between the second end P2 and the sixth end P6 intersects the connection line between the second end P2 and the first end P1 with an angle therebetween, which is not 180 degrees, i.e., the two connection lines are not in a straight line. Furthermore, the first scan line edge 12a and the second data line edge 151b intersect at a seventh terminal P7, the first active layer edge 14a and the second data line edge 151b intersect at an eighth terminal P8, and the second active layer edge 14b and the second data line edge 151b intersect at a fourth terminal P4; and the connection line of the seventh end point P7 and the eighth end point P8 intersects the connection line of the fourth end point P4 and the eighth end point P8 and forms an angle, the angle is not 180 degrees, that is, the two connection lines are not in a straight line. Similarly, the second scan line edge 12b and the second data line edge 151b intersect at the third end point P3, and the connection line between the fourth end point P4 and the eighth end point P8 intersects the connection line between the fourth end point P4 and the third end point P3 while sandwiching an angle, which is not 180 degrees, i.e. the two connection lines are not in a straight line.

In addition, as shown in fig. 3, an angle θ 1 between a connection line of the fifth terminal P5 and the sixth terminal P6 and the data line 151 in the substantially extending direction is smaller than an angle θ 2 between a connection line of the seventh terminal P7 and the eighth terminal P8 and the data line 151 in the substantially extending direction. The same relationship can also be seen from the connection between the fourth terminal P4 and the third terminal P3 and the connection between the second terminal P2 and the first terminal P1, and therefore, the description thereof is omitted here.

Furthermore, as shown in FIG. 3, the data line 151 outside the overlap area A has a third length L3 in the direction of extending the parallel scanning lines 12, and the second length L2 is greater than the third length L3.

As shown in fig. 1, the thin film transistor substrate of the present embodiment includes: a plurality of scan lines 12 disposed on a first substrate (not shown); a plurality of data lines 151 disposed on a first substrate (not shown) and respectively intersecting the scan lines 12; and a plurality of sub-pixel units disposed between two adjacent scan lines 12 and data lines 151, wherein each of the pixel units has a thin film transistor unit including a source (i.e., a first overlap region a) and a drain 152, wherein the source (i.e., the first overlap region a) is electrically connected to the data line 151, and the drain 152 is disposed on the scan line 12. In two adjacent sub-pixel units, the distance X between the drain 152 and the source (i.e., the overlapping region a) of the corresponding sub-pixel unit is smaller than the distance Y between the drain 152 and the source (i.e., the overlapping region a) of the adjacent sub-pixel unit. By making the distance X smaller than the distance Y, the distance of the channel region can be shortened, so as to improve the electrical performance of the thin film transistor unit.

In addition, as shown in fig. 1, a through hole 150 is disposed in the overlapping region a and has a non-perfect circular contour. Preferably, the through-hole 150 has an oval-like shape. As shown in fig. 3, such an elliptical shape has a major axis a and a minor axis b, the major axis a forms an angle of 0 to 10 degrees with respect to the direction in which the data lines 151 substantially extend, and preferably the major axis a is parallel to the direction in which the data lines 151 substantially extend. Thereby, the contact area of the via hole 150 can be increased.

The thin film transistor substrate of the present embodiment can be applied to a display panel. As shown in fig. 4, the display panel of the present embodiment includes: a thin film transistor substrate 1, on which a first alignment layer 2 is disposed; a pair of side substrates 3, which are disposed opposite to the thin film transistor substrate 1 and have a second alignment layer 4 disposed thereon, wherein the second alignment layer 4 is disposed opposite to the first alignment layer 2; the frame glue 5 is arranged between the thin film transistor substrate 1 and the opposite substrate 3 and is positioned on the periphery of the thin film transistor substrate 1 and the opposite substrate 3; and a liquid crystal layer 6 disposed in a space formed by the thin film transistor substrate 1 and the opposite substrate 3. As shown in fig. 2 and 4, the tft unit (not shown) is disposed on the first substrate 11, and the color filter layer (not shown) is disposed on the opposite substrate 3, so that the opposite substrate 3 is a color filter substrate; however, in other embodiments, a color filter layer (not shown) may also be disposed on the first substrate 11 as shown in fig. 1, so that the first substrate 11 is a color filter on array (COA) integrated with the color filter array.

The display panel of the embodiment can be applied to a display device. As shown in fig. 5, the display device of the present embodiment includes: the aforementioned display panel 10; and a backlight module 20 disposed below the display panel 10 for providing a light beam to penetrate the display panel 10.

Example 2

The tft substrate, the display panel and the display apparatus of this embodiment are the same as those of embodiment 1, except that the overlapping unit is only provided with the fourth concave edge 156 and the second concave edge 154, and is not provided with the first concave edge and the third concave edge.

Example 3

The tft substrate, the display panel and the display apparatus of this embodiment are the same as those of embodiment 1, except that the overlapping unit has only the fourth concave edge 156, and the first concave edge, the second concave edge and the third concave edge are not provided.

The display device manufactured in the foregoing embodiment of the invention can be applied to any electronic device that needs a display screen and is known in the art, such as a display, a mobile phone, a notebook computer, a video camera, a music player, a mobile navigation device, a television, and the like.

Claims

1. A display panel, comprising:

a first substrate;

a scan line on the first substrate and having a first scan line edge;

a data line and a drain electrode on the first substrate, the data line having a first data line edge, and the data line and the scan line having a first overlap region, wherein the first overlap region includes a first edge and a first concave edge, the first edge is an edge of the scan line in the first overlap region, and an end of the first concave edge is connected to an end of the first edge;

an active layer disposed between the data line and the scan line, the active layer having a first active layer edge opposite to the first scan line edge and a second active layer edge opposite to the first active layer edge, and the active layer, the data line and the scan line having a second overlapping region, wherein the second overlapping region is disposed in the first overlapping region and has a via hole, the via hole connects the data line and the active layer; and

a pair of side substrates disposed opposite to the first substrate;

wherein, in the first overlapping area, the edge of the scan line has a first length in a substantially extending direction parallel to the scan line; in the second overlapping area, the active layer has a second length in the direction parallel to the substantial extending direction of the scan line; and the second length is greater than the first length,

wherein the first scanning line edge intersects the first data line edge at a fifth end, the first active layer edge intersects the first data line edge at a sixth end, and the second active layer edge intersects the first data line edge at a second end; and a connecting line of the fifth end point and the sixth end point intersects with a connecting line of the second end point and the sixth end point and forms an angle, and the angle is not 180 degrees.

2. The display panel of claim 1, wherein the first overlapping region further comprises a second concave edge, wherein two ends of the first edge are respectively connected to one end of the first concave edge and one end of the second concave edge, and the first concave edge and the second concave edge have different radii of curvature.

3. The display panel of claim 2, wherein the drain electrode is spaced apart from the data line by a predetermined distance to define a channel region; wherein the first concave edge is adjacent to the drain electrode relative to the second concave edge; the data line has a second data line edge opposite to the first data line edge, and the first data line edge is adjacent to the drain electrode relative to the second data line edge;

wherein the first concave edge has a first end point which is the intersection point of the scanning line and the data line, and the outermost edge of the first data line is used as a first base line along a tangent line perpendicular to the substantial extending direction of the scanning line, and a first distance is arranged between the first end point and the first base line; the second concave edge has a third end point which is the intersection point of the scanning line and the data line, and the outermost edge of the second data line is taken as a second base line along a tangent line which is vertical to the substantial extending direction of the scanning line, and a second distance is reserved between the third end point and the second base line; and the second distance is greater than the first distance.

4. The display panel of claim 1, wherein the drain is disposed on the scan line and spaced apart from the data line by a predetermined distance to define a channel region; the first overlapping area has a second edge and a third concave edge, wherein the second edge is the edge of the data line in the first overlapping area, and the second edge is relatively adjacent to the drain, wherein two ends of the second edge are respectively connected with one end of the first concave edge and one end of the third concave edge, and the radius of curvature of the first concave edge is different from that of the third concave edge.

5. The display panel of claim 1, wherein the data line further has a second data line edge opposite to the first data line edge, wherein the second data line edge intersects the first scan line edge at a seventh end, the second data line edge intersects the first active layer edge at an eighth end, and an angle between a connection line of the fifth end and the sixth end and the data line in the substantially extending direction is smaller than an angle between a connection line of the seventh end and the eighth end and the substantially extending direction of the data line.

6. The display panel of claim 4, wherein the second edge extends in a direction substantially the same as the data line.

7. The display panel of claim 1, wherein the data line outside the first overlap region has a third length in the substantially extending direction parallel to the scan line, and the second length is greater than the third length.

8. The display panel of claim 1, further comprising:

a plurality of scanning lines arranged on the first substrate;

a plurality of data lines disposed on the first substrate and respectively intersecting the scan lines; and

a plurality of sub-pixel units arranged between two adjacent scanning lines and data lines, wherein each sub-pixel unit is respectively provided with a thin film transistor unit comprising a source electrode, the source electrode is electrically connected with the data line, and the drain electrode is arranged on the scanning line;

in two adjacent sub-pixel units, the distance between the drain and the source of the corresponding sub-pixel unit is smaller than the distance between the drain and the source of the adjacent sub-pixel unit.

9. The display panel of claim 1, wherein the via has a non-perfect circular profile.

10. The display panel of claim 1, wherein the through hole has an elliptical shape having a major axis and a minor axis, the major axis being at an angle of 0 to 10 degrees with respect to a direction in which the data line substantially extends, as viewed toward the first substrate.

11. The display panel of claim 10, wherein the long axis is parallel to the substantially extending direction of the data line.