CN105721069A - 2.4G wireless signal detection system - Google Patents
2.4G wireless signal detection system Download PDFInfo
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- CN105721069A CN105721069A CN201410730662.4A CN201410730662A CN105721069A CN 105721069 A CN105721069 A CN 105721069A CN 201410730662 A CN201410730662 A CN 201410730662A CN 105721069 A CN105721069 A CN 105721069A
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Abstract
The invention provides a 2.4G wireless signal detection system, and the system is implemented on an FPGA platform of a XilinxVirtex-7 series. The system can be used for the spectrum analysis and interference and compossibility analysis of signals of a wireless local network, Bluetooth and ZigBee. The system mainly consists of four parts: 2.4G signal receiving and demodulation part, phase-locked loop frequency synthesis part, double-channel A/D switching part, and baseband signal FFT transformation part. The system is good in anti-interference performance, and is high in utilization rate of frequency band.
Description
Technical field
The present invention relates to signal detection field, particularly a kind of 2.4G radio signal detecting system.
Background technology
The wireless networks such as 2.4G frequency range is between 2.400GHz-2.485GHz, and this frequency range is the free frequency range of international regulations, WLAN Wi-Fi (IEEE802.11b/IEEE802.11g), bluetooth, ZigBee all can be operated in 2.4GHz frequency range.Along with the product of increasing company production and application 2.4GHz frequency range, the equipment of deployment increases sharply, and the number of the radio-frequency technique and agreement of sharing this frequency band is consequently increased.So being operated between the various wireless devices of this frequency range there will be interference unavoidably, even the equal operational excellence of equipment and operation within the scope of frequency band adjustments, the chance that Radio frequency interference occurs between equipment in this frequency band is also considerable.These interference may result in data-bag lost, power consumption increases and network performance declines.Developing a 2.4G radio signal detecting system and the signal of ISM band can be carried out effective spectrum analysis, can be interference and the compossibility analysis of this frequency range, radio network optimization, spectrum management etc. provides good support.On the other hand, detecting system for high frequency signal is higher to index requests such as data acquisition sampling precision, sample rate and processing speeds.Traditional signal detection system often adopts single-chip microcomputer or digital signal processor as main control unit, SCM Based data collecting system is due to the impact of single-chip microcomputer instruction cycle itself Yu speed, its clock frequency is relatively low, it is impossible to meet modern signal processing system to the real-time of data acquisition and synchronicity requirement.Although the data collecting system processing speed based on digital signal processor DSP is fast, but being subject to the restriction of serial command stream, sampling rate is only capable of reaching a few MHz, has been only capable of the very simple calculations of paired data stream, and DSP interrupts reducing the efficiency of system frequently in addition.
FPGA is the abbreviation of FieldProgrammableGateArray, i.e. field programmable gate array, and it is the product of development further on the basis of the programming devices such as PAL, GAL, EPLD.Having substantial amounts of gate and trigger in sheet, mostly be look-up table configuration, it is achieved technique mostly is SRAM, scale is big, and integrated level is high, and processing speed is fast, and execution efficiency is high.
Summary of the invention
The goal of the invention of the present invention is in that: for easily the disturbing of above-mentioned existence, frequency is relatively low all the time problem, it is provided that a kind of 2.4G radio signal detecting system.
A kind of 2.4G radio signal detecting system, including demodulation chip, frequency synthesis chip, wave filter and analog-digital chip.Wherein, demodulation chip selects the quadrature demodulation chip ADL5380 that ADI company provides, and frequency synthesis chip selects PLL frequency synthesizer ADF4350, and wave filter adopts Butterworth 3 rank passive filter.
ADL5380 covers the radio-frequency region of 400MHz～6GHz, has the linear index of industry rs most dynamic range and the best, and during 2500MHz, its second order inter-modulation section and third order intermodulation section are 31dBm and 60dBm respectively.
Frequency synthesis chip selects PLL frequency synthesizer ADF4350, and the continuous tuning within the scope of 137.5～4400MHz supported by frequency synthesizer.On sheet, VCO is-137dBc/Hz at the phase noise of 2.1GHz operating frequency, 1MHz skew place, and the phase noise in 137.5MHz operating frequency, 1MHz skew place is-155dBc/Hz.Voltage controlled oscillator (VCO) built-in for ADF4350 can cover the frequency range of 2200～4400MHz, it is provided that two radio frequency output ports, makes user output can be carried out digital programmable.
In the phase discriminator of ADF4350, reference frequency frequency multiplication takes 1 or 0, and reference frequency divider takes 1 or 0,10bit reference frequency divider, desirable 1 ~ 1023 frequency dividing.Reference frequency adopts the TCXO of 26MHz to provide, and the phase demodulation frequency of ADF4350 is up to 32MHz.It is spuious that phase demodulation frequency raising can reduce Fractional-N frequency device, it is possible to improves phase noise specifications, adopts 26MHz herein for obtaining better phase noise performance phase demodulation frequency.So, the reference frequency doubler of ADF4350 cuts out (namely D takes 0), reference frequency 2 frequency divider cuts out (namely T takes 0), R frequency divider takes 1, then phase discriminator operating frequency Fpfd is 26MHz.
The pre-divider ratio value INT of the output frequency of ADF4350 wherein 16bit is 16, when pre-frequency counter is 4/5 desirable 23 ~ 65535, when pre-frequency counter is 8/9 desirable 75 ~ 65535.MOD is fractional frequency division modulus, desirable 2 ~ 4056, and FRAC is fractional frequency division molecule, desirable 0 ~ MOD-1.X is radio frequency output frequency divider value, desirable 1/2/4/8/16.The present invention adopts overproof outer reception (difference 100M), it is desirable to output frequency is at 2.500 ~ 2.583GHz, and the concussion frequency of VCO is 2.2GHz ~ 4.4GHz, and radio frequency output X frequency divider takes 1.Frequency step of the present invention is 200KHz, takes 1 because radio frequency exports X frequency divider, so the frequency step=200k*X=200kHz of internal VCO.Then: MOD=26M/200k=130. low noise mode, ternary output, current pump push-and-pull electric current is set to 2.5mA.
The configuration of AD9862 depositor, closes sendaisle power supply, TxPOWERDOWN is set to 0xOf；Closing the power supply receiving passage B, RxPOWERDOWN is set to Ox14, bypass receives the input buffer circuit of passage B, and RxB is set to 0xS0, and bypass receives the data of passage B, and Digital is set to 0；For ease of calculating, data form adopts the complement of two's two's complement, and RxI/F is set to Ox04；AD9862 clock adopts externally input, and DLL is output as 2 frequencys multiplication of input, and frequency range is set to " low " pattern, and elkout2 output is consistent with DLL output.
Beneficial effects of the present invention: owing to have employed aforesaid way, simplifies structure, strong interference immunity, and band efficiency is high.
Accompanying drawing explanation
Fig. 1 is the structural representation of the present invention.
Labelling in figure: 1-digital to analog converter, 2-show frequency spectrum, 3-FFT, 4-FPGA, 5-ADF4350,6-ADL5380,7-2.4G frequency band signals.
Detailed description of the invention
A kind of 2.4G radio signal detecting system, including demodulation chip, frequency synthesis chip, wave filter and analog-digital chip.Owing to the signal frequency range to receive is at 2.400GHz ~ 2.485GHz, so when selecting demodulation chip, should first consider its frequency coverage, followed by suppressing the factors such as the interference size of signal capabilities and the linearity.Based on above-mentioned consideration, the present invention adopts the quadrature demodulation chip ADL5380 that ADI company provides, and adopts ADL5380 demodulator, it is possible to meet multiple honeycomb and broadband wireless data system requirements.ADL5380 covers the radio-frequency region of 400MHz～6GHz, has the linear index of industry rs most dynamic range and the best.Such as, when 2500MHz, its second order inter-modulation section and third order intermodulation section are 31dBm and 60dBm respectively.The superior ability of signal and the perfect adaptation of minimal noise are disturbed in remarkable linear index, suppression, make ADL5380 can keep the receiver dynamic range of the best under complicated real interference environment, for Direct Conversion Receiver, this is an important demand.Except high linearity, ADL5380 also provides for the exemplary variable frequency gain of 3～4dB, contributes to making receiver front end gain requirements be down to minimum.
Demodulation complete need provide local frequency, the frequency of local oscillator differs 100M with signal frequency, and its excursion is at 2.3G～2.585G.The present invention adopts PLL frequency synthesizer ADF4350, it be ADI company produce applicable radio frequency and microwave electron system in use frequency synthesis chip.The continuous tuning within the scope of 137.5～4400MHz supported by this complete frequency synthesizer.On sheet, VCO is-137dBc/Hz at the phase noise of 2.1GHz operating frequency, 1MHz skew place, phase noise in 137.5MHz operating frequency, 1MHz skew place is-155dBc/Hz, this comprehensive root-mean-square (RMS) phase error be equivalent under 2.1GHz frequency is 0.36 °, and the comprehensive root-mean-square phase error under 137.5MHz frequency is 0.02 °.Voltage controlled oscillator (VCO) built-in for ADF4350 can cover the frequency range of 2200～4400MHz.It addition, ADF4350 provides two radio frequency output ports, make user output can be carried out digital programmable.Different from other like products, ADF435O supports Integer N frequency dividing and fractional-N divide mode of operation, it is allowed to determine best spuious and phase noise performance by software control method, thus realizing the performance of the best.Additionally, 1/2/4/8/16 frequency dividing circuit allows users to generate the radio frequency output frequency being low to moderate 137.5MHz on sheet.
After demodulation, two groups of signals that mid frequency is 100M and mid frequency is 4900M will be respectively obtained, for target signal filter that mid frequency is 4900M is retained the signal that mid frequency is 100M, system will adopt band filter.The feature of Butterworth filter is that passband internal characteristic is very smooth, closely direct current signal, and the attenuation characteristic of this wave filter and phase characteristic are all fairly good, the requirement constituting filter device is very not strict yet, it is easy to obtain meeting the characteristic of design load.In addition passive filter (LC wave filter) is the filter circuit utilizing the modular design of inductance, electric capacity and resistance to constitute, and can filter certain once or multiple harmonic, have simple in construction, need not extraneous power supply, with low cost, operational reliability is higher, etc. advantage.So native system selects Butterworth 3 rank passive filter.
Analogue signal is transformed to digital signal, most common method is sampling, Nyquist Law requirement sample frequency is be more than or equal to the twice of signal highest frequency, the signal that frequency band is narrower to mid frequency is higher uses Nyquist law, can cause that sample frequency is significantly high has a lot of frequency range blank simultaneously, bandpass sampling is identical in itself with low pass sampling, and it is only relevant with signal bandwidth to sample, so using bandpass sampling can be substantially reduced sample rate this signal.AD9862 is the high performance mixed signal FEP of the applicable wireless broadband communication application that ADI company produces, sheet is integrated with two 12 64MSPSADC and two 14 128MSPSDAC, SNR is up to 70dB, function admirable, therefore the analog-to-digital conversion module of system selects AD9862.
The phase discriminator operating frequency D of ADF4350 is reference frequency doubler (taking 1 or 0), and T is reference frequency 2 frequency divider (taking 1 or 0), and R is 10bit reference frequency divider, desirable 1 ~ 1023 frequency dividing.Reference frequency adopts the TCXO of 26MHz to provide, and the phase demodulation frequency of ADF4350 is up to 32MHz.It is spuious that phase demodulation frequency raising can reduce Fractional-N frequency device, it is possible to improves phase noise specifications, adopts 26MHz herein for obtaining better phase noise performance phase demodulation frequency.So, the reference frequency doubler of ADF4350 cuts out (namely D takes 0), reference frequency 2 frequency divider cuts out (namely T takes 0), R frequency divider takes 1, then phase discriminator operating frequency Fpfd is 26MHz.Wherein INT is the pre-divider ratio value of 16bit, when pre-frequency counter is 4/5 desirable 23 ~ 65535, when pre-frequency counter is 8/9 desirable 75 ~ 65535.MOD is fractional frequency division modulus, desirable 2 ~ 4056, and FRAC is fractional frequency division molecule, desirable 0 ~ MOD-1.X is radio frequency output frequency divider value, desirable 1/2/4/8/16.The present invention adopts overproof outer reception (difference 100M), it is desirable to output frequency is at 2.500 ~ 2.583GHz, and the concussion frequency of VCO is 2.2GHz ~ 4.4GHz, so radio frequency output X frequency divider should take 1.Application claims frequency step is 200KHz, takes 1 because radio frequency exports X frequency divider, so the frequency step=200k*X=200kHz of internal VCO.MOD=26M/200k=130. low noise mode, ternary output, current pump push-and-pull electric current is set to 2.5mA.
Close sendaisle power supply, TxPOWERDOWN is set to 0xOf；Owing to adopting if sampling, therefore 1 road ADC need to only be used, close the power supply receiving passage B, RxPOWERDOWN is set to Ox14, bypass receives the input buffer circuit of passage B, and RxB is set to 0xS0, does not use AD9862 to receive decimation filter and the Hilbert wave filter of passage in the present invention, bypass simultaneously receives the data of passage B, and Digital is set to 0；For ease of calculating, data form adopts the complement of two's two's complement, and RxI/F is set to Ox04；AD9862 clock adopts externally input, and DLL is output as 2 frequencys multiplication of input, and frequency range is set to " low " pattern, and elkout2 output is consistent with DLL output.
Claims (6)
1. a 2.4G radio signal detecting system, including demodulation chip, frequency synthesis chip, wave filter and analog-digital chip, it is characterised in that:
Described demodulation chip adopts quadrature demodulation chip ADL5380, is connected with frequency synthesis chip；
Described frequency synthesis chip selects PLL frequency synthesizer ADF4350 to be connected with wave filter；Described wave filter adopts Butterworth 3 rank passive filter, is connected with analog-digital chip.
2. a kind of 2.4G radio signal detecting system according to claim 1, it is characterized in that: described demodulation chip, ADL5380 covers the radio-frequency region of 400MHz～6GHz, and when radio frequency is 2500MHz, its second order inter-modulation section and third order intermodulation section are 31dBm and 60dBm respectively.
3. a kind of 2.4G radio signal detecting system according to claim 1, it is characterized in that: described frequency synthesis chip, the continuous tuning within the scope of 137.5～4400MHz supported by frequency synthesizer, on sheet, VCO is-137dBc/Hz at the phase noise of 2.1GHz operating frequency, 1MHz skew place, phase noise in 137.5MHz operating frequency, 1MHz skew place is-155dBc/Hz, voltage controlled oscillator can cover the frequency range of 2200～4400MHz, it is provided that two radio frequency output ports.
4. a kind of 2.4G radio signal detecting system according to claim 3, it is characterised in that: in the phase discriminator of ADF4350, reference frequency frequency multiplication takes 1 or 0, and reference frequency divider takes 1 or 0,10bit reference frequency divider, desirable 1 ~ 1023 frequency dividing；Reference frequency adopts the TCXO of 26MHz to provide, and phase noise performance phase demodulation frequency adopts 26MHz.
5. a kind of 2.4G radio signal detecting system according to claim 1,3 or 4, it is characterized in that: described ADF4350 output frequency, the pre-divider ratio value INT of 16bit is 16, takes 23 ~ 65535 when pre-frequency counter is 4/5, takes 75 ~ 65535 when pre-frequency counter is 8/9, MOD is fractional frequency division modulus, taking 2 ~ 4056, FRAC is fractional frequency division molecule, takes 0 ~ MOD-1, X is radio frequency output frequency divider value, takes 1/2/4/8/16；Adopt overproof outer reception, difference is 100M, and output frequency is 2.2GHz ~ 4.4GHz in the concussion frequency of 2.500 ~ 2.583GHz, VCO, radio frequency output X frequency divider takes 1, frequency step is 200KHz, takes 1 because radio frequency exports X frequency divider, and the frequency step of internal VCO is 200kHz, MOD is 130, low noise mode, ternary output, current pump push-and-pull electric current is set to 2.5mA.
6. a kind of 2.4G radio signal detecting system according to claim 1, it is characterized in that: the configuration of AD9862 depositor, close sendaisle power supply, TxPOWERDOWN is set to 0xOf, close the power supply receiving passage B, RxPOWERDOWN is set to Ox14, and bypass receives the input buffer circuit of passage B, and RxB is set to 0xS0, bypass receives the data of passage B, Digital is set to 0, and data form adopts the complement of two's two's complement, and RxI/F is set to Ox04；AD9862 clock adopts externally input, and DLL is output as 2 frequencys multiplication of input, and frequency range is set to low mode, and elkout2 output is consistent with DLL output.
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| CN201410730662.4A CN105721069A (en) | 2014-12-05 | 2014-12-05 | 2.4G wireless signal detection system |
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| CN201410730662.4A CN105721069A (en) | 2014-12-05 | 2014-12-05 | 2.4G wireless signal detection system |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106603073A (en) * | 2016-11-24 | 2017-04-26 | 中国电子科技集团公司第四十研究所 | Integrated single-loop system for achieving low-phase-noise microwave broadband frequency synthesis |
| CN110336711A (en) * | 2019-06-13 | 2019-10-15 | 苏州中科集成电路设计中心有限公司 | A kind of the check and evaluation method and its realization device of carrier communication signal quality |
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| CN102577128A (en) * | 2009-06-03 | 2012-07-11 | 意法爱立信有限公司 | Frequency offset correction |
| CN203327019U (en) * | 2013-06-07 | 2013-12-04 | 国家电网公司 | High power signal transmission device based on underground cable comprehensive detection system |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102577128A (en) * | 2009-06-03 | 2012-07-11 | 意法爱立信有限公司 | Frequency offset correction |
| CN203327019U (en) * | 2013-06-07 | 2013-12-04 | 国家电网公司 | High power signal transmission device based on underground cable comprehensive detection system |
Non-Patent Citations (1)
| Title |
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| 刘刚等: "基于Virtex-7 FPGA的2.4G无线信号检测系统的设计与实现", 《中国科技论文在线》 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106603073A (en) * | 2016-11-24 | 2017-04-26 | 中国电子科技集团公司第四十研究所 | Integrated single-loop system for achieving low-phase-noise microwave broadband frequency synthesis |
| CN106603073B (en) * | 2016-11-24 | 2021-04-27 | 中国电子科技集团公司第四十一研究所 | Integrated single-ring system for realizing low-phase-noise microwave wide-band frequency synthesis |
| CN110336711A (en) * | 2019-06-13 | 2019-10-15 | 苏州中科集成电路设计中心有限公司 | A kind of the check and evaluation method and its realization device of carrier communication signal quality |
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