CN102751983B - Multi-loop synthesized local oscillation device of TD-LTE (time division-long term evolution) comprehensive test instrument - Google Patents
Multi-loop synthesized local oscillation device of TD-LTE (time division-long term evolution) comprehensive test instrument Download PDFInfo
- Publication number
- CN102751983B CN102751983B CN201210265791.1A CN201210265791A CN102751983B CN 102751983 B CN102751983 B CN 102751983B CN 201210265791 A CN201210265791 A CN 201210265791A CN 102751983 B CN102751983 B CN 102751983B
- Authority
- CN
- China
- Prior art keywords
- circuit
- output
- input
- frequency
- controlled oscillator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The invention relates to a multi-loop synthesized local oscillation device of a TD-LTE (time division-long term evolution) comprehensive test instrument, comprising an FPGA (field programmable gate array) controller of which an output end is respectively connected with an input end of a direct digital synthetic circuit and an input end of an eccentric loop circuit. The output ends of the direct digital synthetic circuit, a DAC (digital-to-analog converter) presetting circuit and a eccentric loop circuit are all connected with the input end of a main loop circuit, a first voltage-controlled oscillator (VCO) is adopted by the main loop circuit and a second VCO is adopted by the eccentric loop circuit. According to the requirement of a radiofrequency conformance test device of the TD-LTE terminal, the main loop circuit and the eccentric loop circuit constitute a multi-loop structure which uses the VCO with low cost. According to the invention, high purity, high resolution ratio and low cost can be guaranteed, and the radiofrequency design index of the TD-LTE comprehensive test instrument can be simultaneously ensured to meet the requirement of 3GPP. Besides, the device also can be referred in the other frequency synthesis situations with strong generality.
Description
Technical field
The present invention relates to TD-LTE terminal radio frequency consistency Test Application field, especially a kind of many cyclizations of TD-LTE comprehensive test instrument become local oscillation device.
Background technology
In to the various detections of mobile communication base station and end product and checking, RF consistency test is a ring of most critical wherein.3GPP TS36.521/TS36.141 has defined whole test cases of TD-LTE base station and terminal, requires TD-LTE terminal radio frequency consistency testing equipment output frequency resolution rate 1Hz; Output error amplitude of the vector EVM(error vector magnitude) be less than 3%; In receiver EVM certainty of measurement be better than ± 1%.These several indexs all depend on high performance synthetic local oscillation device, its high-resolution has been guaranteed 1Hz frequency resolution, when its high-purity has guaranteed that the signal frequency conversion that receives is to intermediate frequency, signal to noise ratio remains unchanged, guarantee that the signal to noise ratio of LTE signal of transmitting is far away higher than equipment under test, make to receive and the EVM of transmitter itself and error rate index far above 3GPP requirement.
The phase noise of synthetic local oscillation device is the critical index of restriction transmitter and receiver, is also to weigh one of Yi Ge research institute, the level of an instrument and important symbol of class.In TD-LTE comprehensive test instrument, the phase noise index of synthetic local oscillation device directly affects the test results such as EVM, the error rate, and the resolution of synthetic local oscillation device has determined that signal receives and the frequency resolution of transmitting.The existing synthetic local oscillation device with the higher index of making an uproar mutually all adopts the Oscillator based on YTO(YIG Tuning at present), be yig tuned oscillator, wherein, YIG (Yttrium Iron Garnet) refers to yttrium iron garnet, this conceptual design is complicated, and cost is higher; In addition, use VCO(voltage controlled oscillator) design synthetic local oscillation device be used for greatly in low side, Eco-power product.How with Eco-power VCO, to design high performance local oscillator, have the higher index of making an uproar mutually, for not only focusing on high target but also focusing on cheaply comprehensive test instrument extremely urgent.
Summary of the invention
The many cyclizations that the object of the present invention is to provide a kind of low cost, have a TD-LTE comprehensive test instrument of higher phase noise objective become local oscillation device.
For achieving the above object, the present invention has adopted following technical scheme: a kind of many cyclizations of TD-LTE comprehensive test instrument become local oscillation device, comprise FPGA controller, its output is connected with the input of direct digital synthesis circuit, biasing loop circuit respectively, the output of direct digital synthesis circuit, DAC prewired circuit and biasing loop circuit is all connected with the input of main ring circuit, main ring circuit adopts the first voltage controlled oscillator VCO, and biasing loop circuit adopts the second voltage controlled oscillator VCO.
As shown from the above technical solution, the present invention is according to the requirement of TD-LTE terminal radio frequency consistency testing equipment, utilize main ring circuit and biasing loop circuit to form multiring structure, and this multiring structure adopts lower-cost voltage controlled oscillator VCO, guaranteeing high-purity, high-resolution, simultaneously cheaply, guaranteed that the radio frequency design index of TD-LTE comprehensive test instrument meets 3GPP requirement.In addition, this device also can be referred from other frequency synthesis occasion, has stronger versatility.
Accompanying drawing explanation
Fig. 1 is system principle diagram of the present invention.
When Fig. 2 is offset carrier 1kHz of the present invention, phase noise measurement result schematic diagram.
When Fig. 3 is offset carrier 10kHz of the present invention, phase noise measurement result schematic diagram.
Embodiment
A kind of many cyclizations of TD-LTE comprehensive test instrument become local oscillation device, comprise FPGA controller 1, its output is connected with the input of direct digital synthesis circuit 2, biasing loop circuit 3 respectively, the output of direct digital synthesis circuit 2, DAC prewired circuit 5 and biasing loop circuit 3 is all connected with the input of main ring circuit 4, main ring circuit 4 adopts the first voltage controlled oscillator VCO, biasing loop circuit 3 adopts the second voltage controlled oscillator VCO, as shown in Figure 1, FPGA controller 1 completes the logic control of whole device, as shown in Figure 1.
As shown in Figure 1, described direct digital synthesis circuit 2 comprises phase accumulator, its input is connected with the output of FPGA controller 1, its output is connected with the input of D/A converter, the output of D/A converter is connected with the input of main ring circuit 4, direct digital synthesis circuit 2 is realized the fractional frequency division of whole local oscillator, guarantees to realize higher frequency resolution (1Hz).The output of described FPGA controller 1 is connected with the input of DAC prewired circuit 5, and the output of DAC prewired circuit 5 is connected with the input of the first voltage controlled oscillator VCO of main ring circuit 4.DAC prewired circuit 5 presetly guarantees main ring circuit 4 quick lock ins and avoids producing wrong lock to main ring circuit 4 with meticulous, described DAC prewired circuit 5 is D/A converter.
As shown in Figure 1, described main ring circuit 4 comprises the first phase discriminator, its input is connected with the output of direct digital synthesis circuit 2, its output is connected with the input of the first voltage controlled oscillator VCO by the first low pass filter, the local frequency scope of the first described voltage controlled oscillator VCO output is 1.6～3.2GHz, the output of the first voltage controlled oscillator VCO divides the input of match circuit to be connected with the first merit, the first merit divides the output of match circuit and the input of mixting circuit to be connected, the output of mixting circuit is connected with the input of intermediate frequency amplifier circuit, the output of intermediate frequency amplifier circuit is connected with the input of fixed frquency divider, the output of fixed frquency divider is connected with the input of phase discriminator.Mixting circuit is the binding site of main ring circuit 4 and biasing loop circuit 3, realizes frequency translation, the index that guarantees to make an uproar mutually without worsening translation, thereby making an uproar mutually of having avoided that frequency multiplication brings significantly worsens.Intermediate frequency amplifier circuit is adjusted mixing and is outputed to the reliably working that a suitable amplitude is beneficial to fixed frquency divider.Main ring circuit 4 is to be based upon biasing loop circuit 3 to have reduced on the basis of frequency, utilizes the matching of multistage loop parameter, debugs out the desirable index performance of making an uproar mutually.The first described low pass filter is formed by a passive second order wideband low pass filter and an active second order filter cascade, utilize passive second order wideband low pass filter to guarantee making an uproar mutually of 10kHz～100kHz place, utilize the index of making an uproar mutually at the narrow-band characteristic assurance near-end 1kHz place of active second order filter.
As shown in Figure 1, described biasing loop circuit 3 comprises integrated phase discriminator, its input is connected with the output of FPGA controller 1, its output is connected with the input of the second voltage controlled oscillator VCO by the second low pass filter, the local frequency scope of the second described voltage controlled oscillator VCO output is 1.4～3GHz, the output of the second voltage controlled oscillator VCO divides the input of match circuit to be connected with the second merit, the output that the second merit is divided match circuit respectively with the mixting circuit of main ring circuit 4, the input of 2 frequency dividers is connected, the output of 2 frequency dividers is connected with the input of integrated phase discriminator.Described integrated phase discriminator comprises first and second frequency divider, the input termination 100MHZ signal of the first frequency divider, the input of the second frequency divider is connected with the output of FPGA controller 1, the output of first and second frequency divider is all connected with the input of the second phase discriminator, and the second phase discriminator is connected with the input of low pass filter by charge pump.Biasing loop circuit 3 provides the offset frequency of 1.4GHz～3.0GHz for main ring circuit 4, realizes the overall offset of basic frequency, to improving making an uproar mutually of whole local oscillator, plays vital effect.The index of biasing loop circuit 3 depends on high reference, integral frequency divisioil etc. because usually guaranteeing.
Below in conjunction with Fig. 1,2,3 the present invention is further illustrated.
This device utilizes direct digital frequency synthesis technology to realize fractional frequency division, guarantees that local oscillator output frequency has higher frequency resolution.Direct digital synthesis circuit 2 is a kind of frequency synthesis techniques from the directly synthetic required waveform of phase place concept.A Direct Digital Frequency Synthesizers consists of phase accumulator, sine lookup table (ROM), D/A converter and low pass filter.Under the driving of reference clock, phase accumulator carries out linear superposition to frequency control word, the phase code obtaining is to look-up table addressing, make it to export corresponding amplitude code, through D/A converter, obtain corresponding staircase waveform, finally use low pass filter to carry out smoothly, obtaining level and smooth, the continuous waveform of required frequency to it.
This device utilizes 10 D/A converters, and its phase accumulator figure place (being frequency resolution) is 32.According to Direct Digital composite formula
In above formula, " FTW " represents DDS frequency control word, " f
dDS" represent that DDS output frequency, N represent that the position of DDS frequency control word is long, equal 32 here, " f
r" represent DDS reference clock, this device by outside provide 100MHz reference frequency as reference clock.According to formula above, as long as provide the output frequency of expectation, can calculate frequency control word FTW, by FPGA controller 1, by parallel loading, realize frequency output.
Reference frequency by the output frequency of DDS as major loop phase demodulation.The resolution that can calculate DDS output frequency according to formula (1) is 0.023Hz, because
so the resolution of main ring output frequency is 0.23Hz, meet the requirement that frequency resolution is 1Hz.The output frequency of this matching requirements DDS meets following formula:
（3）
Biasing loop circuit 3 provides the offset frequency of 1.4GHz～3.0GHz for main ring circuit 4, realizes the integral shift of basic frequency, reduces the deterioration of making an uproar mutually that main ring circuit 4 brings due to frequency-doubled effect.The loop circuit 3 of simultaneously setovering is made an uproar mutually and is played vital effect to improving making an uproar mutually of whole local oscillator.The index of making an uproar mutually of main ring circuit 4 be based upon biasing loop circuit 3 basis on, if the single-side belt phase noise that the main ring circuit of design 4 requires is-100dBc/Hz@10kHz that biasing loop circuit 3 single-side belt phase noises should meet <-106dBc/Hz@10kHz.In order to meet the index of making an uproar mutually of biasing loop circuit 3, this device selects integrated low phase noise frequency synthesizer as prescalar and the phase discriminator of biasing ring 3.Because the integrated low phase noise frequency synthesizer operating frequency upper limit is 2.8GHz, and the frequency of biasing loop circuit 3 output 1.4GHz～3.0GHz, so insert 2 frequency dividers at biasing loop circuit 3, makes the incoming frequency of integrated low phase noise frequency synthesizer lower than 2.8GHz.Biasing loop circuit 3 output frequencies
, wherein N is the integral frequency divisioil number that FPGA controller 1 send.
The output of direct digital synthesis circuit 2 output signals and biasing loop circuit 3 all enters main ring circuit 4, main ring circuit 4 provides the output frequency of 1.6～3.2GHz, mixting circuit is the binding site of main ring circuit 4 and biasing loop circuit 3, realize frequency translation, the deterioration of making an uproar mutually that the translation of index has avoided frequency multiplication to bring thereby assurance is made an uproar mutually.
Main ring circuit 4 is to be based upon biasing ring 3 circuit to have reduced on the basis of frequency.If do not setover loop circuit 3, main ring circuit 4 is because frequency-doubled effect is made an uproar mutually by deterioration 20log(3200/100)=30dBc/Hz, increase the rear main ring circuit 4 of biasing loop circuit 3 because frequency-doubled effect is made an uproar mutually by deterioration 20log10=20dBc/Hz.Therefore utilize 3 mixing of biasing loop circuit to realize frequency translation, the translation of index guarantees to make an uproar mutually, reduce the deterioration (having optimized 10dB) of making an uproar mutually bringing due to frequency-doubled effect, due to the noise signals such as spuious, harmonic wave that loop filter adopts the mode filtering high fdrequency component of cascade and introduced by phase discriminator, institute is so that the frequency that this device is finally exported has extremely low phase noise.
In addition; in order to realize the quick lock in of main ring circuit 4 and to avoid producing wrong lock; increased DAC prewired circuit 5; the preset voltage that DAC prewired circuit 5 provides can be preset to the frequency of oscillation of the first voltage controlled oscillator VCO exactly specifies near frequency; reduce to control the time of integration of voltage, can guarantee loop quick lock in and avoid producing wrong lock.
Utilize high performance spectrum analyzer to carry out the test of single-side belt phase noise to the output frequency of this device, select output frequency 2.825GHz, this point approaches high-end, if select the output frequency point of low side, test index can be better.Fig. 2 is making an uproar mutually while measuring offset carrier 1kHz, the scanning span SPAN of frequency spectrograph is set to 5kHz, value of making an uproar mutually while selecting frequency spectrograph directly to read offset carrier 1kHz, see that the measured value that the frequency spectrograph upper right corner shows is offset carrier (X) 1kHz, the measured value (Y) of making an uproar is mutually-107.15dBc/Hz.
Fig. 3 is making an uproar mutually while measuring offset carrier 10kHz, the scanning span SPAN of frequency spectrograph is set to 50kHz, value of making an uproar mutually while selecting frequency spectrograph directly to read offset carrier 10kHz, see that the measured value that the frequency spectrograph upper right corner shows is offset carrier (X) 10kHz, the measured value (Y) of making an uproar is mutually-104.03dBc/Hz.
From test result shown in Fig. 2, Fig. 3, this device meets the index request of TD-LTE comprehensive test instrument local oscillator.
Claims (5)
1. many cyclizations of a TD-LTE comprehensive test instrument become local oscillation device, it is characterized in that: comprise FPGA controller (1), its output is connected with the input of direct digital synthesis circuit (2), biasing loop circuit (3) respectively, the output of direct digital synthesis circuit (2), DAC prewired circuit (5) and biasing loop circuit (3) is all connected with the input of main ring circuit (4), main ring circuit (4) adopts the first voltage controlled oscillator VCO, and biasing loop circuit (3) adopts the second voltage controlled oscillator VCO, described direct digital synthesis circuit (2) comprises phase accumulator, and its input is connected with the output of FPGA controller (1), and its output is connected with the input of D/A converter, and the output of D/A converter is connected with the input of main ring circuit (4), described main ring circuit (4) comprises the first phase discriminator, its input is connected with the output of direct digital synthesis circuit (2), its output is connected with the input of the first voltage controlled oscillator VCO by the first low pass filter, the output of the first voltage controlled oscillator VCO divides the input of match circuit to be connected with the first merit, the first merit divides the output of match circuit and the input of mixting circuit to be connected, the output of mixting circuit is connected with the input of intermediate frequency amplifier circuit, the output of intermediate frequency amplifier circuit is connected with the input of fixed frquency divider, the output of fixed frquency divider is connected with the input of phase discriminator, described biasing loop circuit (3) comprises integrated phase discriminator, its input is connected with the output of FPGA controller (1), its output is connected with the input of the second voltage controlled oscillator VCO by the second low pass filter, the output of the second voltage controlled oscillator VCO divides the input of match circuit to be connected with the second merit, the second merit divides the output of match circuit to be connected with the mixting circuit of main ring circuit (4), the input of 2 frequency dividers respectively, and the output of 2 frequency dividers is connected with the input of integrated phase discriminator.
2. many cyclizations of TD-LTE comprehensive test instrument according to claim 1 become local oscillation device, it is characterized in that: the output of described FPGA controller (1) is connected with the input of DAC prewired circuit (5), the output of DAC prewired circuit (5) is connected with the input of the first voltage controlled oscillator VCO of main ring circuit (4), and described DAC prewired circuit (5) is D/A converter.
3. many cyclizations of TD-LTE comprehensive test instrument according to claim 1 become local oscillation device, it is characterized in that: described integrated phase discriminator comprises first and second frequency divider, the input termination 100MHZ signal of the first frequency divider, the input of the second frequency divider is connected with the output of FPGA controller (1), the output of first and second frequency divider is all connected with the input of the second phase discriminator, and the second phase discriminator is connected with the input of low pass filter by charge pump.
4. many cyclizations of TD-LTE comprehensive test instrument according to claim 1 become local oscillation device, it is characterized in that: the local frequency scope of the first described voltage controlled oscillator VCO output is 1.6～3.2GHz, and the first described low pass filter is formed by a passive second order wideband low pass filter and an active second order filter cascade.
5. many cyclizations of TD-LTE comprehensive test instrument according to claim 1 become local oscillation device, it is characterized in that: the local frequency scope of the second described voltage controlled oscillator VCO output is 1.4～3GHz.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210265791.1A CN102751983B (en) | 2012-07-30 | 2012-07-30 | Multi-loop synthesized local oscillation device of TD-LTE (time division-long term evolution) comprehensive test instrument |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210265791.1A CN102751983B (en) | 2012-07-30 | 2012-07-30 | Multi-loop synthesized local oscillation device of TD-LTE (time division-long term evolution) comprehensive test instrument |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102751983A CN102751983A (en) | 2012-10-24 |
| CN102751983B true CN102751983B (en) | 2014-10-22 |
Family
ID=47031916
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210265791.1A Active CN102751983B (en) | 2012-07-30 | 2012-07-30 | Multi-loop synthesized local oscillation device of TD-LTE (time division-long term evolution) comprehensive test instrument |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102751983B (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103633997B (en) * | 2013-11-18 | 2016-08-17 | 中国电子科技集团公司第四十一研究所 | TD-LTE-Advanced comprehensive test instrument synthesizes local oscillation device |
| CN105049036B (en) * | 2015-07-30 | 2018-08-14 | 中国电子科技集团公司第四十一研究所 | A kind of wideband low noise signal generator |
| CN106559075B (en) * | 2015-09-30 | 2019-11-26 | 中星联华科技（北京）有限公司 | Numerical frequency source generator |
| US11283557B2 (en) * | 2017-04-28 | 2022-03-22 | Panasonic Intellectual Property Corporation Of America | Measurement apparatus and measurement method |
| CN107968651B (en) * | 2017-11-20 | 2021-12-17 | 成都中创锐科信息技术有限公司 | Broadband signal generator |
| CN109613336B (en) * | 2018-12-07 | 2020-12-01 | 中国电子科技集团公司第四十一研究所 | Frequency domain analysis device and method for FFT (fast Fourier transform) multimode signals with any length |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101958757A (en) * | 2010-09-02 | 2011-01-26 | 湖北众友科技实业股份有限公司 | Method and device for testing radio-frequency performance of TD-LTE terminal |
| CN202750070U (en) * | 2012-07-30 | 2013-02-20 | 中国电子科技集团公司第四十一研究所 | Polycyclic synthetic local oscillator device of time division long term evolution (TD-LTE) tester |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9065537B2 (en) * | 2002-09-03 | 2015-06-23 | Broadcom Corporation | Method and system for calibrating a multi-mode, multi-standard transmitter and receiver |
| EP2360835B1 (en) * | 2010-02-19 | 2012-12-05 | TELEFONAKTIEBOLAGET LM ERICSSON (publ) | Down-conversion using square wave local oscillator signals |
| US20110299634A1 (en) * | 2010-06-03 | 2011-12-08 | Broadcom Corporation | Saw-less receiver with a frequency translated bpf having a negative resistance |
-
2012
- 2012-07-30 CN CN201210265791.1A patent/CN102751983B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101958757A (en) * | 2010-09-02 | 2011-01-26 | 湖北众友科技实业股份有限公司 | Method and device for testing radio-frequency performance of TD-LTE terminal |
| CN202750070U (en) * | 2012-07-30 | 2013-02-20 | 中国电子科技集团公司第四十一研究所 | Polycyclic synthetic local oscillator device of time division long term evolution (TD-LTE) tester |
Non-Patent Citations (3)
| Title |
|---|
| Design and Implementation of Primitive Tracking for TD-LTE Wireless Integrated Testing Instrument;Fatang Chen,Liuwei Shi;《2011 IEEE 2nd International Conference on Computing, Control and Industrial Engineering(CCIE2011)》;20110820;第186-189页 * |
| FatangChen Liuwei Shi.Design and Implementation of Primitive Tracking for TD-LTE Wireless Integrated Testing Instrument.《2011 IEEE 2nd International Conference on Computing |
| 陈发堂，杨林雨.TD-LTE综合测试仪表基带信号生成的研究与现实.《现代电信科技》.2011,(第6期),第18-22页. * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102751983A (en) | 2012-10-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102751983B (en) | Multi-loop synthesized local oscillation device of TD-LTE (time division-long term evolution) comprehensive test instrument | |
| CN105187060B (en) | The phase-locked loop circuit and its implementation of a kind of low phase noise | |
| CN104320137B (en) | A kind of phase-locked loop frequency synthesizer | |
| US20140327478A1 (en) | Wideband frequency synthesizer and frequency synthesizing method thereof | |
| CN204131498U (en) | A kind of phase-locked loop frequency synthesizer | |
| CN105978562B (en) | Super Low phase noise and the high-frequency narrow-band of ultra-high frequency resolution ratio synthesis source circuit and method | |
| CN105187059A (en) | Wideband and low-phase noise local frequency synthesizing circuit and method | |
| CN105406864B (en) | A kind of broadband high-speed Frequency Hopping Synthesizer and its working method | |
| CN103762978A (en) | Broadband low-phase noise frequency synthesizer without frequency divider based on harmonic mixing | |
| CN102651649A (en) | Design method of low-phase-noise microwave wideband frequency combiner | |
| CN105245224A (en) | Low-phase noise microwave local oscillation generating device and method | |
| CN105071804A (en) | Low phase noise wideband microwave local oscillator source circuit and realization method thereof | |
| Rong et al. | A 0.05-to 10-GHz, 19-to 22-GHz, and 38-to 44-GHz Frequency Synthesizer for Software-Defined Radios in 0.13-$\mu\mbox {m} $ CMOS Process | |
| CN109391266A (en) | A kind of hybrid frequency synthesizer based on orthogonal modulation | |
| CN108988857A (en) | A kind of broadband low phase noise frequency synthesizer and method based on optical-electronic oscillator | |
| CN105375922A (en) | Microwave signal source used for miniature atomic clock | |
| CN110289858B (en) | Broadband fine stepping agile frequency conversion combination system | |
| CN201541235U (en) | Microwave signal source module | |
| CN202750070U (en) | Polycyclic synthetic local oscillator device of time division long term evolution (TD-LTE) tester | |
| CN106209089A (en) | A kind of single loop frequency division type broadband frequency synthesizer of phase locking | |
| CN107196653B (en) | Broadband low-phase noise frequency synthesizer | |
| CN101834620B (en) | Broadband receiver with phase-locked loop local oscillation circuit | |
| CN205647494U (en) | Ultra wide band low phase noise hangs down stray frequency synthesizer | |
| CN110729996B (en) | Miniaturized phase-locked loop circuit and method for twice phase locking | |
| CN204103898U (en) | A kind of frequency synthesizer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20190318 Address after: 266000 No. 98 Xiangjiang Road, Huangdao District, Qingdao City, Shandong Province Patentee after: China Electronics Technology Instrument and Meter Co., Ltd. Address before: 233006 Mailbox 101, 726 Zhengzheng Road, Bengbu City, Anhui Province Patentee before: The 41st Institute of CETC |
|
| CP01 | Change in the name or title of a patent holder | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 266000 No. 98 Xiangjiang Road, Huangdao District, Qingdao City, Shandong Province Patentee after: CLP kesiyi Technology Co.,Ltd. Address before: 266000 No. 98 Xiangjiang Road, Huangdao District, Qingdao City, Shandong Province Patentee before: CHINA ELECTRONIC TECHNOLOGY INSTRUMENTS Co.,Ltd. |