CN105720947A

CN105720947A - Oscillator with ultralow power consumption

Info

Publication number: CN105720947A
Application number: CN201610042262.3A
Authority: CN
Inventors: 方镜清
Original assignee: ZHONGSHAN XINDA ELECTRONIC TECHNOLOGY Co Ltd
Current assignee: ZHONGSHAN XINDA ELECTRONIC TECHNOLOGY Co Ltd
Priority date: 2016-01-21
Filing date: 2016-01-21
Publication date: 2016-06-29
Anticipated expiration: 2036-01-21
Also published as: CN105720947B

Abstract

The invention provides an oscillator with ultralow power consumption. The oscillator is characterized in that an oscillation-starting circuit provided with a first terminal and a second terminal and used for receiving clock signals for starting the oscillation, a bias circuit used for generating a bias voltage for the second terminal of the oscillation-starting circuit in order to reduce the oscillation amplitude of an oscillation circuit, a boosting circuit used for output and boosting of oscillation signals, and an output circuit, and a plurality of nodes mutually connected in a staggered manner are arranged between the oscillation-starting circuit and the boosting circuit. According to the oscillator, the staggered wiring method different from the conventional scheme is adopted, in-phase control of the oscillation-starting circuit and the boosting circuit is realized, the problem of short circuit current in the conventional electronic circuit is solved, high short circuit current during on-off switch of components is avoided, and an important effect is exerted on the reduction of the power consumption of the circuit and the improvement of the stability of the circuit; besides, the boosting circuit is provided so that the oscillation amplitude of the circuit can be reduced, and the power consumption of the overall circuit of the oscillator is further reduced.

Description

A kind of super low-power consumption agitator

Technical field

The invention belongs to microelectronic circuit arts field, be specifically related to a kind of super low-power consumption agitator.

Background technology

Along with the development of microelectric technique, microelectronic circuit is also more and more stronger to the demand of low-power consumption, high stable.Such as, just require that battery can have the use time permanent as far as possible at operating heart heartstart, even wish within the whole product life cycle all without changing battery.The means extending service time of battery are increase battery capacity nothing more than two kinds: one；Two is rely on Low-power Technology, lowers and control the power consumption of integrated circuit；The former room for promotion is limited, especially for this kind of tiny device of heart heartstart, so the latter will be the study frontier of the art.

In this kind of microelectronics system, agitator is to produce the requisite part of system clock, therefore its power consumption control is particularly critical, can the operating frequency of control realization agitator be more low, power consumption is more low then desirable for it, general way is to utilize Low-power Technology means so that service intermittent time-count cycle of agitator, but there is obvious defect in such way: common based on RC(resistance capacitance) agitator, if requiring that frequency of oscillation is relatively low, then need resistance and the electric capacity of higher value, chip area so not only can be made excessive, and cost also greatly increases.There are many application operating frequencies also cannot be down to too low.Therefore, it is necessary to propose a kind of new low-power consumption agitator scheme to overcome the problems referred to above.

Summary of the invention

Based on problem mentioned in background technology, the present invention proposes a kind of super low-power consumption agitator, meets the microelectronic circuit demand to low-power consumption, high stable, and its concrete technical scheme is as follows:

A kind of super low-power consumption agitator, including

Start-oscillation circuit；Initiate vibration for receiving clock enabling signal, this start-oscillation circuit has the first end and the second end, and its first end connects DC source VEE, and the second end is connected with biasing circuit；

Biasing circuit；For producing the bias voltage of the second end to this start-oscillation circuit, to reduce the oscillation amplitude of oscillating circuit, this biasing circuit has the first end and the second end, and its first end connects DC source VEE, and the second end connects signal ground end VSS；

Pressure-raising circuit；For the output pressure-raising of oscillator signal, this pressure-raising circuit has the first end and the second end, and its first end connects DC source VEE, and the second end connects signal ground end VSS；And

Output circuit；This output circuit has the first end, the second end and outfan, and its first end connects DC source VEE, and the second end connects signal ground end VSS；

There are between this start-oscillation circuit, biasing circuit and pressure-raising circuit several nodes being crossed-over.

In the middle of one or more embodiments of the invention, described start-oscillation circuit includes elements below:

First PMOS, the second PMOS, the first NMOS tube and the second NMOS tube concatenation are connected between this first end and second end, wherein, the grid of the first PMOS and the grid of the second NMOS tube are connected to a B, the grid of the second PMOS and the grid of the first NMOS tube are connected to a C, and the second PMOS is connected in series a little for an A with the first NMOS tube；

3rd PMOS, the 4th PMOS, the 3rd NMOS tube, the 4th NMOS tube and the 11st NMOS tube concatenation are connected between this first end and second end, wherein, the grid of the 3rd PMOS and the grid of the 4th NMOS tube are connected to a C, the grid of the 4th PMOS and the grid of the 3rd NMOS tube are connected to a D, 4th PMOS is some a some B with being connected in series of the 3rd NMOS tube, and the grid of the 11st NMOS tube is connected to a W；

5th PMOS, the 6th PMOS, the 5th NMOS tube and the 6th NMOS tube concatenation are connected between this first end and second end, wherein, the grid of the 5th PMOS and the grid of the 6th NMOS tube are connected to a D, the grid of the 6th PMOS and the grid of the 5th NMOS tube are connected to an E, and the 6th PMOS is connected in series a little for a C with the 5th NMOS tube；

16th PMOS, the 7th PMOS, the 8th PMOS, the 7th NMOS tube and the 8th NMOS tube concatenation are connected between this first end and second end, wherein, the grid of the 7th PMOS and the grid of the 8th NMOS tube are connected to an E, the grid of the 8th PMOS and the grid of the 7th NMOS tube are connected to an A, 8th PMOS is some a some D with being connected in series of the 7th NMOS tube, and the grid of the 16th NMOS tube is connected to an X；

17th PMOS, the 9th PMOS, the tenth PMOS, the 9th NMOS tube and the tenth NMOS tube concatenation are connected between this first end and second end, wherein, the grid of the 9th PMOS and the grid of the tenth NMOS tube are connected to an A, the grid of the tenth PMOS and the grid of the 9th NMOS tube are connected to a B, tenth PMOS is some a some E with being connected in series of the 8th NMOS tube, and the grid of the 17th NMOS tube is connected to an X；

18th PMOS is connected between described first end and some B, and its grid is connected to a W；

19th PMOS and the tenth point of NMOS tube are connected in series between described first end and VSS end, and the grid of the two is connected to a W, and being connected in series of the two is a little connected to an X；

16th NMOS tube is connected between an E and described second end, and the 17th NMOS tube is connected between a D and described second end, and the grid of the 16th NMOS tube and the grid of the 17th NMOS tube are connected to an X.

In the middle of one or more embodiments of the invention, described pressure-raising circuit includes elements below:

26th PMOS, the 27th PMOS and the 23rd NMOS tube are connected between the first end and the second end, the grid of the 26th PMOS is connected to a B, the grid of the 27th PMOS is connected to a C, and the 27th PMOS and being connected in series of the 23rd NMOS tube are a little connected to a M；

24th PMOS, the 25th PMOS and the 22nd NMOS tube are connected between the first end and the second end, and the grid of the 24th PMOS is connected to an E, and the grid of the 25th PMOS is connected to an A；

22nd PMOS, the 23rd PMOS and the 21st NMOS tube are connected between the first end and the second end, and the grid of the 22nd PMOS is connected to a C, and the grid of the 23rd PMOS is connected to an E；

20th PMOS, the 21st PMOS and the 20th NMOS tube are connected between the first end and the second end, the grid of the 20th PMOS is connected to a C, the grid of the 21st PMOS is connected to a D, and the 21st PMOS and being connected in series of the 20th NMOS tube are a little connected to a N；

The grid of the 22nd NMOS tube is connected to a M, and the grid of the 20th NMOS tube and the grid of the 21st NMOS tube are commonly connected to being connected in series a little of the 25th PMOS and the 22nd NMOS tube；

In the middle of one or more embodiments of the invention, described biasing circuit includes elements below:

31st PMOS, the 30th NMOS tube, the 32nd NMOS tube and the 27th NMOS tube are connected in series between the first end and the second end, wherein, the grid of the 31st PMOS and the grid of the 30th NMOS tube are connected to a F, 31st PMOS and being connected in series of the 30th NMOS tube are a little connected to a F, what the grid of the 32nd PMOS was connected to the 30th NMOS tube and the 32nd NMOS tube is connected in series a little, and the grid of the 27th NMOS tube is connected to an I；

35th NMOS tube is connected between the second end of start-oscillation circuit and the second end of pressure-raising circuit, and its grid is connected to an I；

29th NMOS tube is connected between the second end of start-oscillation circuit and the second end of pressure-raising circuit, and the grid of its grid and the 18th NMOS tube is commonly connected to an X, and the 18th NMOS tube and the 23rd NMOS tube are connected in parallel；

28th PMOS, the 29th PMOS and the 26th NMOS tube are connected in series between the first end and the second end, wherein, the grid of the 28th PMOS is connected to a F, and the grid of the 29th PMOS is connected to being connected in series a little of the 27th NMOS tube and the 32nd NMOS tube；

30th PMOS and the 25th NMOS tube are connected in series between the 28th PMOS and the second end, wherein, the grid of the 30th PMOS is connected to the 29th NMOS tube, it is connected to the 24th NMOS tube between grid and second end of the 30th PMOS, being connected to electric capacity C1 between grid and the grid of the 30th PMOS of the 24th NMOS tube, the grid of the 24th NMOS tube is connected to being connected in series a little of the 29th PMOS and the 26th NMOS tube.

In the middle of one or more embodiments of the invention, described output circuit includes elements below:

12nd PMOS, 13rd PMOS, 14th PMOS, 12nd NMOS tube and the 13rd NMOS tube are connected in series between the first end and the second end, wherein, the grid of the 12nd PMOS and the grid of the 13rd NMOS tube are connected to a M, the grid of the 13rd PMOS, the grid of the 14th PMOS and the grid of the 12nd NMOS tube are connected to a N, 13rd PMOS is connected in series a little for an I with the 14th PMOS, 14th PMOS is connected in series a little for a J with the 12nd NMOS tube, it is connected to the 14th NMOS tube between some I and some J, the grid of the 14th NMOS tube connects the grid of the 14th PMOS；

15th PMOS and the 15th NMOS tube are connected in series between the first end and the second end, 36th PMOS and the 36th NMOS tube are connected in series between the first end and the second end, the grid of the 15th PMOS is connected to an I, the grid of the 15th NMOS tube is connected to a J, what the grid of the 36th PMOS and the grid of the 36th NMOS tube were commonly connected to the 15th PMOS and the 15th NMOS tube is connected in series a little, the 36th PMOS and the 36th NMOS tube be connected in series a little output as circuit.

The present invention is compared with prior art, its advantageous exists: adopt the staggered mode of connection being different from traditional scheme, start-oscillation circuit and pressure-raising circuit are carried out same phase control, solve the short circuit current problem existed in conventional circuit, avoid components and parts to carry out big short circuit current when switch switches, reduction circuit power consumption and lifting circuit stability are had important effect；Simultaneously because the existence of pressure-raising circuit so that circuit oscillation amplitude can be reduced, thus reducing the power consumption of integral oscillation device circuit further.The present invention breaks away from the limitation of traditional circuit, adopt the super low-power consumption oscillator circuit structure of innovation, realize circuit persistently, stably run, greatly extend the use time of battery, no matter from practicality or economy, it is respectively provided with excellent performance, is particularly suitable on this kind of product that circuit power consumption requirement is strict of heart heartstart and uses.

Accompanying drawing explanation

Fig. 1 is the theory diagram of the super low-power consumption agitator of the present invention.

Fig. 2 is the circuit structure diagram of the super low-power consumption agitator of the present invention.

Detailed description of the invention

Below in conjunction with accompanying drawing 1 to 2, the application scheme is further described:

A kind of super low-power consumption agitator, including

Start-oscillation circuit 1；Initiate vibration for receiving clock signal, this start-oscillation circuit has the first end 101 and the second end 102, and its first end 101 connects DC source VEE, and the second end 102 is connected with biasing circuit 2；

Biasing circuit 2；For producing the bias voltage of the second end to this start-oscillation circuit 1, to reduce the oscillation amplitude of oscillating circuit 1, this biasing circuit 2 has the first end 201 and the second end 202, and its first end 201 connects DC source VEE, and the second end 202 connects signal ground end VSS；For 5V voltage, this biasing circuit 2 is equivalent to connect with start-oscillation circuit 1, and biasing circuit 2 by producing the bias voltage of about 3V, then makes the oscillation amplitude of start-oscillation circuit 1 be reduced to about 2V by 5V, the power consumed that so not only vibrates is reducing greatly, and low pressure vibration is conducive to stablizing of circuit；

Pressure-raising circuit 3；For the output pressure-raising of oscillator signal, this pressure-raising circuit 3 has the first end 301 and the second end 302, and its first end 301 connects DC source VEE, and the second end 302 connects signal ground end VSS；And

Output circuit 4；This output circuit 4 has first end the 401, second end 402 and outfan OSC1, OSC2, and its first end 401 connects DC source VEE, and the second end 402 connects signal ground end VSS；

Having several nodes being crossed-over between this start-oscillation circuit 1, biasing circuit 2 and pressure-raising circuit 3, those nodes include A, B, C, D, E, F, I, M, N, X, and some W is clock signal input node.

Described start-oscillation circuit 1 includes elements below:

Described pressure-raising circuit 3 includes elements below:

Elements below drawn together by described biasing circuit bag 2:

Described output circuit 4 includes elements below:

Above-mentioned preferred implementation should be regarded as the illustration of the application scheme embodiment, all identical with the application scheme, approximate or make based on this technology deduction, replacement, improvement etc., be regarded as the protection domain of this patent.

Claims

1. a super low-power consumption agitator, it is characterised in that: include

Start-oscillation circuit；Initiating vibration during for receiving clock enabling signal, this start-oscillation circuit has the first end and the second end, and its first end connects DC source VEE, and the second end is connected with biasing circuit；

2. super low-power consumption agitator according to claim 1, it is characterised in that described start-oscillation circuit includes elements below:

3. super low-power consumption agitator according to claim 1, it is characterised in that described pressure-raising circuit includes elements below:

The grid of the 22nd NMOS tube is connected to a M, and the grid of the 20th NMOS tube and the grid of the 21st NMOS tube are commonly connected to being connected in series a little of the 25th PMOS and the 22nd NMOS tube.

4. super low-power consumption agitator according to claim 1, it is characterised in that described biasing circuit includes elements below:

5. super low-power consumption agitator according to claim 1, it is characterised in that described output circuit includes elements below: