CN105720947A - An Ultra Low Power Oscillator - Google Patents

An Ultra Low Power Oscillator Download PDF

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CN105720947A
CN105720947A CN201610042262.3A CN201610042262A CN105720947A CN 105720947 A CN105720947 A CN 105720947A CN 201610042262 A CN201610042262 A CN 201610042262A CN 105720947 A CN105720947 A CN 105720947A
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pmos
nmos tube
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CN105720947B (en
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方镜清
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Zhongshan Xinda Electronic Technology Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption

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Abstract

The invention provides an ultra-low power consumption oscillator, which is characterized in that: comprises a starting oscillation circuit; the oscillation starting circuit is used for receiving a clock signal to start oscillation and is provided with a first end and a second end; a bias circuit; the bias voltage is used for generating a bias voltage to the second end of the oscillation starting circuit so as to reduce the oscillation amplitude of the oscillation circuit; a voltage boosting circuit; the output voltage raising device is used for outputting an oscillating signal; and an output circuit; a plurality of nodes which are connected in a staggered mode are arranged between the oscillation starting circuit and the voltage boosting circuit. The invention adopts a staggered connection mode different from the traditional scheme to carry out in-phase control on the oscillation starting circuit and the voltage boosting circuit, solves the problem of short-circuit current in the traditional electronic circuit, avoids large short-circuit current when components are switched, and plays an important role in reducing the power consumption of the circuit and improving the stability of the circuit; meanwhile, due to the existence of the voltage boosting circuit, the oscillation amplitude of the circuit can be reduced, and the power consumption of the whole oscillator circuit is further reduced.

Description

一种超低功耗振荡器An Ultra Low Power Oscillator

技术领域 technical field

本发明属于微电子电路技术领域，具体涉及一种超低功耗振荡器。 The invention belongs to the technical field of microelectronic circuits, and in particular relates to an ultra-low power consumption oscillator.

背景技术 Background technique

随着微电子技术的发展，微电子电路对低功耗、高稳定的需求也越来越强烈。例如，在外科手术的心脏起博器就要求电池能拥有尽可能长久的使用时间，甚至希望在整个产品生命周期内都无需更换电池。延长电池使用时间的手段不外乎两种：一是增大电池容量；二是依赖低功耗技术，减低和控制整体电路的电能消耗；前者的提升空间有限，特别是对于心脏起博器这类细小器件来讲，所以后者将是本技术领域的研究前沿。 With the development of microelectronic technology, the demand for low power consumption and high stability of microelectronic circuits is becoming stronger and stronger. For example, cardiac pacemakers in surgical operations require batteries to last as long as possible, and it is even hoped that the batteries will not need to be replaced during the entire product life cycle. There are no more than two ways to prolong battery life: one is to increase battery capacity; the other is to rely on low-power technology to reduce and control the power consumption of the overall circuit; the former has limited room for improvement, especially for cardiac pacemakers. In terms of small devices, the latter will be the research frontier in this technical field.

在这类微电子系统中振荡器是产生系统时钟必不可少的部分，因此它的功耗控制尤为关键，能够控制实现振荡器的工作频率越低、功耗越低则为之理想，一般的做法是利用低功耗技术手段以使振荡器的计时周期间歇式工作，但这样的做法存在明显的缺陷：普通基于RC（电阻电容）的振荡器，如果要求振荡频率较低，则需要较大值的电阻和电容，这样不仅会令芯片面积过大，而且成本也大为增加。有许多应用工作频率也不可以降至太低。因此，有必要提出一种新的低功耗振荡器方案来克服上述问题。 In this type of microelectronic system, the oscillator is an essential part of generating the system clock, so its power consumption control is particularly critical. It is ideal to control the lower the operating frequency of the oscillator and the lower the power consumption. Generally, The method is to use low power consumption technology to make the oscillator's timing cycle work intermittently, but this method has obvious defects: ordinary RC (resistor-capacitor)-based oscillators require a larger frequency if the oscillation frequency is lower. The value of resistors and capacitors will not only make the chip area too large, but also greatly increase the cost. There are many applications where the operating frequency cannot be reduced too low. Therefore, it is necessary to propose a new low-power oscillator solution to overcome the above problems.

发明内容 Contents of the invention

基于背景技术中所提及的问题，本发明提出一种超低功耗振荡器，满足微电子电路对低功耗、高稳定的需求，其具体技术方案如下： Based on the problems mentioned in the background technology, the present invention proposes an ultra-low power consumption oscillator to meet the requirements of microelectronic circuits for low power consumption and high stability. The specific technical solutions are as follows:

一种超低功耗振荡器，包括 An ultra-low power oscillator including

起振电路；用于接收时钟启动信号而发起振荡，该起振电路具有第一端和第二端，其第一端连接直流源VEE，第二端与偏置电路相连； An oscillating circuit; used to receive a clock start signal to initiate oscillation, the oscillating circuit has a first end and a second end, the first end of which is connected to a DC source VEE, and the second end is connected to a bias circuit;

偏置电路；用于产生对该起振电路的第二端的偏置电压，以降低振荡电路的振荡幅值，该偏置电路具有第一端和第二端，其第一端连接直流源VEE，第二端连接信号地端VSS； Bias circuit; used to generate a bias voltage to the second end of the oscillating circuit to reduce the oscillation amplitude of the oscillating circuit, the bias circuit has a first end and a second end, the first end of which is connected to the DC source VEE , the second terminal is connected to the signal ground terminal VSS;

提压电路；用于振荡信号的输出提压，该提压电路具有第一端和第二端，其第一端连接直流源VEE，第二端连接信号地端VSS；以及 A voltage boosting circuit; used for boosting the output of the oscillating signal, the voltage boosting circuit has a first end and a second end, the first end of which is connected to the DC source VEE, and the second end is connected to the signal ground terminal VSS; and

输出电路；该输出电路具有第一端、第二端和输出端，其第一端连接直流源VEE，第二端连接信号地端VSS； An output circuit; the output circuit has a first terminal, a second terminal and an output terminal, the first terminal of which is connected to the DC source VEE, and the second terminal is connected to the signal ground terminal VSS;

该起振电路、偏置电路和提压电路之间具有若干个相互交错连接的节点。 There are several interleaved nodes connected among the oscillation circuit, the bias circuit and the voltage boosting circuit.

于本发明的一个或多个实施例当中，所述起振电路包括有以下元件： In one or more embodiments of the present invention, the oscillation circuit includes the following components:

第一PMOS管、第二PMOS管、第一NMOS管和第二NMOS管串接连接于该第一端与第二端之间，其中，第一PMOS管的栅极与第二NMOS管的栅极连接于点B，第二PMOS管的栅极与第一NMOS管的栅极连接于点C，第二PMOS管与第一NMOS管的串联连接点为点A； The first PMOS transistor, the second PMOS transistor, the first NMOS transistor and the second NMOS transistor are connected in series between the first end and the second end, wherein the gate of the first PMOS transistor and the gate of the second NMOS transistor The pole is connected to point B, the gate of the second PMOS transistor is connected to the gate of the first NMOS transistor at point C, and the series connection point of the second PMOS transistor and the first NMOS transistor is point A;

第三PMOS管、第四PMOS管、第三NMOS管、第四NMOS管和第十一NMOS管串接连接于该第一端与第二端之间，其中，第三PMOS管的栅极与第四NMOS管的栅极连接于点C，第四PMOS管的栅极与第三NMOS管的栅极连接于点D，第四PMOS管与第三NMOS管的串联连接点为点B，第十一NMOS管的栅极连接于点W； The third PMOS transistor, the fourth PMOS transistor, the third NMOS transistor, the fourth NMOS transistor and the eleventh NMOS transistor are connected in series between the first end and the second end, wherein the gate of the third PMOS transistor is connected to the second end. The gate of the fourth NMOS transistor is connected to point C, the gate of the fourth PMOS transistor and the gate of the third NMOS transistor are connected to point D, and the series connection point of the fourth PMOS transistor and the third NMOS transistor is point B. The gate of eleven NMOS transistors is connected to point W;

第五PMOS管、第六PMOS管、第五NMOS管和第六NMOS管串接连接于该第一端与第二端之间，其中，第五PMOS管的栅极与第六NMOS管的栅极连接于点D，第六PMOS管的栅极与第五NMOS管的栅极连接于点E，第六PMOS管与第五NMOS管的串联连接点为点C； The fifth PMOS transistor, the sixth PMOS transistor, the fifth NMOS transistor and the sixth NMOS transistor are connected in series between the first end and the second end, wherein the gate of the fifth PMOS transistor and the gate of the sixth NMOS transistor The pole is connected to point D, the gate of the sixth PMOS transistor and the gate of the fifth NMOS transistor are connected to point E, and the series connection point of the sixth PMOS transistor and the fifth NMOS transistor is point C;

第十六PMOS管、第七PMOS管、第八PMOS管、第七NMOS管和第八NMOS管串接连接于该第一端与第二端之间，其中，第七PMOS管的栅极与第八NMOS管的栅极连接于点E，第八PMOS管的栅极与第七NMOS管的栅极连接于点A，第八PMOS管与第七NMOS管的串联连接点为点D，第十六NMOS管的栅极连接于点X； The sixteenth PMOS transistor, the seventh PMOS transistor, the eighth PMOS transistor, the seventh NMOS transistor and the eighth NMOS transistor are connected in series between the first end and the second end, wherein the gate of the seventh PMOS transistor is connected to the The gate of the eighth NMOS transistor is connected to point E, the gate of the eighth PMOS transistor and the gate of the seventh NMOS transistor are connected to point A, the series connection point of the eighth PMOS transistor and the seventh NMOS transistor is point D, and the gate of the eighth PMOS transistor and the seventh NMOS transistor is connected to point D. The gates of sixteen NMOS transistors are connected to point X;

第十七PMOS管、第九PMOS管、第十PMOS管、第九NMOS管和第十NMOS管串接连接于该第一端与第二端之间，其中，第九PMOS管的栅极与第十NMOS管的栅极连接于点A，第十PMOS管的栅极与第九NMOS管的栅极连接于点B，第十PMOS管与第八NMOS管的串联连接点为点E，第十七NMOS管的栅极连接于点X； The seventeenth PMOS transistor, the ninth PMOS transistor, the tenth PMOS transistor, the ninth NMOS transistor and the tenth NMOS transistor are connected in series between the first end and the second end, wherein the gate of the ninth PMOS transistor is connected to the The gate of the tenth NMOS transistor is connected to point A, the gate of the tenth PMOS transistor and the gate of the ninth NMOS transistor are connected to point B, the series connection point of the tenth PMOS transistor and the eighth NMOS transistor is point E, and the gate of the ninth NMOS transistor is connected to point E. The gate of the seventeenth NMOS transistor is connected to point X;

第十八PMOS管连接于所述第一端和点B之间，其栅极连接于点W； The eighteenth PMOS transistor is connected between the first end and point B, and its gate is connected to point W;

第十九PMOS管和第十分NMOS管串联连接于所述第一端和VSS端之间，二者的栅极连接于点W，二者的串联连接点连接于点X； The nineteenth PMOS transistor and the tenth NMOS transistor are connected in series between the first terminal and the VSS terminal, the gates of the two are connected to point W, and the series connection point of the two is connected to point X;

第十六NMOS管连接于点E和所述第二端之间，第十七NMOS管连接于点D和所述第二端之间，第十六NMOS管的栅极和第十七NMOS管的栅极连接于点X。 The sixteenth NMOS transistor is connected between the point E and the second end, the seventeenth NMOS transistor is connected between the point D and the second end, the gate of the sixteenth NMOS transistor and the seventeenth NMOS transistor The gate of is connected to point X.

于本发明的一个或多个实施例当中，所述提压电路包括有以下元件： In one or more embodiments of the present invention, the voltage boosting circuit includes the following components:

第二十六PMOS管、第二十七PMOS管和第二十三NMOS管连接于第一端和第二端之间，第二十六PMOS管的栅极连接于点B，第二十七PMOS管的栅极连接于点C，第二十七PMOS管与第二十三NMOS管的串联连接点连接于点M； The twenty-sixth PMOS transistor, the twenty-seventh PMOS transistor and the twenty-third NMOS transistor are connected between the first end and the second end, the gate of the twenty-sixth PMOS transistor is connected to point B, the twenty-seventh The gate of the PMOS transistor is connected to point C, and the series connection point of the twenty-seventh PMOS transistor and the twenty-third NMOS transistor is connected to point M;

第二十四PMOS管、第二十五PMOS管和第二十二NMOS管连接于第一端和第二端之间，第二十四PMOS管的栅极连接于点E，第二十五PMOS管的栅极连接于点A； The twenty-fourth PMOS transistor, the twenty-fifth PMOS transistor and the twenty-second NMOS transistor are connected between the first end and the second end, the gate of the twenty-fourth PMOS transistor is connected to point E, and the twenty-fifth The gate of the PMOS transistor is connected to point A;

第二十二PMOS管、第二十三PMOS管和第二十一NMOS管连接于第一端和第二端之间，第二十二PMOS管的栅极连接于点C，第二十三PMOS管的栅极连接于点E； The twenty-second PMOS transistor, the twenty-third PMOS transistor and the twenty-first NMOS transistor are connected between the first end and the second end, the gate of the twenty-second PMOS transistor is connected to point C, and the twenty-third The gate of the PMOS transistor is connected to point E;

第二十PMOS管、第二十一PMOS管和第二十NMOS管连接于第一端和第二端之间，第二十PMOS管的栅极连接于点C，第二十一PMOS管的栅极连接于点D，第二十一PMOS管与第二十NMOS管的串联连接点连接于点N； The 20th PMOS transistor, the 21st PMOS transistor and the 20th NMOS transistor are connected between the first end and the second end, the gate of the 20th PMOS transistor is connected to point C, and the gate of the 21st PMOS transistor The gate is connected to point D, and the series connection point of the twenty-first PMOS transistor and the twenty-first NMOS transistor is connected to point N;

第二十二NMOS管的栅极连接于点M，第二十NMOS管的栅极和第二十一NMOS管的栅极共同连接于第二十五PMOS管与第二十二NMOS管的串联连接点； The gate of the twenty-second NMOS transistor is connected to point M, and the gate of the twenty-first NMOS transistor is connected to the series connection of the twenty-fifth PMOS transistor and the twenty-second NMOS transistor. Junction;

于本发明的一个或多个实施例当中，所述偏置电路包括有以下元件： In one or more embodiments of the present invention, the bias circuit includes the following components:

第三十一PMOS管、第三十NMOS管、第三十二NMOS管和第二十七NMOS管串联连接于第一端和第二端之间，其中，第三十一PMOS管的栅极与第三十NMOS管的栅极连接于点F，第三十一PMOS管和第三十NMOS管的串联连接点连接至点F，第三十二PMOS管的栅极连接至第三十NMOS管和第三十二NMOS管的串联连接点，第二十七NMOS管的栅极连接于点I； The thirty-first PMOS transistor, the thirty-first NMOS transistor, the thirty-second NMOS transistor, and the twenty-seventh NMOS transistor are connected in series between the first end and the second end, wherein the gate of the thirty-first PMOS transistor The gate of the 30th NMOS transistor is connected to point F, the series connection point of the 31st PMOS transistor and the 30th NMOS transistor is connected to point F, and the gate of the 32nd PMOS transistor is connected to the 30th NMOS transistor. The series connection point of the tube and the thirty-second NMOS tube, and the gate of the twenty-seventh NMOS tube is connected to point I;

第三十五NMOS管连接于起振电路的第二端和提压电路的第二端之间，其栅极连接于点I； The thirty-fifth NMOS transistor is connected between the second end of the oscillating circuit and the second end of the voltage boosting circuit, and its gate is connected to point I;

第二十九NMOS管连接于起振电路的第二端和提压电路的第二端之间，其栅极与第十八NMOS管的栅极共同连接于点X，第十八NMOS管与第二十三NMOS管并联连接； The twenty-ninth NMOS transistor is connected between the second end of the oscillating circuit and the second end of the voltage boosting circuit, and its grid is connected to point X with the grid of the eighteenth NMOS transistor, and the eighteenth NMOS transistor is connected to the grid of the eighteenth NMOS transistor. The twenty-third NMOS tubes are connected in parallel;

第二十八PMOS管、第二十九PMOS管和第二十六NMOS管串联连接于第一端和第二端之间，其中，第二十八PMOS管的栅极连接于点F，第二十九PMOS管的栅极连接至第二十七NMOS管和第三十二NMOS管的串联连接点； The twenty-eighth PMOS transistor, the twenty-ninth PMOS transistor, and the twenty-sixth NMOS transistor are connected in series between the first end and the second end, wherein the gate of the twenty-eighth PMOS transistor is connected to point F, and the gate of the twenty-eighth PMOS transistor is connected to point F, and The gate of the twenty-ninth PMOS transistor is connected to the series connection point of the twenty-seventh NMOS transistor and the thirty-second NMOS transistor;

第三十PMOS管和第二十五NMOS管串联连接于第二十八PMOS管和第二端之间，其中，第三十PMOS管的栅极连接至第二十九NMOS管，第三十PMOS管的栅极与第二端之间连接有第二十四NMOS管，第二十四NMOS管的栅极与第三十PMOS管的栅极之间接有电容C1，第二十四NMOS管的栅极连接至第二十九PMOS管和第二十六NMOS管的串联连接点。 The 30th PMOS transistor and the 25th NMOS transistor are connected in series between the 28th PMOS transistor and the second end, wherein the gate of the 30th PMOS transistor is connected to the 29th NMOS transistor, and the 30th PMOS transistor is connected to the 29th NMOS transistor. A twenty-fourth NMOS transistor is connected between the gate of the PMOS transistor and the second terminal, a capacitor C1 is connected between the gate of the twenty-fourth NMOS transistor and the gate of the thirty PMOS transistor, and the twenty-fourth NMOS transistor The gate of is connected to the series connection point of the twenty-ninth PMOS transistor and the twenty-sixth NMOS transistor.

于本发明的一个或多个实施例当中，所述输出电路包括有以下元件： In one or more embodiments of the present invention, the output circuit includes the following components:

第十二PMOS管、第十三PMOS管、第十四PMOS管、第十二NMOS管和第十三NMOS管串联连接于第一端和第二端之间，其中，第十二PMOS管的栅极与第十三NMOS管的栅极连接于点M，第十三PMOS管的栅极、第十四PMOS管的栅极与第十二NMOS管的栅极连接于点N，第十三PMOS管与第十四PMOS管的串联连接点为点I，第十四PMOS管与第十二NMOS管的串联连接点为点J，点I和点J之间连接有第十四NMOS管，第十四NMOS管的栅极连接第十四PMOS管的栅极； The twelfth PMOS transistor, the thirteenth PMOS transistor, the fourteenth PMOS transistor, the twelfth NMOS transistor, and the thirteenth NMOS transistor are connected in series between the first end and the second end, wherein the twelfth PMOS transistor The gate and the gate of the thirteenth NMOS transistor are connected to point M, the gate of the thirteenth PMOS transistor, the gate of the fourteenth PMOS transistor and the gate of the twelfth NMOS transistor are connected to point N, and the gate of the thirteenth PMOS transistor is connected to point N. The series connection point of the PMOS transistor and the fourteenth PMOS transistor is point I, the series connection point of the fourteenth PMOS transistor and the twelfth NMOS transistor is point J, and the fourteenth NMOS transistor is connected between point I and point J, The gate of the fourteenth NMOS transistor is connected to the gate of the fourteenth PMOS transistor;

第十五PMOS管和第十五NMOS管串联连接于第一端和第二端之间，第三十六PMOS管和第三十六NMOS管串联连接于第一端和第二端之间，第十五PMOS管的栅极连接于点I，第十五NMOS管的栅极连接于点J，第三十六PMOS管的栅极和第三十六NMOS管的栅极共同连接于第十五PMOS管与第十五NMOS管的串联连接点，第三十六PMOS管与第三十六NMOS管的串联连接点作为电路的输出。 The fifteenth PMOS transistor and the fifteenth NMOS transistor are connected in series between the first end and the second end, the thirty-sixth PMOS transistor and the thirty-sixth NMOS transistor are connected in series between the first end and the second end, The gate of the fifteenth PMOS transistor is connected to point I, the gate of the fifteenth NMOS transistor is connected to point J, and the gate of the thirty-sixth PMOS transistor and the gate of the thirty-sixth NMOS transistor are commonly connected to the tenth point. The serial connection point of the fifth PMOS transistor and the fifteenth NMOS transistor, and the serial connection point of the thirty-sixth PMOS transistor and the thirty-sixth NMOS transistor are output of the circuit.

本发明与现有技术相比，其优越性体现在：采用区别于传统方案的交错接线方式，对起振电路和提压电路进行同相控制，解决传统电子电路中存在的短路电流问题，避免元器件进行开关切换时的大短路电流，对降低电路功耗以及提升电路稳定性有着重要的作用；同时由于提压电路的存在，使得电路振荡幅值能够得到降低，从而进一步降低整体振荡器电路的功耗。本发明摆脱传统电路的局限，采用革新的超低功耗振荡器电路结构，实现电路持久、稳定地运行，极大地延长电池的使用时间，无论从实用性还是经济性上看，均具有卓越性能，特别适合在心脏起博器这类对电路功耗要求严格的产品上使用。 Compared with the prior art, the present invention has its advantages in that it adopts the interleaved wiring method different from the traditional scheme, controls the oscillation circuit and the voltage boosting circuit in the same phase, solves the short-circuit current problem existing in the traditional electronic circuit, and avoids element failure. The large short-circuit current when the device is switching plays an important role in reducing the power consumption of the circuit and improving the stability of the circuit; at the same time, due to the existence of the voltage boosting circuit, the oscillation amplitude of the circuit can be reduced, thereby further reducing the overall oscillator circuit. power consumption. The present invention gets rid of the limitations of traditional circuits, adopts an innovative ultra-low power consumption oscillator circuit structure, realizes long-lasting and stable operation of the circuit, greatly prolongs the service time of the battery, and has excellent performance in terms of practicability and economy , especially suitable for use in products such as cardiac pacemakers that have strict requirements on circuit power consumption.

附图说明 Description of drawings

图1为本发明的超低功耗振荡器的原理框图。 FIG. 1 is a functional block diagram of an ultra-low power oscillator of the present invention.

图2为本发明的超低功耗振荡器的电路结构图。 Fig. 2 is a circuit structure diagram of the ultra-low power consumption oscillator of the present invention.

具体实施方式 detailed description

如下结合附图1至2，对本申请方案作进一步描述： The scheme of this application is further described in conjunction with accompanying drawings 1 to 2 as follows:

一种超低功耗振荡器，包括 An ultra-low power oscillator including

起振电路1；用于接收时钟信号而发起振荡，该起振电路具有第一端101和第二端102，其第一端101连接直流源VEE，第二端102与偏置电路2相连； An oscillating circuit 1; used to receive a clock signal to initiate oscillation, the oscillating circuit has a first end 101 and a second end 102, the first end 101 is connected to the DC source VEE, and the second end 102 is connected to the bias circuit 2;

偏置电路2；用于产生对该起振电路1的第二端的偏置电压，以降低振荡电路1的振荡幅值，该偏置电路2具有第一端201和第二端202，其第一端201连接直流源VEE，第二端202连接信号地端VSS；以5V电压为例，该偏置电路2与起振电路1相当于串联，偏置电路2将产生3V左右的偏置电压，则令起振电路1的振荡幅值由5V减小为2V左右，这样不仅振荡所消耗的功率大在降低，而且低压振荡有利于电路的稳定； Bias circuit 2; used to generate a bias voltage to the second end of the oscillation circuit 1 to reduce the oscillation amplitude of the oscillation circuit 1, the bias circuit 2 has a first end 201 and a second end 202, the second end of which is One terminal 201 is connected to the DC source VEE, and the second terminal 202 is connected to the signal ground terminal VSS; taking a voltage of 5V as an example, the bias circuit 2 is connected in series with the oscillation circuit 1, and the bias circuit 2 will generate a bias voltage of about 3V , then the oscillation amplitude of the oscillation circuit 1 is reduced from 5V to about 2V, so that not only the power consumed by the oscillation is greatly reduced, but also the low-voltage oscillation is conducive to the stability of the circuit;

提压电路3；用于振荡信号的输出提压，该提压电路3具有第一端301和第二端302，其第一端301连接直流源VEE，第二端302连接信号地端VSS；以及 Boosting circuit 3; used for output boosting of the oscillating signal, the boosting circuit 3 has a first end 301 and a second end 302, the first end 301 is connected to the DC source VEE, and the second end 302 is connected to the signal ground terminal VSS; as well as

输出电路4；该输出电路4具有第一端401、第二端402和输出端OSC1、OSC2，其第一端401连接直流源VEE，第二端402连接信号地端VSS； Output circuit 4; the output circuit 4 has a first terminal 401, a second terminal 402 and output terminals OSC1, OSC2, the first terminal 401 is connected to the DC source VEE, and the second terminal 402 is connected to the signal ground terminal VSS;

该起振电路1、偏置电路2和提压电路3之间具有若干个相互交错连接的节点，该些节点包括A、B、C、D、E、F、I、M、N、X，点W为时钟信号输入节点。 The oscillation circuit 1, the bias circuit 2 and the voltage boosting circuit 3 have several interleaved nodes, these nodes include A, B, C, D, E, F, I, M, N, X, Point W is the clock signal input node.

所述起振电路1包括有以下元件： The oscillation circuit 1 includes the following components:

第一PMOS管、第二PMOS管、第一NMOS管和第二NMOS管串接连接于该第一端与第二端之间，其中，第一PMOS管的栅极与第二NMOS管的栅极连接于点B，第二PMOS管的栅极与第一NMOS管的栅极连接于点C，第二PMOS管与第一NMOS管的串联连接点为点A； The first PMOS transistor, the second PMOS transistor, the first NMOS transistor and the second NMOS transistor are connected in series between the first end and the second end, wherein the gate of the first PMOS transistor and the gate of the second NMOS transistor The pole is connected to point B, the gate of the second PMOS transistor is connected to the gate of the first NMOS transistor at point C, and the series connection point of the second PMOS transistor and the first NMOS transistor is point A;

第三PMOS管、第四PMOS管、第三NMOS管、第四NMOS管和第十一NMOS管串接连接于该第一端与第二端之间，其中，第三PMOS管的栅极与第四NMOS管的栅极连接于点C，第四PMOS管的栅极与第三NMOS管的栅极连接于点D，第四PMOS管与第三NMOS管的串联连接点为点B，第十一NMOS管的栅极连接于点W； The third PMOS transistor, the fourth PMOS transistor, the third NMOS transistor, the fourth NMOS transistor and the eleventh NMOS transistor are connected in series between the first end and the second end, wherein the gate of the third PMOS transistor is connected to the second end. The gate of the fourth NMOS transistor is connected to point C, the gate of the fourth PMOS transistor and the gate of the third NMOS transistor are connected to point D, and the series connection point of the fourth PMOS transistor and the third NMOS transistor is point B. The gate of eleven NMOS transistors is connected to point W;

第五PMOS管、第六PMOS管、第五NMOS管和第六NMOS管串接连接于该第一端与第二端之间，其中，第五PMOS管的栅极与第六NMOS管的栅极连接于点D，第六PMOS管的栅极与第五NMOS管的栅极连接于点E，第六PMOS管与第五NMOS管的串联连接点为点C； The fifth PMOS transistor, the sixth PMOS transistor, the fifth NMOS transistor and the sixth NMOS transistor are connected in series between the first end and the second end, wherein the gate of the fifth PMOS transistor and the gate of the sixth NMOS transistor The pole is connected to point D, the gate of the sixth PMOS transistor and the gate of the fifth NMOS transistor are connected to point E, and the series connection point of the sixth PMOS transistor and the fifth NMOS transistor is point C;

第十六PMOS管、第七PMOS管、第八PMOS管、第七NMOS管和第八NMOS管串接连接于该第一端与第二端之间，其中，第七PMOS管的栅极与第八NMOS管的栅极连接于点E，第八PMOS管的栅极与第七NMOS管的栅极连接于点A，第八PMOS管与第七NMOS管的串联连接点为点D，第十六NMOS管的栅极连接于点X； The sixteenth PMOS transistor, the seventh PMOS transistor, the eighth PMOS transistor, the seventh NMOS transistor and the eighth NMOS transistor are connected in series between the first end and the second end, wherein the gate of the seventh PMOS transistor is connected to the The gate of the eighth NMOS transistor is connected to point E, the gate of the eighth PMOS transistor and the gate of the seventh NMOS transistor are connected to point A, the series connection point of the eighth PMOS transistor and the seventh NMOS transistor is point D, and the gate of the eighth PMOS transistor and the seventh NMOS transistor is connected to point D. The gates of sixteen NMOS transistors are connected to point X;

第十七PMOS管、第九PMOS管、第十PMOS管、第九NMOS管和第十NMOS管串接连接于该第一端与第二端之间，其中，第九PMOS管的栅极与第十NMOS管的栅极连接于点A，第十PMOS管的栅极与第九NMOS管的栅极连接于点B，第十PMOS管与第八NMOS管的串联连接点为点E，第十七NMOS管的栅极连接于点X； The seventeenth PMOS transistor, the ninth PMOS transistor, the tenth PMOS transistor, the ninth NMOS transistor and the tenth NMOS transistor are connected in series between the first end and the second end, wherein the gate of the ninth PMOS transistor is connected to the The gate of the tenth NMOS transistor is connected to point A, the gate of the tenth PMOS transistor and the gate of the ninth NMOS transistor are connected to point B, and the series connection point of the tenth PMOS transistor and the eighth NMOS transistor is point E. The gate of the seventeenth NMOS transistor is connected to point X;

第十八PMOS管连接于所述第一端和点B之间，其栅极连接于点W； The eighteenth PMOS transistor is connected between the first end and point B, and its gate is connected to point W;

第十九PMOS管和第十分NMOS管串联连接于所述第一端和VSS端之间，二者的栅极连接于点W，二者的串联连接点连接于点X； The nineteenth PMOS transistor and the tenth NMOS transistor are connected in series between the first terminal and the VSS terminal, the gates of the two are connected to point W, and the series connection point of the two is connected to point X;

第十六NMOS管连接于点E和所述第二端之间，第十七NMOS管连接于点D和所述第二端之间，第十六NMOS管的栅极和第十七NMOS管的栅极连接于点X。 The sixteenth NMOS transistor is connected between the point E and the second end, the seventeenth NMOS transistor is connected between the point D and the second end, the gate of the sixteenth NMOS transistor and the seventeenth NMOS transistor The gate of is connected to point X.

所述提压电路3包括有以下元件： The voltage boosting circuit 3 includes the following elements:

第二十六PMOS管、第二十七PMOS管和第二十三NMOS管连接于第一端和第二端之间，第二十六PMOS管的栅极连接于点B，第二十七PMOS管的栅极连接于点C，第二十七PMOS管与第二十三NMOS管的串联连接点连接于点M； The twenty-sixth PMOS transistor, the twenty-seventh PMOS transistor and the twenty-third NMOS transistor are connected between the first end and the second end, the gate of the twenty-sixth PMOS transistor is connected to point B, the twenty-seventh The gate of the PMOS transistor is connected to point C, and the series connection point of the twenty-seventh PMOS transistor and the twenty-third NMOS transistor is connected to point M;

第二十四PMOS管、第二十五PMOS管和第二十二NMOS管连接于第一端和第二端之间，第二十四PMOS管的栅极连接于点E，第二十五PMOS管的栅极连接于点A； The twenty-fourth PMOS transistor, the twenty-fifth PMOS transistor and the twenty-second NMOS transistor are connected between the first end and the second end, the gate of the twenty-fourth PMOS transistor is connected to point E, and the twenty-fifth The gate of the PMOS transistor is connected to point A;

第二十二PMOS管、第二十三PMOS管和第二十一NMOS管连接于第一端和第二端之间，第二十二PMOS管的栅极连接于点C，第二十三PMOS管的栅极连接于点E； The twenty-second PMOS transistor, the twenty-third PMOS transistor and the twenty-first NMOS transistor are connected between the first end and the second end, the gate of the twenty-second PMOS transistor is connected to point C, and the twenty-third The gate of the PMOS transistor is connected to point E;

第二十PMOS管、第二十一PMOS管和第二十NMOS管连接于第一端和第二端之间，第二十PMOS管的栅极连接于点C，第二十一PMOS管的栅极连接于点D，第二十一PMOS管与第二十NMOS管的串联连接点连接于点N； The 20th PMOS transistor, the 21st PMOS transistor and the 20th NMOS transistor are connected between the first end and the second end, the gate of the 20th PMOS transistor is connected to point C, and the gate of the 21st PMOS transistor The gate is connected to point D, and the series connection point of the twenty-first PMOS transistor and the twenty-first NMOS transistor is connected to point N;

第二十二NMOS管的栅极连接于点M，第二十NMOS管的栅极和第二十一NMOS管的栅极共同连接于第二十五PMOS管与第二十二NMOS管的串联连接点； The gate of the twenty-second NMOS transistor is connected to point M, and the gate of the twenty-first NMOS transistor is connected to the series connection of the twenty-fifth PMOS transistor and the twenty-second NMOS transistor. Junction;

所述偏置电路包2括有以下元件： The bias circuit includes the following components:

第三十一PMOS管、第三十NMOS管、第三十二NMOS管和第二十七NMOS管串联连接于第一端和第二端之间，其中，第三十一PMOS管的栅极与第三十NMOS管的栅极连接于点F，第三十一PMOS管和第三十NMOS管的串联连接点连接至点F，第三十二PMOS管的栅极连接至第三十NMOS管和第三十二NMOS管的串联连接点，第二十七NMOS管的栅极连接于点I； The thirty-first PMOS transistor, the thirty-first NMOS transistor, the thirty-second NMOS transistor, and the twenty-seventh NMOS transistor are connected in series between the first end and the second end, wherein the gate of the thirty-first PMOS transistor The gate of the 30th NMOS transistor is connected to point F, the series connection point of the 31st PMOS transistor and the 30th NMOS transistor is connected to point F, and the gate of the 32nd PMOS transistor is connected to the 30th NMOS transistor. The series connection point of the tube and the thirty-second NMOS tube, and the gate of the twenty-seventh NMOS tube is connected to point I;

第三十五NMOS管连接于起振电路的第二端和提压电路的第二端之间，其栅极连接于点I； The thirty-fifth NMOS transistor is connected between the second end of the oscillating circuit and the second end of the voltage boosting circuit, and its gate is connected to point I;

第二十九NMOS管连接于起振电路的第二端和提压电路的第二端之间，其栅极与第十八NMOS管的栅极共同连接于点X，第十八NMOS管与第二十三NMOS管并联连接； The twenty-ninth NMOS transistor is connected between the second end of the oscillating circuit and the second end of the voltage boosting circuit, and its grid is connected to point X with the grid of the eighteenth NMOS transistor, and the eighteenth NMOS transistor is connected to the grid of the eighteenth NMOS transistor. The twenty-third NMOS tubes are connected in parallel;

第二十八PMOS管、第二十九PMOS管和第二十六NMOS管串联连接于第一端和第二端之间，其中，第二十八PMOS管的栅极连接于点F，第二十九PMOS管的栅极连接至第二十七NMOS管和第三十二NMOS管的串联连接点； The twenty-eighth PMOS transistor, the twenty-ninth PMOS transistor, and the twenty-sixth NMOS transistor are connected in series between the first end and the second end, wherein the gate of the twenty-eighth PMOS transistor is connected to point F, and the gate of the twenty-eighth PMOS transistor is connected to point F, and The gate of the twenty-ninth PMOS transistor is connected to the series connection point of the twenty-seventh NMOS transistor and the thirty-second NMOS transistor;

第三十PMOS管和第二十五NMOS管串联连接于第二十八PMOS管和第二端之间，其中，第三十PMOS管的栅极连接至第二十九NMOS管，第三十PMOS管的栅极与第二端之间连接有第二十四NMOS管，第二十四NMOS管的栅极与第三十PMOS管的栅极之间接有电容C1，第二十四NMOS管的栅极连接至第二十九PMOS管和第二十六NMOS管的串联连接点。 The 30th PMOS transistor and the 25th NMOS transistor are connected in series between the 28th PMOS transistor and the second end, wherein the gate of the 30th PMOS transistor is connected to the 29th NMOS transistor, and the 30th PMOS transistor is connected to the 29th NMOS transistor. A twenty-fourth NMOS transistor is connected between the gate of the PMOS transistor and the second terminal, a capacitor C1 is connected between the gate of the twenty-fourth NMOS transistor and the gate of the thirty PMOS transistor, and the twenty-fourth NMOS transistor The gate of is connected to the series connection point of the twenty-ninth PMOS transistor and the twenty-sixth NMOS transistor.

所述输出电路4包括有以下元件： The output circuit 4 includes the following components:

第十二PMOS管、第十三PMOS管、第十四PMOS管、第十二NMOS管和第十三NMOS管串联连接于第一端和第二端之间，其中，第十二PMOS管的栅极与第十三NMOS管的栅极连接于点M，第十三PMOS管的栅极、第十四PMOS管的栅极与第十二NMOS管的栅极连接于点N，第十三PMOS管与第十四PMOS管的串联连接点为点I，第十四PMOS管与第十二NMOS管的串联连接点为点J，点I和点J之间连接有第十四NMOS管，第十四NMOS管的栅极连接第十四PMOS管的栅极； The twelfth PMOS transistor, the thirteenth PMOS transistor, the fourteenth PMOS transistor, the twelfth NMOS transistor, and the thirteenth NMOS transistor are connected in series between the first end and the second end, wherein the twelfth PMOS transistor The gate and the gate of the thirteenth NMOS transistor are connected to point M, the gate of the thirteenth PMOS transistor, the gate of the fourteenth PMOS transistor and the gate of the twelfth NMOS transistor are connected to point N, and the gate of the thirteenth PMOS transistor is connected to point N. The series connection point of the PMOS transistor and the fourteenth PMOS transistor is point I, the series connection point of the fourteenth PMOS transistor and the twelfth NMOS transistor is point J, and the fourteenth NMOS transistor is connected between point I and point J, The gate of the fourteenth NMOS transistor is connected to the gate of the fourteenth PMOS transistor;

第十五PMOS管和第十五NMOS管串联连接于第一端和第二端之间，第三十六PMOS管和第三十六NMOS管串联连接于第一端和第二端之间，第十五PMOS管的栅极连接于点I，第十五NMOS管的栅极连接于点J，第三十六PMOS管的栅极和第三十六NMOS管的栅极共同连接于第十五PMOS管与第十五NMOS管的串联连接点，第三十六PMOS管与第三十六NMOS管的串联连接点作为电路的输出。 The fifteenth PMOS transistor and the fifteenth NMOS transistor are connected in series between the first end and the second end, the thirty-sixth PMOS transistor and the thirty-sixth NMOS transistor are connected in series between the first end and the second end, The gate of the fifteenth PMOS transistor is connected to point I, the gate of the fifteenth NMOS transistor is connected to point J, and the gate of the thirty-sixth PMOS transistor and the gate of the thirty-sixth NMOS transistor are commonly connected to the tenth point. The serial connection point of the fifth PMOS transistor and the fifteenth NMOS transistor, and the serial connection point of the thirty-sixth PMOS transistor and the thirty-sixth NMOS transistor are output of the circuit.

上述优选实施方式应视为本申请方案实施方式的举例说明，凡与本申请方案雷同、近似或以此为基础作出的技术推演、替换、改进等，均应视为本专利的保护范围。 The above-mentioned preferred implementation mode should be regarded as an illustration of the implementation mode of the scheme of this application, and any technical deduction, replacement, improvement, etc. that are similar to, similar to, or based on the scheme of this application should be regarded as the scope of protection of this patent.

Claims (5)

1. a super low-power consumption agitator, it is characterised in that: include
Start-oscillation circuit；Initiating vibration during for receiving clock enabling signal, this start-oscillation circuit has the first end and the second end, and its first end connects DC source VEE, and the second end is connected with biasing circuit；
Biasing circuit；For producing the bias voltage of the second end to this start-oscillation circuit, to reduce the oscillation amplitude of oscillating circuit, this biasing circuit has the first end and the second end, and its first end connects DC source VEE, and the second end connects signal ground end VSS；
Pressure-raising circuit；For the output pressure-raising of oscillator signal, this pressure-raising circuit has the first end and the second end, and its first end connects DC source VEE, and the second end connects signal ground end VSS；And
Output circuit；This output circuit has the first end, the second end and outfan, and its first end connects DC source VEE, and the second end connects signal ground end VSS；
There are between this start-oscillation circuit, biasing circuit and pressure-raising circuit several nodes being crossed-over.
2. super low-power consumption agitator according to claim 1, it is characterised in that described start-oscillation circuit includes elements below:
First PMOS, the second PMOS, the first NMOS tube and the second NMOS tube concatenation are connected between this first end and second end, wherein, the grid of the first PMOS and the grid of the second NMOS tube are connected to a B, the grid of the second PMOS and the grid of the first NMOS tube are connected to a C, and the second PMOS is connected in series a little for an A with the first NMOS tube；
3rd PMOS, the 4th PMOS, the 3rd NMOS tube, the 4th NMOS tube and the 11st NMOS tube concatenation are connected between this first end and second end, wherein, the grid of the 3rd PMOS and the grid of the 4th NMOS tube are connected to a C, the grid of the 4th PMOS and the grid of the 3rd NMOS tube are connected to a D, 4th PMOS is some a some B with being connected in series of the 3rd NMOS tube, and the grid of the 11st NMOS tube is connected to a W；
5th PMOS, the 6th PMOS, the 5th NMOS tube and the 6th NMOS tube concatenation are connected between this first end and second end, wherein, the grid of the 5th PMOS and the grid of the 6th NMOS tube are connected to a D, the grid of the 6th PMOS and the grid of the 5th NMOS tube are connected to an E, and the 6th PMOS is connected in series a little for a C with the 5th NMOS tube；
16th PMOS, the 7th PMOS, the 8th PMOS, the 7th NMOS tube and the 8th NMOS tube concatenation are connected between this first end and second end, wherein, the grid of the 7th PMOS and the grid of the 8th NMOS tube are connected to an E, the grid of the 8th PMOS and the grid of the 7th NMOS tube are connected to an A, 8th PMOS is some a some D with being connected in series of the 7th NMOS tube, and the grid of the 16th NMOS tube is connected to an X；
17th PMOS, the 9th PMOS, the tenth PMOS, the 9th NMOS tube and the tenth NMOS tube concatenation are connected between this first end and second end, wherein, the grid of the 9th PMOS and the grid of the tenth NMOS tube are connected to an A, the grid of the tenth PMOS and the grid of the 9th NMOS tube are connected to a B, tenth PMOS is some a some E with being connected in series of the 8th NMOS tube, and the grid of the 17th NMOS tube is connected to an X；
18th PMOS is connected between described first end and some B, and its grid is connected to a W；
19th PMOS and the tenth point of NMOS tube are connected in series between described first end and VSS end, and the grid of the two is connected to a W, and being connected in series of the two is a little connected to an X；
16th NMOS tube is connected between an E and described second end, and the 17th NMOS tube is connected between a D and described second end, and the grid of the 16th NMOS tube and the grid of the 17th NMOS tube are connected to an X.
3. super low-power consumption agitator according to claim 1, it is characterised in that described pressure-raising circuit includes elements below:
26th PMOS, the 27th PMOS and the 23rd NMOS tube are connected between the first end and the second end, the grid of the 26th PMOS is connected to a B, the grid of the 27th PMOS is connected to a C, and the 27th PMOS and being connected in series of the 23rd NMOS tube are a little connected to a M；
24th PMOS, the 25th PMOS and the 22nd NMOS tube are connected between the first end and the second end, and the grid of the 24th PMOS is connected to an E, and the grid of the 25th PMOS is connected to an A；
22nd PMOS, the 23rd PMOS and the 21st NMOS tube are connected between the first end and the second end, and the grid of the 22nd PMOS is connected to a C, and the grid of the 23rd PMOS is connected to an E；
20th PMOS, the 21st PMOS and the 20th NMOS tube are connected between the first end and the second end, the grid of the 20th PMOS is connected to a C, the grid of the 21st PMOS is connected to a D, and the 21st PMOS and being connected in series of the 20th NMOS tube are a little connected to a N；
The grid of the 22nd NMOS tube is connected to a M, and the grid of the 20th NMOS tube and the grid of the 21st NMOS tube are commonly connected to being connected in series a little of the 25th PMOS and the 22nd NMOS tube.
4. super low-power consumption agitator according to claim 1, it is characterised in that described biasing circuit includes elements below:
31st PMOS, the 30th NMOS tube, the 32nd NMOS tube and the 27th NMOS tube are connected in series between the first end and the second end, wherein, the grid of the 31st PMOS and the grid of the 30th NMOS tube are connected to a F, 31st PMOS and being connected in series of the 30th NMOS tube are a little connected to a F, what the grid of the 32nd PMOS was connected to the 30th NMOS tube and the 32nd NMOS tube is connected in series a little, and the grid of the 27th NMOS tube is connected to an I；
35th NMOS tube is connected between the second end of start-oscillation circuit and the second end of pressure-raising circuit, and its grid is connected to an I；
29th NMOS tube is connected between the second end of start-oscillation circuit and the second end of pressure-raising circuit, and the grid of its grid and the 18th NMOS tube is commonly connected to an X, and the 18th NMOS tube and the 23rd NMOS tube are connected in parallel；
28th PMOS, the 29th PMOS and the 26th NMOS tube are connected in series between the first end and the second end, wherein, the grid of the 28th PMOS is connected to a F, and the grid of the 29th PMOS is connected to being connected in series a little of the 27th NMOS tube and the 32nd NMOS tube；
30th PMOS and the 25th NMOS tube are connected in series between the 28th PMOS and the second end, wherein, the grid of the 30th PMOS is connected to the 29th NMOS tube, it is connected to the 24th NMOS tube between grid and second end of the 30th PMOS, being connected to electric capacity C1 between grid and the grid of the 30th PMOS of the 24th NMOS tube, the grid of the 24th NMOS tube is connected to being connected in series a little of the 29th PMOS and the 26th NMOS tube.
5. super low-power consumption agitator according to claim 1, it is characterised in that described output circuit includes elements below:
12nd PMOS, 13rd PMOS, 14th PMOS, 12nd NMOS tube and the 13rd NMOS tube are connected in series between the first end and the second end, wherein, the grid of the 12nd PMOS and the grid of the 13rd NMOS tube are connected to a M, the grid of the 13rd PMOS, the grid of the 14th PMOS and the grid of the 12nd NMOS tube are connected to a N, 13rd PMOS is connected in series a little for an I with the 14th PMOS, 14th PMOS is connected in series a little for a J with the 12nd NMOS tube, it is connected to the 14th NMOS tube between some I and some J, the grid of the 14th NMOS tube connects the grid of the 14th PMOS；
15th PMOS and the 15th NMOS tube are connected in series between the first end and the second end, 36th PMOS and the 36th NMOS tube are connected in series between the first end and the second end, the grid of the 15th PMOS is connected to an I, the grid of the 15th NMOS tube is connected to a J, what the grid of the 36th PMOS and the grid of the 36th NMOS tube were commonly connected to the 15th PMOS and the 15th NMOS tube is connected in series a little, the 36th PMOS and the 36th NMOS tube be connected in series a little output as circuit.
CN201610042262.3A 2016-01-21 2016-01-21 Ultra-low power consumption oscillator Active CN105720947B (en)

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CN110113032A (en) * 2019-05-17 2019-08-09 芯翼信息科技(南京)有限公司 Crystal oscillation control circuit and its control method
CN119995563A (en) * 2025-04-17 2025-05-13 博越微电子(江苏)有限公司 A ring oscillator with adjustable phase noise and maximum oscillation frequency and control method

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CN101212174A (en) * 2006-12-31 2008-07-02 中国科学院半导体研究所 A Charge Pump Circuit Applied to Passive Radio Frequency Identification System
CN104104331A (en) * 2013-04-15 2014-10-15 深圳先进技术研究院 Transconductance enhancement circuit unit and crystal oscillator circuit
CN204993275U (en) * 2015-10-15 2016-01-20 深圳市博巨兴实业发展有限公司 Low -power consumption low -speed clock circuit and wearable equipment

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US20050174818A1 (en) * 2004-02-11 2005-08-11 Yung-Lin Lin Liquid crystal display system with lamp feedback
CN101212174A (en) * 2006-12-31 2008-07-02 中国科学院半导体研究所 A Charge Pump Circuit Applied to Passive Radio Frequency Identification System
CN104104331A (en) * 2013-04-15 2014-10-15 深圳先进技术研究院 Transconductance enhancement circuit unit and crystal oscillator circuit
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CN110113032A (en) * 2019-05-17 2019-08-09 芯翼信息科技(南京)有限公司 Crystal oscillation control circuit and its control method
CN110113032B (en) * 2019-05-17 2023-06-02 芯翼信息科技(南京)有限公司 Crystal oscillation control circuit and control method thereof
CN119995563A (en) * 2025-04-17 2025-05-13 博越微电子(江苏)有限公司 A ring oscillator with adjustable phase noise and maximum oscillation frequency and control method

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