CN105720563A - Multi-principle relay protection chip based on FPGA and method - Google Patents
Multi-principle relay protection chip based on FPGA and method Download PDFInfo
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Abstract
The invention discloses a multi-principle relay protection chip based on an FPGA and a method. The chip comprises a data collection module, an FPGA module, an MCU module and a communication peripheral interface; the data collection module, the FPGA module, the MCU module and the communication peripheral interface are successively connected. The method comprises steps of converting the inputted voltage and current analog quantity to an voltage signal, inputting the voltage signal into the multi-path selector and an AD unit, transmitting digital signals converted by the AD unit to an FFT unit for operation, transmitting the signal obtained through the operation of the FFT unit to a measurement unit and a hardware protection algorithm unit, transmitting the operation results of the FFT unit, the measurement unit and the hardware protection algorithm unit to a data buffering area, transmitting a relay operation signal of the data buffering area to output control and a dispatching control unit in the MCU module, wherein the MCU modules performs the interaction between the related control data and the dispatching control unit.
Description
Technical field
The present invention relates to a kind of relay protection chip, in particular to a kind of many principles relay protection chip based on FPGA and method thereof.
Background technology
Protective relaying device refers to electrical equipment in reflection power system and breaks down or irregular operating state, and action is in circuit breaker trip or a kind of automaton sending signal.Protective relaying device is widely used in existing power system, and plays an important role in New Generation of Intelligent transformer station.In traditional relay protection system design; the frameworks adopting DSP+MCU module realize more; there is certain motility and operability; but the development along with intelligent grid; New Generation of Intelligent transformer station requires to realize the miniaturization of transformer station, integrated, modularity, wisdom; to protective relaying device protection act speed and integrated on propose higher requirement, the framework of DSP+MCU module all haves much room for improvement in integrated, modularity and reliability.
Summary of the invention
For the deficiencies in the prior art; the present invention provides a kind of many principles relay protection chip based on FPGA and method thereof; based on field programmable gate array (Field-ProgrammableGateArray; and microprocessor (MicroControlUnit FPGA); MCU module) hardware structure basis on; system adopts data acquisition, Digital Signal Processing, hardware protection algorithm, FPGA and MCU module process scheduling and the module such as FPGA and peripheral communication to be analyzed and design, and has carried out hardware compilation and experimental verification on QuartusII.The present invention improves the protection act speed of relay protection system, have compressed the volume of device, and architecturally has reconfigurability.
It is an object of the invention to adopt following technical proposals to realize:
A kind of many principles relay protection chip based on FPGA, it thes improvement is that, described chip includes data acquisition module, FPGA module, MCU module and communications peripheral interface；
Described data acquisition module, FPGA module, MCU module and communications peripheral interface are sequentially connected with；
Described data acquisition module includes analog input unit, dispatch circuit, MUX and AD unit；
Described FPGA module includes that FFT unit, hardware protection unit, measuring unit, output control unit, data buffering be trivial and multi-path choice control unit；
Described MCU module includes scheduling controller and communication unit；
Described communications peripheral interface includes EEPROM interface, LCD Interface, keyboard interface and RS485 interface.
A kind of many principles relay protecting method based on FPGA that the present invention proposes based on another object, it thes improvement is that, described method includes
(1) voltage of input, current-mode analog quantity are converted to voltage signal；
(2) voltage signal is input to MUX and AD unit；
(3) the digital signal transmission after AD cell translation is carried out computing to FFT unit；
(4) signal obtained after FFT unit computing is sent in measuring unit and hardware protection algorithm unit；
(5) operation result of FFT unit, measuring unit and hardware protection algorithm unit is sent to data buffer zone；
(6) relay action signal of data buffer zone is sent to dispatch control unit in output control and MCU module；
(7) related control data and dispatch control unit are interacted by MCU module, are completed and the communicating of peripheral hardware by EEPROM, liquid crystal display screen, keyboard and RS485.
Preferably, described step (1) includes by transformer, filter circuit and voltage conversion circuit, and 16 road voltages of input, current-mode analog quantity are converted to the voltage signal lower than 2.5V by signal conditioning circuit.
Preferably, described step (2) includes this voltage signal is input to MUX and AD unit, completes every passage 32 real-time samplings of every cycle to the 16 tunnels analogy amounts inputted, and exports 14 AD cell datas of correspondence.
Preferably; described step (3) includes FFT unit and realizes the fast Fourier transform of AD unit sampling data; frequency measurement, virtual value calculate and power calculation; wherein; FFT unit calculates the first-harmonic of the every cycle of every passage and the amplitude of 15 subharmonic; first-harmonic is that hardware protection algorithm unit provides real-time data input, and harmonic wave is used for power quality analysis.
Further, the extraction of square root computing in the calculating of described virtual value adopts look-up table, it is achieved that the efficient utilization of hardware resource, each 32 of every passage is carried out FFT unit calculating by every cycle 20ms, totally 16 passage, namely every cycle completes the FFT unit of 512, and clock frequency adopts 12MHz.
Preferably; described step (4) includes being simultaneously sent to by the signal obtained after FFT unit computing in measuring unit and hardware protection algorithm unit; wherein measuring unit is for measuring the real-time amplitude of its each passage, and hardware protection algorithm unit is used for realizing pressing through stream, inverse-time overcurrent and differential protection, conventional syllogic overcurrent protection, low-frequency load reduction protection and zero sequence again and crosses the algorithm of stream and zero sequence overvoltage protection.
Preferably; described hardware protection algorithm unit is thrown by defencive function and is moved back the defencive function module that control word selects to start; result of calculation according to FFT unit and comparing with the definite value in EEPROM; corresponding protection act is carried out by the logic function of each protection module; output protection working value, warning signal and SOE event, and fixed value modification, protection are thrown and are moved back the transmission of action and SOE event by MCU module control.
Preferably; described step (5) includes the operation result of FFT unit, measuring unit and hardware protection algorithm unit is sent to data buffer zone in real time; data buffer zone, for realizing arrangement and the output of event queue SOE, carries out data interaction with dispatch control unit in MCU module simultaneously.
Preferably, described step (6) includes the relay action signal of data buffer zone and is sent to output control, is sent to relay output end mouth through output control；The data of data buffer zone are by the control of dispatch control unit in MCU module simultaneously, complete the data communication of MCU module and FPGA.
Further; the communication of described FPGA and MCU module adopts self-defining bus protocol of running simultaneously; this protocol basis realizes effective scheduling of process; the process of scheduling, it includes protection algorism throwing and moves back control, switching value, electricity, virtual value, performance number, frequency values, definite value, breaker control, higher hamonic wave value and SOE event.
Preferably, described step (7) includes MCU module and related control data and dispatch control unit is interacted, completed and the communicating of peripheral hardware by EEPROM, liquid crystal display screen, keyboard and RS485, described EEPROM reads control word for MCU module, liquid crystal is used for showing, keyboard is used for inputting, and RS485 is for communication with the outside.
Compared with the prior art, the invention have the benefit that
(1) present invention adopts FPGA+MCU module architectures, utilizes the hardware concurrent of FPGA to perform program and improves the processing speed of hardware protection logic, it is ensured that the safety and reliability of system.
(2) design of the present invention has reconfigurability, and relay protection algorithm is independent, in many occasions of relay protection, it is only necessary to by changing hardware protection algorithm unit, it is possible to make it be applied to the fields such as route protection, bus protection and tranformer protection.
(3) design of the present invention has reconfigurability, it is possible under the premise not promoting CPU frequency, high-speed response protection requirement.
(4) design of the present invention have compressed the volume of device, is conducive to site and the miniaturization of intelligent grid secondary device, provides " core " to support for intelligent grid.
Accompanying drawing explanation
Fig. 1 is a kind of many principles relay protection chip concept figure based on FPGA provided by the invention.
Fig. 2 is hardware protection algorithm logic block diagram provided by the invention.
Detailed description of the invention
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in further detail.
As it is shown in figure 1, a kind of many principles relay protection chip based on FPGA of the present invention, it includes data acquisition module, FPGA module, MCU module and communications peripheral interface；
Data acquisition module, FPGA module, MCU module and communications peripheral interface are sequentially connected with；
Data acquisition module includes analog input unit, dispatch circuit, MUX and AD unit；
FPGA module includes that FFT unit, hardware protection unit, measuring unit, output control unit, data buffering be trivial and multi-path choice control unit；
MCU module includes scheduling controller and communication unit；
Communications peripheral interface includes EEPROM interface, LCD Interface, keyboard interface and RS485 interface.
A kind of many principles relay protecting method based on FPGA of the present invention; integrate metering, protection, communication function; adopt FPGA+MCU module hardware framework; the function of the control of FPGA data acquisition, Digital Signal Processing, hardware protection algorithm and FPGA and MCU module Control on Communication, MCU module completes the function mutual with peripheral communication and MCU module and FPGA data.Concrete grammar is as follows:
1, the voltage of input, current-mode analog quantity are converted to voltage signal；
Wherein, data acquisition realizes the voltage conversion of input analog amount, real-time sampling, storage and analog digital conversion.First, by transformer, filter circuit and voltage conversion circuit, 16 road voltages of input, current-mode analog quantity are converted to the voltage signal lower than 2.5V by signal conditioning circuit.
2, voltage signal is input to MUX and AD unit；
This voltage signal is input to MUX and AD unit, completes every passage 32 real-time samplings of every cycle to the 16 tunnels analogy amounts inputted, and export 14 AD cell datas of correspondence.
3, the digital signal transmission after AD cell translation is carried out computing to FFT unit；
Digital Signal Processing realizes the function of the fast Fourier transform (FastFourierTransformation, FFT unit) of AD unit sampling data, frequency measurement, virtual value calculating and power calculation.FFT unit calculates the first-harmonic of the every cycle of every passage and the amplitude of 15 subharmonic, and first-harmonic is that hardware protection algorithm unit provides real-time data input, and harmonic wave is used for power quality analysis.FFT unit adopts the radix-4 butterfly algorithm of altera corp's IP kernel, has both met the requirement of speed and resource, is easy to again the layout to FPGA, wiring and hardware debugging.Extraction of square root computing in virtual value calculating adopts look-up table to realize, and is simultaneously achieved efficiently utilizing of hardware resource ensureing that precision is high, fireballing.Each 32 of every passage is carried out FFT unit calculating by every cycle (20ms), totally 16 passage, and namely every cycle completes the FFT unit of 512, and clock frequency adopts 12MHz.
4, the signal obtained after FFT unit computing is simultaneously sent in measuring unit and hardware protection algorithm unit; wherein measuring unit is for measuring the real-time amplitude of its each passage, and hardware protection algorithm unit is for realizing pressing through again the algorithm of stream, inverse-time overcurrent and differential protection etc.；
Hardware protection algorithm mainly includes multiple pressure overcurrent protection, inverse-time overcurrent protection, differential protection and conventional syllogic overcurrent protection, low-frequency load reduction protection (with low-voltage dead lock and slippage blocking function), zero sequence and crosses stream and zero sequence overvoltage protection etc..Hardware protection algorithm unit is thrown by defencive function and is moved back the defencive function module that control word selects to need to start; further according to the result of calculation of FFT unit with compare with the definite value (time definite value, current ration, voltage definite value etc.) in EEPROM (EEPROM); corresponding protection act is carried out by the logic function of each protection module; simultaneously output protection working value, warning signal and SOE event etc., and fixed value modification, protection throw the transmission moving back action and SOE event by MCU module control.
Wherein, pressure overcurrent protection calculates positive sequence voltage, negative sequence voltage, residual voltage and forward-order current according to three-phase phase voltage and the phase current of input again, then realizes negative sequence voltage latch-up protection by comparing with setting valve and meeting time delay condition；Inverse-time overcurrent protection adopts Taylor series expansion method 0.02 power function of general inverse time lag to be carried out curve fitting calculating；Differential protection realizes biased differential protection and the difference stream fast tripping protection of two ends formula, and biased differential protection makees difference realization of making comparisons with difference current minimum movements definite value and the minimum restraint current by calculating six phase currents of first and last end；Syllogic overcurrent protection scheduling algorithm is compared by the setting valve of the amplitude of input in real time with time and amplitude, and exports fault value and relay trip signal.
Hardware protection algorithm logic block diagram is as shown in Figure 2.Wherein I in biased differential protectionAT、IBT、ICTFor the head end electric current of test line or device, IAN、IBN、ICNFor tail current, S is ratio brake coefficient, IOPFor difference current minimum movements definite value, IresFor the minimum restraint current；I in inverse-time overcurrent protectionAset、IBset、ICsetRespectively three-phase phase current over-current adjusting value, IpFor current reference value, tpFor time constant；U in pressure overcurrent protection againA、UB、UC、UORespectively A, B, C three-phase phase voltage and residual voltage, IZsetFor forward-order current setting valve, VZsetFor positive sequence voltage setting valve, VFsetFor negative sequence voltage setting valve, VOsetFor residual voltage setting valve.
5, the operation result of FFT unit, measuring unit and hardware protection algorithm unit being sent to data buffer zone in real time, data buffer zone, for realizing arrangement and the output of event queue SOE, carries out data interaction with dispatch control unit in MCU module simultaneously；
In each task process, some processes are by PORT COM control, for instance the MCU module reading to frequency values；Some processes want spontaneous waking up, occur if any SOE event, after write FIFO, system must notify that MCU module reads immediately, and read the time that in real-time timepiece chip, SOE event occurs simultaneously, if this process oversize (having exceeded 10ms), then lose the precision of SOE logout；Such as watt metering module recorded certain value (such as 10 degree) will notify that MCU module is to read electric degree value and to be written in E2PROM.
6, the relay action signal of data buffer zone is sent to output control, is sent to relay output end mouth through output control；The data of data buffer zone are by the control of dispatch control unit in MCU module simultaneously, complete the data communication of MCU module and FPGA；
FPGA and MCU module process scheduling complete the scheduling of measured data, point information, SOE event information and Control information and the system-level scheduling of task process.The reliability of transmission speed and protection act in order to ensure system data; the communication of FPGA and MCU module adopts self-defining bus protocol of running simultaneously; realizing effective scheduling of process on this protocol basis, the process of scheduling includes protection algorism throwing and moves back control, switching value, electricity, virtual value, performance number, frequency values, definite value, breaker control, higher hamonic wave value and SOE event etc..
Realizing in process in communication task process scheduling, host state machine variable sends the command number of coming, the enable signal of the corresponding process of set according to peripheral control unit, until process end signal is driven high entrance idle condition.All task process are independent of one another, parallel, and they are only by detecting respective enable signal enabling process in real time, after once-through operation completes, automatically remove oneself enable signal so that next time host state machine restart new process.Except host state machine, other all state machines all can not start any process, all processes can not spontaneous start oneself, and simply make mistakes module etc. of SOE event buffering FIFO and internal data verification can force the peripheral control unit word that says the word within the shortest time to start corresponding task process by irq signal.
Wherein, FPGA is as follows with MCU module internal bus protocol definition:
(1) bus definition
In order to ensure the reliability of system data transmission speed and protection act, the communication of FPGA and MCU module adopts bus protocol of running simultaneously.Its signal of communication each other is 11, is described in detail below:
DATA [7:0]: 8 BDB Bi-directional Data Bus；
TCLK: parallel transmission clock signal, is controlled to produce by MCU module, high level corresponding data effect duration；
ACK: data direction id signal, is controlled to produce by MCU module, and high level represents that FPGA sends out MCU module and receives, and low level represents that MCU module is sent out FPGA and received；
FLAG: data transfer request signal, is controlled to produce by FPGA, and low level represents that MCU module must send corresponding querying command to read SOE event or electric degree value.
(2) command number
More owing to transmitting data type and content, it is separately shown according to command number.Transmitting the startup of process each time and terminate all by MCU module control, MCU module saves (namely command number) according to the first character being sent to FPGA and notifies the FPGA data content next transmitted, and determines the total amount of byte needing transmission simultaneously.
7, related control data and dispatch control unit are interacted by MCU module, being completed and the communicating of peripheral hardware by EEPROM, liquid crystal display screen, keyboard and RS485, described EEPROM reads control word for MCU module, and liquid crystal is used for showing, keyboard is used for inputting, and RS485 is for communication with the outside.
MCU module and peripheral communication provide the RS485 interface of standard, complete the communication with host computer, it is achieved the function that remote signalling, remote measurement, remote control and SOE event send.Meanwhile, MCU module and EEPROM carry out data interaction by I2C bus, it is achieved the digital independent of definite value, time etc. and amendment；MCU module has defined control and the display of data with display screen and keyboard by self-defining COM1.
Embodiment
The present invention develops software by QuartursII and carries out system design with comprehensive, adopts the EP1C12Q240C8 of ALTERA company Cyclone series to carry out simulation hardware.This FPGA realizes MUX control, the control of AD unit, FFT unit, hardware protection algorithm, frequency calculate, the function such as communicate of power calculation and FPGA and MCU module, and resources of chip takies situation in Table 1.
The design of this system has reconfigurability; have only to changing relevant hardware protection algorithm and interface; can realize being applicable to the System on Chip/SoC of different relay protection field; this system shortens the operation hardware protection time simultaneously; have compressed relay equipment volume, the design of relay protection system chip also provides more wide space for the miniaturization of New Generation of Intelligent transformer station and intelligentized application.
Finally should be noted that: above example is only in order to illustrate that technical scheme is not intended to limit; the specific embodiment of the present invention still can be modified or equivalent replacement by those of ordinary skill in the field with reference to above-described embodiment; these are without departing from any amendment of spirit and scope of the invention or equivalent replace, within the claims of the present invention all awaited the reply in application.
Claims (12)
1. the many principles relay protection chip based on FPGA, it is characterised in that described chip includes data acquisition module, FPGA module, MCU module and communications peripheral interface；
Described data acquisition module, FPGA module, MCU module and communications peripheral interface are sequentially connected with；
Described data acquisition module includes analog input unit, dispatch circuit, MUX and AD unit；
Described FPGA module includes that FFT unit, hardware protection unit, measuring unit, output control unit, data buffering be trivial and multi-path choice control unit；
Described MCU module includes scheduling controller and communication unit；
Described communications peripheral interface includes EEPROM interface, LCD Interface, keyboard interface and RS485 interface.
2. the many principles relay protecting method based on FPGA, it is characterised in that described method includes
(1) voltage of input, current-mode analog quantity are converted to voltage signal；
(2) voltage signal is input to MUX and AD unit；
(3) the digital signal transmission after AD cell translation is carried out computing to FFT unit；
(4) signal obtained after FFT unit computing is sent in measuring unit and hardware protection algorithm unit；
(5) operation result of FFT unit, measuring unit and hardware protection algorithm unit is sent to data buffer zone；
(6) data buffering is trivial is sent to output control by relay action signal；In MCU module, dispatch control unit controls data buffer zone；
(7) related control data and dispatch control unit are interacted by MCU module, complete the communication with peripheral hardware by communications peripheral interface.
3. a kind of many principles relay protecting method based on FPGA as claimed in claim 2; it is characterized in that; described step (1) includes by transformer, filter circuit and voltage conversion circuit, and in acquisition module, 16 road voltages of input, current-mode analog quantity are converted to the voltage signal lower than 2.5V by signal conditioning circuit.
4. a kind of many principles relay protecting method based on FPGA as claimed in claim 2; it is characterized in that; described step (2) includes this voltage signal is input to MUX and AD unit; complete every passage 32 real-time samplings of every cycle to the 16 tunnels analogy amounts inputted, and export 14 AD cell datas of correspondence.
5. a kind of many principles relay protecting method based on FPGA as claimed in claim 2; it is characterized in that; described step (3) includes FFT unit and realizes the fast Fourier transform of AD unit sampling data; frequency measurement, virtual value calculate and power calculation; wherein; FFT unit calculates the first-harmonic of the every cycle of every passage and the amplitude of 15 subharmonic, and first-harmonic is that hardware protection algorithm unit provides real-time data input, and harmonic wave is used for power quality analysis.
6. a kind of many principles relay protecting method based on FPGA as claimed in claim 5; it is characterized in that; extraction of square root computing in the calculating of described virtual value adopts look-up table; achieve the efficient utilization of hardware resource; each 32 of every passage is carried out FFT unit calculating by every cycle 20ms; totally 16 passage, namely every cycle completes the FFT unit of 512, and clock frequency adopts 12MHz.
7. a kind of many principles relay protecting method based on FPGA as claimed in claim 1; it is characterized in that; described step (4) includes being simultaneously sent to by the signal obtained after FFT unit computing in measuring unit and hardware protection algorithm unit; wherein measuring unit is for measuring the real-time amplitude of its each passage, and hardware protection algorithm unit is used for realizing pressing through stream, inverse-time overcurrent and differential protection, conventional syllogic overcurrent protection, low-frequency load reduction protection and zero sequence again and crosses the algorithm of stream and zero sequence overvoltage protection.
8. a kind of many principles relay protecting method based on FPGA as claimed in claim 2; it is characterized in that; described hardware protection algorithm unit is thrown by defencive function and is moved back the defencive function module controlling to select to start; result of calculation according to FFT unit and comparing with the definite value in EEPROM; corresponding protection act is carried out by the logic function of each protection module; output protection working value, warning signal and SOE event, and fixed value modification, protection are thrown and are moved back the transmission of action and SOE event by MCU module control.
9. a kind of many principles relay protecting method based on FPGA as claimed in claim 2; it is characterized in that; described step (5) includes the operation result of FFT unit, measuring unit and hardware protection algorithm unit is sent to data buffer zone in real time; data buffer zone, for realizing arrangement and the output of event queue SOE, carries out data interaction with dispatch control unit in MCU module simultaneously.
10. a kind of many principles relay protecting method based on FPGA as claimed in claim 2, it is characterised in that described step (6) includes the relay action signal of data buffer zone and is sent to output control, is sent to relay output end mouth through output control；The data of data buffer zone are by the control of dispatch control unit in MCU module simultaneously, complete the data communication of MCU module and FPGA.
11. a kind of many principles relay protecting method based on FPGA as claimed in claim 10; it is characterized in that; the communication of described FPGA and MCU module adopts bus protocol of running simultaneously; this protocol basis realizes effective scheduling of process; the process of scheduling, it includes protection algorism throwing and moves back control, switching value, electricity, virtual value, performance number, frequency values, definite value, breaker control, higher hamonic wave value and SOE event.
12. a kind of many principles relay protecting method based on FPGA as claimed in claim 2; it is characterized in that; described step (7) includes MCU module and related control data and dispatch control unit is interacted; completed and the communicating of peripheral hardware by EEPROM, liquid crystal display screen, keyboard and RS485; described EEPROM reads control word for MCU module; liquid crystal is used for showing, keyboard is used for inputting, and RS485 is for communication with the outside.
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| CN106649160A (en) * | 2016-12-29 | 2017-05-10 | 国核自仪系统工程有限公司 | ETS voting card based on FPGA architecture |
| CN110794736A (en) * | 2019-11-12 | 2020-02-14 | 西安子国微科技有限公司 | Automatic control airplane wheel cooling control device and control method |
| CN115036895A (en) * | 2022-08-10 | 2022-09-09 | 南方电网数字电网研究院有限公司 | Power chip nano relay capable of realizing series-parallel cooperation |
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Address after: 100031 Xicheng District West Chang'an Avenue, No. 86, Beijing Co-patentee after: GLOBAL ENERGY INTERCONNECTION RESEARCH INSTITUTE Co.,Ltd. Patentee after: STATE GRID CORPORATION OF CHINA Co-patentee after: STATE GRID ZHEJIANG ELECTRIC POWER Co.,Ltd. Address before: 100031 Xicheng District West Chang'an Avenue, No. 86, Beijing Co-patentee before: GLOBAL ENERGY INTERCONNECTION Research Institute Patentee before: STATE GRID CORPORATION OF CHINA Co-patentee before: STATE GRID ZHEJIANG ELECTRIC POWER Co.,Ltd. Address after: 100031 Xicheng District West Chang'an Avenue, No. 86, Beijing Co-patentee after: GLOBAL ENERGY INTERCONNECTION Research Institute Patentee after: STATE GRID CORPORATION OF CHINA Co-patentee after: STATE GRID ZHEJIANG ELECTRIC POWER Co.,Ltd. Address before: 100031 Xicheng District West Chang'an Avenue, No. 86, Beijing Co-patentee before: STATE GRID SMART GRID Research Institute Patentee before: State Grid Corporation of China Co-patentee before: STATE GRID ZHEJIANG ELECTRIC POWER Co. |
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Effective date of registration: 20191105 Address after: Building 3, zone a, Dongsheng Science Park, Zhongguancun, No.66, xixiaokou Road, Haidian District, Beijing 102200 Co-patentee after: STATE GRID INFORMATION & TELECOMMUNICATION GROUP Co.,Ltd. Patentee after: BEIJING SMARTCHIP MICROELECTRONICS TECHNOLOGY Co.,Ltd. Co-patentee after: STATE GRID ZHEJIANG ELECTRIC POWER Co.,Ltd. Co-patentee after: STATE GRID CORPORATION OF CHINA Address before: 100031 Xicheng District West Chang'an Avenue, No. 86, Beijing Co-patentee before: GLOBAL ENERGY INTERCONNECTION RESEARCH INSTITUTE Co.,Ltd. Patentee before: STATE GRID CORPORATION OF CHINA Co-patentee before: STATE GRID ZHEJIANG ELECTRIC POWER Co.,Ltd. |