CN105717749B - Non-contact type silicon wafer deflection compensation device and method based on electrostatic effect - Google Patents
Non-contact type silicon wafer deflection compensation device and method based on electrostatic effect Download PDFInfo
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- CN105717749B CN105717749B CN201410723788.9A CN201410723788A CN105717749B CN 105717749 B CN105717749 B CN 105717749B CN 201410723788 A CN201410723788 A CN 201410723788A CN 105717749 B CN105717749 B CN 105717749B
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Abstract
The present invention discloses a kind of non-contact type silicon wafer deflection compensation device, including：Positive air flotation cell；The positive air flotation cell includes housing and groove；Electrostatic adsorption unit；The groove inside bottom is provided with stationary electrode array；The positive air flotation cell includes the air inlet of some settings on the housing, for importing compressed air.
Description
Technical field
The present invention relates to a kind of integrated circuit equipment manufacturing field, more particularly to it is a kind of based on the contactless of electrostatic effect
Silicon chip deflection compensation device and method.
Background technology
193nm immersion lithographies are that it is under object lens at present towards 45nm with the main flow photoetching technique of lower node
High index of refraction n liquid is introduced between photoresist on surface and silicon chip（Such as deionized water）, by increasing objective lens numerical hole
Footpath（N.A.>1.3）, to greatly improve resolution ratio and increase depth of focus.Research shows that the deflection of silicon chip mostlys come from：（1）Silicon
The flatness error of sheet material itself；（2）Silicon chip clamping deforms；（3）The thermal deformation of silicon chip.
As for the self level error of silicon chip material, it is related to Material Cost and preceding working procedure, it is clear that it is to certainly exist, this
Meaning that needs the influence of its silicon chip flatness of active suppression.For the problem, international mainstream litho machine manufacturer ASML and
Nikon etc. is in addition to by silicon chip clamping, mainly by means of focusing and leveling measurement sensor（Such as FLS）, use is right before exposure
The vertical carry out active measurement of silicon chip surface, and pass through silicon wafer stage vertical freedom degree（Z、Rx、Ry）Feedovered accordingly vertical
Adjustment.This relates to the vertical control of complexity and may reduce yield, or introduces uncontrollable dynamic disturbances, do not utilize alignment and
Focal plane precision controlling.
To improve the yield of the effective rate of utilization of silicon chip and lithographic equipment, silicon chip diameter is by past 12inch
(300mm) extends to 18inch (450mm), i.e., smaller silicon wafer thickness diameter ratio, this means that the bending resistance stiffness of silicon chip
Reduce, and if more large-sized silicon wafers still use 3 traditional hair style E-PIN contact pin supporting mechanisms, the gravity deformation of silicon chip will be caused
Amount will increased dramatically, it is clear that be unfavorable for the flatness control of silicon chip.Itd is proposed in United States Patent (USP) US 4504045 in the upper of Substrate table
Surface layout piezoelectric actuator array controls silicon chip vertical strain.But, the response characteristic based on piezoelectric actuator, the program
It is difficult to come the accurate position for controlling piezoelectric actuator in a short time to compensate the deformation of silicon chip.Therefore, ASML companies are in patent
In US 2013/0164688 propose can quick response electrostatic capacitive brake array type silicon chip clamping and deformation-compensated dress
The scheme put.But, the program still suffers from the risk that Multi-contact pollutes between silicon chip back side and silicon chip clamping device, and clamps
Spacing, contact area and arrangement density of the controllable contact lattice array of mechanism surface etc. are still limitation control silicon chip partial face type
Restraining factors.
For dry lithography technology, " wet " environment between silicon chip and camera lens will cause silicon chip thermal deformation tighter
Weight：（1）Silicon chip surface local deformation because caused by remaining the heatcooling effect of drop；（2）Local immersion flow field maintains dress
Silicon chip part thermal deformation caused by putting（The evaporation cooling thermal change as caused by air knife is air-cooled and local flow field liquid circulation flows
Shape）；（3）Cooling thermal deformation of silicon chip back side caused by silicon chip edge leakage etc..The above-mentioned silicon chip caused by immersion flow field is local
Thermal deformation, if not being subject to active control, submergence alignment index harsh all the more certainly will be given（Such as 22nm nodes, corresponding alignment index
For 7.4nm）Bring huge technical risk.Therefore, international mainstream litho machine manufacturer such as ASML and NIKON is towards submergence
Numerous patent protections are proposed in terms of the silicon chip clamping and Control Thermal Deformation of photoetching.ASML companies are in patent US 2012/
Itd is proposed in 0212725 electrostatic clamp and temperature control device organic combination based on thin film electrode array is integral, beneficial to electrode temperature
Spend sensor array and adding thermal resistance array and real-time local temperature control is carried out to the temperature of silicon chip specified point.But, the program is only capable of
Solve the thermal deformation of silicon chip, can not solve the self-deformation of silicon chip and clamping deformation.Further, since main flow light current ASML
It is dual stage framework to carve equipment（Such as NXT 1950I）, i.e., only silicon chip pattern is measured in the measurement end of " dry " environment, and
Local deformation amount caused by the exposure end of " wet " environment is simultaneously uncontrollable and eliminated, and this does not obviously utilize alignment and focal plane
The further control of error.
The content of the invention
In order to overcome defect present in prior art, the present invention proposes a kind of positive air supporting of coupling and contactless electrostatic
Absorption without E-PIN formulas silicon chip clamping and face type compensation device, to reach elimination contact stain, and can monitor and adjust in real time silicon
Piece partial face type, to eliminate silicon chip self-deformation and clamping deformation.
In order to realize foregoing invention purpose, the present invention discloses a kind of non-contact type silicon wafer deflection compensation device, including：It is positive
Air flotation cell；The positive air flotation cell includes housing and groove；Electrostatic adsorption unit；The groove inside bottom is provided with quiet
Electrod-array；The positive air flotation cell includes the air inlet of some settings on the housing, for importing compressed air.
Further, the air inlet is located on the side or bottom surface of the housing.
Further, the quantity of the air inlet is four, and is uniformly distributed in the surrounding of housing side.
Further, the Electrostatic adsorption unit is made up of some stationary electrode array elements.
Further, the stationary electrode array element by three or six can separate space addressing stationary electrode array group
Into the vertical posture of part for adjusting the silicon chip.
Further, the stationary electrode array tundish pitch sensors containing condenser type.
Further, the condenser type pitch sensors quantity is three, and position forms an equilateral triangle；When the stationary electrode
When array is six chip, the condenser type pitch sensors are spaced apart on the stationary electrode array；When the stationary electrode array is three
During chip, the condenser type pitch sensors are uniformly distributed on the stationary electrode array.
Further, the stationary electrode array element also includes some temperature surveys and compensating electrode.
Present invention simultaneously discloses a kind of deformation-compensated method of non-contact type silicon wafer, including：Should using an electrostatic adsorption force
Silicon chip absorption is on silicon wafer stage and by a positive air supporting to the silicon chip gravity compensation；Vertical survey is carried out to the face type of the silicon chip
Amount, the vertical deviation of the silicon chip is compensated according to the vertical measurement result；The silicon chip face type after measurement compensation is until enter pre- again
Determine error range.
Compared with prior art, technical scheme silicon chip lower surface provided by the present invention and silicon chip clamping structure upper surface
Do not contact, avoid silicon chip contact stain；Then, controlled in real time by means of silicon chip partial face type, the vertical control of complexity can be avoided
Mechanism processed, improve yield；Furthermore it is exposed to correct submergence in real time by means of the integrated vertical measurement sensor feedback of condenser type
Cheng Zhong, influence of " wet " environment to silicon chip thermal deformation；Finally, the measurement of silicon chip local temperature and coordination electrode battle array can further be integrated
Row, further to eliminate silicon chip influence of thermal deformation in immersion flow field.
Brief description of the drawings
It can be obtained further by following detailed description of the invention and institute's accompanying drawings on the advantages and spirit of the present invention
Solution.
Fig. 1 is the immersion lithographic apparatus structural representation of dual stage framework；
Fig. 2 is the substrate holding apparatus top view for coupling positive air supporting and Electrostatic Absorption involved in the present invention；
Fig. 3 is the substrate holding apparatus sectional view for coupling positive air supporting and Electrostatic Absorption involved in the present invention；
Fig. 4 is six fraction microelectrode structural representations；
Fig. 5 is the space addressing structure schematic diagram of microelectrode array；
Fig. 6 is the substrate holding apparatus top view that stable type involved in the present invention couples positive air supporting and Electrostatic Absorption；
Fig. 7 is the substrate holding apparatus sectional view that stable type involved in the present invention couples positive air supporting and Electrostatic Absorption.
Embodiment
The specific embodiment that the invention will now be described in detail with reference to the accompanying drawings.
Disclosure of the invention is a kind of to couple positive air supporting with contactless Electrostatic Absorption without E-PIN formulas silicon chip clamping and face
Type compensation device, to reach elimination contact stain, and silicon chip partial face type can be monitored and adjust in real time, to eliminate silicon chip from figure
Become and clamp deformation.The technical schemes provided much more of the invention, further can measure silicon chip local temperature and compensating electrode array
It is coupled, can also further eliminates the influence of thermal deformation of silicon chip, so as to optimizes the silicon chip deformation of immersion flow field introducing to set
Quarter and the influence of depth of focus, and can avoid reducing the difficulty of control by the continuous leveling and focusing in field in exposure process, being expected to further
Improve yield.
To illustrate the technical characteristic of the present invention and application environment, it is necessary to first to the key component of immersion lithographic apparatus
Structure and the flow that works online make a brief introduction.Fig. 1 is the immersion lithographic apparatus structural representation of dual stage framework（Omit
The subsystems such as mask platform, framework, alignment, exposure light source and transmission）, wherein measurement end is dry type environment, is mainly used in silicon chip
Online alignment and vertical measurement, and expose end and be then based primarily upon that above-mentioned dry type is vertical and horizontal line measurement result, submerged
Exposure under flow fields environment.In figure, the 1 crucial subsystem object lens to expose, it is connected soon with main substrate 2 with flexibility.Exposing
End, device 3, to ensure in immersion scanning exposure process, camera lens and silicon are maintained for immersion flow field between object lens 1 and silicon chip 4
All the time the liquid of high index of refraction is full of between piece.Silicon chip clamping device 5 is used for the local deformation for supporting, clamping and compensating silicon chip 4,
This is also the key point of the present invention.Silicon chip clamping device 5 is then fixed in work stage 6.In contrast, in dual stage litho machine
The lower section of the main substrate 2 of measurement end is then vertical focusing and leveling measurement sensor 7（Such as FLS）, for being clamped in silicon wafer stage 5
On the vertical pattern of silicon chip 4 measure.
It is illustrated below for the correlation technique feature and structure of silicon chip clamping device 5.It is noted, that in order to suitable
Effective clamping of the more large-sized silicon wafers such as 450mm is answered, chip transmission is given tacit consent to herein and uses the contactless silicon based on Electrostatic Absorption
Piece transmission mechanism, and then silicon chip gravity deformation caused by E-PIN mechanisms can be avoided.Fig. 2, Fig. 3 are involved in the present invention respectively
Couple the top view and sectional view of the substrate holding apparatus of positive air supporting and Electrostatic Absorption.As shown in Figure 2,3, silicon chip clamping device
5 by together with positive air supporting and Electrostatic Absorption function efficient coupling.In the measurement end of litho machine, when silicon chip transmission system with
When CHUCK platforms carry out silicon chip handing-over, system imports compressed air by the air inlet 501 of the surrounding of wafer clamping device 5, and formation has
The positive air supporting of gravity compensation.At the same time, independently addressable stationary electrode array is arranged in the inside bottom of clamping device 5
502.Certainly, the special immersion flow field environment needed for immersion lithographic is directed to, in order to avoid drop can be along silicon chip during edge exposure
Edge immerses silicon chip back side and produces bubble, and avoids silicon chip from producing phase with CHUCK platforms surface during high speed shuttle-scanning
To displacement, its silicon chip 4 is based on electrostatic force in edge surrounding with clamping device 5 and forms air-tightness absorption, and then avoids because edge exposes
Light forms bubble and produces defect.
According to electrostatic force capacitor model, it is assumed that electrode j relative overlapping area isA j , silicon area relative to silicon chip with it is quiet
Spacing between electroded j It is sufficiently large, then correspond to electric capacityC j Can be approximately：
, j=1,2,3,4,5,6（1）
Wherein,For dielectric constant corresponding to Electrostatic Absorption equivalent capacity.If the potential being applied on counter electrode J isV j ,
Silicon chip face potential isV f , then counter electrode j be applied to the electrostatic force on corresponding silicon chip face
, j=1,2,3,4,5,6（2）
As can be seen here, on the premise of gravity compensation is completed, addressed by the space of microelectrode array, and adjust corresponding electricity
Potential on extremely can change the local Z-direction deformation of silicon chip.But, this vertical control system based on static dynamic balance is obvious
The control of silicon chip partial face type is not utilized, can not carry out independent real-time adjustment and compensation to the inclination of part.
The technical program by above-mentioned single point electrode 502 be further subdivided into it is as shown in Figure 4 can be 6 of separate space addressing
Decline electrod-array（502a-502e）.As can be seen here, can be to corresponding silicon chip face by adjusting the driving potential on 6 electrodes respectively
The vertical posture of part（Z、Rx、Ry）It is finely adjusted.For formed the vertical control of closed loop silicon chip partial face type of real-time restructural and
Compensation system, except being introduced respectively in microelectrode 502a, 502c and 502e positioned at 0o, 120 o and 240 o orientation respectively
Outside condenser type pitch sensors 503a, 503c and 503e, following workflow is introduced：
1st, in measurement end, school machine constant is surveyed offline according to silicon chip clamping（Each microelectrode drives potential）Silicon chip absorption is existed
On silicon wafer stage；
2nd, silicon chip face type is measured using the FLS of measurement end；
3rd, the vertical measurement result based on FLS, adjusts corresponding microelectrode driving potential, and its silicon chip of Contrary compensation is vertical partially
Difference；
4th, reuse FLS to measure the silicon chip face type after compensation, if corresponding into predictive error scope, record
The spacing of capacitance sensor；
5th, in the exposure process at exposure end, based on above-mentioned bias measures, vertical closed loop feedback control is carried out.
Furthermore it is also possible to temperature real-time measurement and temperature control compensation microelectrode are further introduced at the center of microelectrode 502
504, further to eliminate the thermal deformation of silicon chip.By temperature real-time measurement and closed loop feedback control are not the emphasis institutes of the present invention
, therefore do not describe in detail herein.
Fig. 5 is that single electrode declines the space addressing scheme of electrod-array, according to 3 points or 6 fraction microelectrode structures, then
Need to increase the dimension for corresponding to addressing circuit on its basis.
Fig. 6 and Fig. 7 is the another kind of the substrate holding apparatus of the positive air supporting of coupling provided by the present invention and Electrostatic Absorption
Embodiment.The embodiment, which overcomes former week line style forward direction air supporting air inlet pattern, may be unfavorable for air supporting in silicon chip scanning fortune
The defects of stability control during dynamic.Positive air supporting hole is introduced in six fraction microelectrode bottom centers, it is pneumatically supported to improve
Uniformity.
The preferred embodiment of the simply present invention described in this specification, above example is only illustrating the present invention
Technical scheme rather than limitation of the present invention.All those skilled in the art pass through logic analysis, reasoning under this invention's idea
Or the limited available technical scheme of experiment, all should be within the scope of the present invention.
Claims (9)
- A kind of 1. non-contact type silicon wafer deflection compensation device, it is characterised in that including：Positive air flotation cell；The positive air supporting Unit includes housing and groove；Electrostatic adsorption unit；The groove inside bottom is provided with stationary electrode array；The positive air supporting Unit includes the air inlet of some settings on the housing, for importing compressed air.
- 2. non-contact type silicon wafer deflection compensation device as claimed in claim 1, it is characterised in that the air inlet is positioned at described On the side or bottom surface of housing.
- 3. non-contact type silicon wafer deflection compensation device as claimed in claim 2, it is characterised in that the quantity of the air inlet is Four, and it is uniformly distributed in the surrounding of the housing side.
- 4. non-contact type silicon wafer deflection compensation device as claimed in claim 1, it is characterised in that the Electrostatic adsorption unit by Some stationary electrode array element compositions.
- 5. non-contact type silicon wafer deflection compensation device as claimed in claim 4, it is characterised in that the stationary electrode array element By three or six can separate space addressing stationary electrode array form, the vertical posture of the part for adjusting the silicon chip.
- 6. non-contact type silicon wafer deflection compensation device as claimed in claim 5, it is characterised in that among the stationary electrode array Include condenser type pitch sensors.
- 7. non-contact type silicon wafer deflection compensation device as claimed in claim 6, it is characterised in that the condenser type spacing sensing Device quantity is three, and position forms an equilateral triangle；When the stationary electrode array is six chip, the condenser type spacing sensing Device is spaced apart on the stationary electrode array；When the stationary electrode array is three-chip type, the condenser type pitch sensors It is uniformly distributed on the stationary electrode array.
- 8. non-contact type silicon wafer deflection compensation device as claimed in claim 4, it is characterised in that the stationary electrode array element Also include some temperature surveys and compensating electrode.
- A kind of 9. deformation-compensated method of non-contact type silicon wafer, it is characterised in that including：Using an electrostatic adsorption force by the silicon chip Absorption is on silicon wafer stage and by a positive air supporting to the silicon chip gravity compensation；Vertical survey is carried out to the face type of the silicon chip Amount, the vertical deviation of the silicon chip is compensated according to the vertical measurement result；The silicon chip face type after measurement compensation is until enter again Enter predictive error scope.
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| CN201410723788.9A CN105717749B (en) | 2014-12-04 | 2014-12-04 | Non-contact type silicon wafer deflection compensation device and method based on electrostatic effect |
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| CN110980280A (en) * | 2019-11-28 | 2020-04-10 | 东莞理工学院 | Non-contact multi-point type air floatation gripping device |
| CN112859531B (en) * | 2019-11-28 | 2022-06-03 | 上海微电子装备（集团）股份有限公司 | Cross-linking force measuring device and method and photoetching machine |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1544991A (en) * | 2003-11-13 | 2004-11-10 | 上海交通大学 | Magnetic suspension precise work bench of integrated circuit photolithography equipment |
| CN102768470A (en) * | 2011-05-05 | 2012-11-07 | 上海微电子装备有限公司 | Reticle stage vertical measuring apparatus |
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| US6570752B2 (en) * | 1999-12-28 | 2003-05-27 | Nikon Corporation | Wafer chucks and the like including substrate-adhesion detection and adhesion correction |
| JP2002329567A (en) * | 2001-05-02 | 2002-11-15 | Ibiden Co Ltd | Ceramic substrate and method of manufacturing junction body |
| NL2009874A (en) * | 2011-12-23 | 2013-06-26 | Asml Netherlands Bv | Support, lithographic apparatus and device manufacturing method. |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1544991A (en) * | 2003-11-13 | 2004-11-10 | 上海交通大学 | Magnetic suspension precise work bench of integrated circuit photolithography equipment |
| CN102768470A (en) * | 2011-05-05 | 2012-11-07 | 上海微电子装备有限公司 | Reticle stage vertical measuring apparatus |
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