CN105702749A - Polycrystalline multilayer passivation antireflection film with high PID resistance and preparation method thereof - Google Patents

Polycrystalline multilayer passivation antireflection film with high PID resistance and preparation method thereof Download PDF

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CN105702749A
CN105702749A CN201610168721.2A CN201610168721A CN105702749A CN 105702749 A CN105702749 A CN 105702749A CN 201610168721 A CN201610168721 A CN 201610168721A CN 105702749 A CN105702749 A CN 105702749A
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optical optimization
refractive index
polycrystalline
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CN105702749B (en
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瞿辉
徐春
曹玉甲
张源
张一源
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Jiangsu Shunfeng Photovoltaic Technology Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02Details
    • H01L31/0216Coatings
    • H01L31/02161Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/02167Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02Details
    • H01L31/0216Coatings
    • H01L31/02161Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/02167Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/02168Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells the coatings being antireflective or having enhancing optical properties for the solar cells
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract

The invention relates to a polycrystalline multilayer passivation antireflection film with high PID resistance and a preparation method thereof. The method comprises the steps as follows: a polycrystalline silicon wafer enters a PECVD furnace body after being etched; oxygen-containing gases of oxygen or air and the like are introduced; multilayer passivation antireflection film layers are deposited; the front surface of a polycrystalline silicon wafer substrate is sequentially provided with a bottom SiNx layer, an intermediate SiNx layer, a single-layer or multi-layer optical optimization SiNx layer and a top optical optimization SiOxNy layer, of which the refractive indexes are reduced progressively, from bottom to top; the total film thickness is 70-135nm; and the total refractive index is 1.95-2.20. Only the preparation method during PECVD and the film structure of the passivation antireflection film are changed on the basis of a traditional polycrystalline silicon battery technology; and the polycrystalline multilayer passivation antireflection film can be compatible with a traditional crystalline silicon battery technology, and can be produced by directly utilizing or slightly transforming ordinary etching equipment and PECVD equipment.

Description

The polycrystalline multilamellar passivated reflection reducing of high PID resistance penetrates film and preparation method thereof
Technical field
The present invention relates to solar energy crystal silicon battery and manufacture field, the polycrystalline multilamellar passivated reflection reducing of especially a kind of high PID resistance penetrates film and preparation method thereof。
Background technology
Along with environmental problem and energy problem obtain the concern of more and more people, solar cell is as a kind of clean energy resource, and its research and development have been had been introduced into a new stage by people。PID (potentialinduceddegradation) effect refers under long-term action of high voltage, assembly exists between glass and encapsulating material leaky, causing surface passivation antireflective coating before this to lose efficacy, then PN junction lost efficacy, and finally made assembly property reduce。All there is certain PID Problem of Failure in the P type solar energy crystal silicon component of traditional handicraft, so research PID phenomenon, develops one of the target that the solar cell of PIDFree is research and development department of vast solar energy manufacturer and part research institutions。More general and stricter is double; two 85PID tests at present, and its test condition is the negative voltage of 1000V, the ambient temperature of 85 DEG C, the humidity of 85%, the testing time of 96h, the final peak power output attenuation ratio of assembly just can determine that less than 5% as PID test passes, i.e. PIDFree。
The SiNx passivated reflection reducing of tradition solar energy polycrystal battery surface is penetrated rete and is nearly all made because refractive index is relatively low PID decay comparatively serious;Existing market is in order to pursue PIDFree, and main method is to improve the refractive index of SiNx rete, but the more conventional technique of battery conversion efficiency reduces 1-2%;Also having method is exactly the ozone O using ultraviolet ionization, high frequency ozone generator to generate3Oxidized silicon chip surface, generates relatively thin SiOxLayer or use laughing gas N2OPECVD method directly deposits one layer of SiO at silicon chip surfacexThin film, makes battery have certain PID resistance。
On the other hand, the antireflective coating that in current large-scale production, polycrystalline battery surface is conventional mostly is two to three layers silicon nitride, generally its optical thickness be specific wavelength 1/4th or 1/2nd。For single-layer silicon nitride silicon antireflective coating, single wavelength is only had good anti-reflective effect by it, has of a relatively high reflectance and poor passivation effect。Reflectance can be reduced and improve the focus that the antireflective coating of passivation effect is solar cell research。
Summary of the invention
The technical problem to be solved in the present invention is: the polycrystalline multilamellar passivated reflection reducing proposing a kind of high PID resistance penetrates film and preparation method thereof, this method need not use ozone devices or additive method silicon chip top layer after etching specially to increase SiOx layer, after directly using common etching apparatus and PECVD device or transforming a little。Passivated reflection reducing prepared by the method penetrates film can reduce reflectance, improves passivation effect, improves efficiency of solar cell, and has very excellent anti-PID attenuation characteristic。
The technical solution adopted in the present invention is: the polycrystalline multilamellar passivated reflection reducing of a kind of high PID resistance penetrates film, including the bottom SiN set gradually from bottom to top at polysilicon chip substrate front surfacexLayer, intermediate layer SiNxLayer, single or multiple lift optical optimization layer SiNxLayer and top layer optical optimization layer SiOxNyLayer;Described bottom SiNxLayer, intermediate layer SiNxLayer, single or multiple lift optical optimization layer SiNxLayer and top layer optical optimization layer SiOxNyThe refractive index of layer is successively decreased;Described bottom SiNxLayer, intermediate layer SiNxLayer, single or multiple lift optical optimization layer SiNxLayer and top layer optical optimization layer SiOxNyThe total film thickness of layer is 70~135nm, and total refractive index is 1.95~2.20。
Further, bottom SiN of the present inventionxLayer, intermediate layer SiNxLayer and single or multiple lift optical optimization layer SiNxLayer all adopts PECVD to prepare;Described bottom SiNxThe refractive index of layer is 2.15~2.35, and thickness is 4~15nm;Described intermediate layer SiNxThe refractive index of layer is 2.10~2.30, and thickness is 10~25nm;Described single or multiple lift optical optimization layer SiNxThe refractive index of layer is 1.95~2.25, and thickness is 20~65nm。
Further say, top layer optical optimization layer SiO of the present inventionxNyLayer adopts PECVD by oxygen-containing gas and SiH4、NH3Deposition forms together;Its thickness is 15~60nm, and refractive index is 1.6~1.95。
Meanwhile, present invention also offers the preparation method that the polycrystalline multilamellar passivated reflection reducing of a kind of high PID resistance penetrates film, comprise the following steps:
1) polysilicon chip common process performs etching after processing;
2) after etching, polysilicon chip, by the PECVD cavity carrier feeding 300 DEG C to 550 DEG C, passes into oxygen-containing gas 3min to 20min;
3) PECVD device plating multilamellar passivated reflection reducing is used to penetrate film;Including the bottom SiN set gradually from bottom to top at polysilicon chip substrate front surfacexLayer, intermediate layer SiNxLayer, single or multiple lift optical optimization layer SiNxLayer and top layer optical optimization layer SiOxNyLayer;
4) use conventional batteries typography printing back electrode, aluminum back surface field, positive grid line and anelectrode, and sinter。
Principles of the invention is: after etching, polysilicon chip enters in the PECVD cavity between 300 DEG C to 550 DEG C, passes into the oxygen-containing gas such as oxygen or air with after certain time, and silicon chip surface grown the hot SiO of thin layer2Layer, this SiOx layer is finer and close, has better passivation effect, can effectively reduce the recombination-rate surface of cell piece;And this densification SiOx layer relatively thin (0.1nm-2nm), the tunneling effect of electronics is clearly, can by battery surface be enriched with a part of electric charge lead away from, prevent the potential induction attenuation (PID) because electric charge accumulation causes at battery surface, make battery have anti-PID attenuation characteristic。
Multilamellar passivated reflection reducing penetrates the SiN of film bottom high index of refractionxThe introducing of layer both can strengthen rete passivation effect, again can the effective free positively charged ion in barrier assembly, be effectively improved the anti-PID attenuation characteristic of battery;Reduce multilamellar SiN according to certain rules successivelyxLayer can also be greatly reduced the reflectance of cell piece side to light while having certain PID resistance, it is possible to effectively reduces the reflectance of intermediate waves wave band, improves the short circuit current of cell piece;SiO in conjunction with top layer low-refractionxNyLayer so that the refractive index of overall rete is lower, continues to increase incident ray ratio, improves short circuit current, and after cell piece lamination, color is dark, and overall uniform colorless is poor。Adopting polycrystalline multilayer film battery PID resistance prepared by the method splendid, the assembly of preparation can pass through the PID test on market under double; two 85 conditions of non-resistance EVA, and battery conversion efficiency is higher than the conventional PECVD coating process of tradition。
The invention has the beneficial effects as follows: based on conventional polysilicon battery process, preparation method when only changing PECVD and passivated reflection reducing penetrate the film quality structure of film, can be compatible with conventional crystalline silicon battery process, can produce after directly using common etching apparatus and PECVD device or transforming a little。The method to equipment and polysilicon chip without particular/special requirement, be easily achieved and owing to passing into the oxygen-containing gas such as oxygen or air before depositional coating; do not have safety problem during vent gas treatment; suitable in large-scale production; also can operate with some advanced battery process, as: the back of the body passivation cell, N-type double-side cell, MWT battery etc.。
Accompanying drawing explanation
Below in conjunction with drawings and Examples, the present invention is further described。
Fig. 1 is the structural representation of the present invention;
In figure: 1, bottom SiNx layer;2, intermediate layer SiNxLayer;3, single or multiple lift optical optimization layer SiNxLayer;4, top layer optical optimization layer SiOxNyLayer。
Detailed description of the invention
Presently in connection with accompanying drawing and preferred embodiment, the present invention is further detailed explanation。These accompanying drawings are the schematic diagram of simplification, and the basic structure of the present invention is only described in a schematic way, and therefore it only shows the composition relevant with the present invention。
The polycrystalline multilamellar passivated reflection reducing of a kind of high PID resistance as shown in Figure 1 penetrates membrane structure, including the bottom SiN set gradually from bottom to top at polysilicon chip substrate front surfacexLayer 1, intermediate layer SiNxLayer 2, single or multiple lift optical optimization layer SiNxLayer 3 and top layer optical optimization layer SiOxNyLayer 4。These retes refractive index from bottom to top is successively decreased, and its total film thickness is 70~135nm, and total refractive index is 1.95~2.20。
It is further described below by two groups of embodiments:
Embodiment 1
1) by original silicon chip pretreatment, this pretreatment includes the techniques such as the making herbs into wool in battery process, diffusion and etching;
2) it is warming up to 500 DEG C after the PECVD device of silicon chip entrance 380 DEG C after etching, first the logical oxygen-containing gas 15min such as oxygen or air in PECVD cavity;It is sequentially depositing the multilamellar SiN that refractive index reduces according to certain rules successively again on polysilicon chip surfacexLayer, wherein bottom SiNxLayer, refractive index is 2.35, and thicknesses of layers is 10nm;Intermediate layer SiNxLayer, refractive index is 2.2, and thicknesses of layers is 20nm;Monolayer SiNxLayer, refractive index is 2.10, and thicknesses of layers is 30nm;Use PECVD device at diffusingsurface plating residue SiOxNyLayer, refractive index is 1.75, and thicknesses of layers is 30nm;
4) use conventional batteries typography printing back electrode, aluminum back surface field, positive grid line and anelectrode, and sinter。
Finding through detection, the photoelectric transformation efficiency of the solar battery sheet that the present embodiment obtains increases and PID resistance has bigger lifting。Concrete data are shown in table 1 below:
The photoelectric transformation efficiency of the solaode that table 1 the present embodiment obtains and PID
As can be seen from Table 1: double-layer reflection reducing coating process efficiency gain 0.11% prepared by the method, mainly due to short-circuit current gain 50 milliamperes, filling FF increases by 0.05;Double; two 85 condition PID (potential induction attenuation) power attenuations in 96 hours simultaneously only have 1.3%, and within 192 hours, PID decays to 2.8%。
Embodiment 2
1) by original silicon chip pretreatment, this pretreatment includes the techniques such as the making herbs into wool in battery process, diffusion and etching;
2) it is warming up to 550 DEG C after the PECVD device of silicon chip entrance 380 DEG C after etching, first the logical oxygen-containing gas 5min such as oxygen or air in PECVD cavity;It is sequentially depositing the multilamellar SiN that refractive index reduces according to certain rules successively again on polysilicon chip surfacexLayer, wherein bottom SiNxLayer, refractive index is 2.4, and thicknesses of layers is 8nm;Intermediate layer SiNxLayer, refractive index is 2.20, and thicknesses of layers is 15nm;Monolayer SiNxLayer, refractive index is 2.05, and thicknesses of layers is 30nm;Use PECVD device at diffusingsurface plating residue SiOxNyLayer, refractive index is 1.75, and thicknesses of layers is 40nm;
4) use conventional batteries typography printing back electrode, aluminum back surface field, positive grid line and anelectrode, and sinter。
Finding through detection, the photoelectric transformation efficiency of the solar battery sheet that the present embodiment obtains increases and PID resistance has bigger lifting。Concrete data are shown in table 2 below:
The photoelectric transformation efficiency of the solaode that table 2 the present embodiment obtains and PID
As can be seen from Table 1: double-layer reflection reducing coating process efficiency gain 0.18% prepared by the method, mainly due to short-circuit current gain 80 milliamperes, filling FF increases by 0.05;PID (potential induction attenuation) power attenuation in 96 hours simultaneously only has 0.7%, and within 192 hours, PID decays to 2.8%, and battery PID pad value is non-normally low。
Simply the specific embodiment of the present invention described in description above, the flesh and blood of the present invention is not construed as limiting by various illustrations, person of an ordinary skill in the technical field after having read description can to before described detailed description of the invention make an amendment or deform, without departing from the spirit and scope of the invention。

Claims (4)

1. the polycrystalline multilamellar passivated reflection reducing of one kind high PID resistance penetrates film, it is characterised in that: include the bottom SiN set gradually from bottom to top at polysilicon chip substrate front surfacexLayer, intermediate layer SiNxLayer, single or multiple lift optical optimization layer SiNxLayer and top layer optical optimization layer SiOxNyLayer;Described bottom SiNxLayer, intermediate layer SiNxLayer, single or multiple lift optical optimization layer SiNxLayer and top layer optical optimization layer SiOxNyThe refractive index of layer is successively decreased;Described bottom SiNxLayer, intermediate layer SiNxLayer, single or multiple lift optical optimization layer SiNxLayer and top layer optical optimization layer SiOxNyThe total film thickness of layer is 70~135nm, and total refractive index is 1.95~2.20。
2. the polycrystalline multilamellar passivated reflection reducing of high PID resistance as claimed in claim 1 penetrates film, it is characterised in that: described bottom SiNxLayer, intermediate layer SiNxLayer and single or multiple lift optical optimization layer SiNxLayer all adopts PECVD to prepare;Described bottom SiNxThe refractive index of layer is 2.15~2.35, and thickness is 4~15nm;Described intermediate layer SiNxThe refractive index of layer is 2.10~2.30, and thickness is 10~25nm;Described single or multiple lift optical optimization layer SiNxThe refractive index of layer is 1.95~2.25, and thickness is 20~65nm。
3. the polycrystalline multilamellar passivated reflection reducing of high PID resistance as claimed in claim 1 penetrates film, it is characterised in that: described top layer optical optimization layer SiOxNyLayer adopts PECVD by oxygen-containing gas and SiH4、NH3Deposition forms together;Its thickness is 15~60nm, and refractive index is 1.6~1.95。
4. the preparation method that the polycrystalline multilamellar passivated reflection reducing of a high PID resistance as claimed in claim 1 penetrates film, it is characterised in that: comprise the following steps:
1) polysilicon chip common process performs etching after processing;
2) after etching, polysilicon chip, by the PECVD cavity carrier feeding 300 DEG C to 550 DEG C, passes into oxygen-containing gas 3min to 20min;
3) PECVD device plating multilamellar passivated reflection reducing is used to penetrate film;Including the bottom SiN set gradually from bottom to top at polysilicon chip substrate front surfacexLayer, intermediate layer SiNxLayer, single or multiple lift optical optimization layer SiNxLayer and top layer optical optimization layer SiOxNyLayer;
4) use conventional batteries typography printing back electrode, aluminum back surface field, positive grid line and anelectrode, and sinter。
CN201610168721.2A 2016-03-23 2016-03-23 The polycrystalline multilayer passivated reflection reducing of high PID resistances penetrates film and preparation method thereof Active CN105702749B (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109888060A (en) * 2019-03-15 2019-06-14 通威太阳能(合肥)有限公司 A kind of solar cell and preparation method thereof with three layers of passivation layer structure
WO2023125776A1 (en) * 2021-12-30 2023-07-06 天合光能股份有限公司 Solar cell front passivation film layer

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102903764A (en) * 2012-09-27 2013-01-30 东方电气集团(宜兴)迈吉太阳能科技有限公司 Three-layered silicon nitride antireflective film of crystalline silicon solar cell and preparation method thereof
CN103794658A (en) * 2014-01-27 2014-05-14 镇江大全太阳能有限公司 Composite membrane efficient crystalline silicon solar cell and manufacturing method of composite membrane efficient crystalline silicon solar cell
CN104916710A (en) * 2015-06-30 2015-09-16 江苏顺风光电科技有限公司 High-efficiency polycrystalline multilayer passivation anti-reflection film structure with high PID resistance

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102903764A (en) * 2012-09-27 2013-01-30 东方电气集团(宜兴)迈吉太阳能科技有限公司 Three-layered silicon nitride antireflective film of crystalline silicon solar cell and preparation method thereof
CN103794658A (en) * 2014-01-27 2014-05-14 镇江大全太阳能有限公司 Composite membrane efficient crystalline silicon solar cell and manufacturing method of composite membrane efficient crystalline silicon solar cell
CN104916710A (en) * 2015-06-30 2015-09-16 江苏顺风光电科技有限公司 High-efficiency polycrystalline multilayer passivation anti-reflection film structure with high PID resistance

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109888060A (en) * 2019-03-15 2019-06-14 通威太阳能(合肥)有限公司 A kind of solar cell and preparation method thereof with three layers of passivation layer structure
WO2023125776A1 (en) * 2021-12-30 2023-07-06 天合光能股份有限公司 Solar cell front passivation film layer

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