CN105700609B - A kind of generating circuit from reference voltage - Google Patents

A kind of generating circuit from reference voltage Download PDF

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Publication number
CN105700609B
CN105700609B CN201610256167.3A CN201610256167A CN105700609B CN 105700609 B CN105700609 B CN 105700609B CN 201610256167 A CN201610256167 A CN 201610256167A CN 105700609 B CN105700609 B CN 105700609B
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operational amplifier
differential operational
resistor
nmos transistor
charge pump
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CN105700609A (en
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石寒夫
刘涛
徐代果
刘璐
王旭
邓民明
陈光炳
王育新
付东兵
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CETC 24 Research Institute
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices

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  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
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  • Automation & Control Theory (AREA)
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Abstract

The present invention provides a kind of generating circuit from reference voltage, including：Level shifting circuit, including the first charge pump, the first differential operational amplifier, the first nmos pass transistor, first resistor, second resistance and 3rd resistor, wherein, the first differential operational amplifier, the first charge pump, the first nmos pass transistor and first resistor form the first unit gain structure；For by the first unit gain structure output reference voltage, and by first resistor, second resistance and 3rd resistor with difference form by the reference voltage output to the pre-driver circuitry；Pre-driver circuitry, including the second differential operational amplifier and the 3rd differential operational amplifier, the second charge pump and tricharged pump, the second nmos pass transistor, the first PMOS transistor and the 4th resistance, wherein, second differential operational amplifier, the second charge pump, the second nmos pass transistor form the second unit gain structure, and the 3rd differential operational amplifier, tricharged pump, the first PMOS transistor form the 3rd unit gain structure；Reference voltage for being exported according to the second unit gain structure and the 3rd unit gain structure to the level shifting circuit is driven；In this way, generating circuit from reference voltage provided in an embodiment of the present invention establishes precision and bigger output voltage swing with higher.

Description

Reference voltage generating circuit
Technical Field
The present invention relates to the field of integrated circuit design, and more particularly, to a reference voltage generating circuit.
Background
With the continuous improvement of the performance of the analog-to-digital a/D converter, the requirement on the reference voltage generating circuit in the a/D converter chip is higher and higher, but the structure of the conventional reference voltage generating circuit is generally simpler, and has the defects of low establishing precision and small output swing, so that the conventional reference voltage generating circuit limits the dynamic performance of the a/D converter, and particularly in the application of the high-precision a/D converter field, the conventional reference voltage generating circuit cannot meet the requirement on the dynamic performance.
The prior reference voltage generating circuit is shown in FIG. 1, and comprises a differential operational amplifier A0N-channel Metal Oxide Semiconductor (NMOS) transistor N0、N1And resistances R1, R2; wherein A is0And N0Forming a unity gain structure such that N0Is equal to VREF(ii) a Resistance R0Has the effect of regulating N0The magnitude of the bias current; n is a radical of0And N1，R1And R0Size ratio, N1And R1A driver driving the subsequent stage circuit is formed. Thus, in the conventional reference voltage generating circuit, AND A0Reference voltage V with positive input end connectedREFThe reference voltage is output by the circuit and drives a post-stage circuit. However, the existing reference voltage generating circuit structure has two problems: firstly, the output swing of the circuit is limited by the power supply voltage of the circuit in the deep submicron process, thereby limiting the signal-to-noise ratio of the A/D converterTaking a 0.18 μm standard Complementary Metal Oxide Semiconductor (CMOS) process as an example, the threshold voltage V of an NMOS transistorTHAbout 0.5V, N in view of body effect0V ofTHApproximately equal to 0.7V, plus an overdrive voltage V of about 0.1VDSATThen N0Gate source voltage VGSAt least more than 0.8V, and N0The maximum grid voltage is 1.8V of the power supply voltage, so the maximum single-ended output swing of the circuit can only reach 1V; second, the negative reference voltage output terminal VRNThe method is easily interfered by substrate coupling noise, and the establishing precision of the substrate coupling noise is influenced, so that the dynamic performance of the whole circuit is influenced. Therefore, the above two points limit the application of such circuit structure in the high precision field.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, it is an object of the present invention to provide a reference voltage generating circuit having higher setup accuracy and larger output swing compared to the prior reference voltage generating circuit structure.
In order to achieve the above objects and other related objects, the technical solution of the present invention is achieved as follows:
the invention provides a reference voltage generating circuit, which comprises:
the level conversion circuit comprises a first charge pump, a first differential operational amplifier, a first NMOS transistor, a first resistor, a second resistor and a third resistor, wherein the first differential operational amplifier, the first charge pump, the first NMOS transistor and the first resistor form a first unit gain structure; the first unit gain structure is used for outputting a reference voltage, and the reference voltage is output to a preceding stage driving circuit in a differential mode through a first resistor, a second resistor and a third resistor;
the pre-stage driving circuit comprises a second differential operational amplifier, a third differential operational amplifier, a second charge pump, a third charge pump, a second NMOS transistor, a first P-channel metal oxide Semiconductor (PMOS) transistor and a fourth resistor, wherein the second differential operational amplifier, the second charge pump and the second NMOS transistor form a second unit gain structure, and the third differential operational amplifier, the third charge pump and the first PMOS transistor form a third unit gain structure; and the circuit is used for driving the reference voltage output by the level conversion circuit according to the second unit gain structure and the third unit gain structure.
Preferably, in the level shift circuit, a drain of the first NMOS transistor is connected to a voltage source, a gate of the first NMOS transistor is connected to an output terminal of a first differential operational amplifier, and a source of the first NMOS transistor is connected to one end of the first resistor and a positive input terminal of the second differential operational amplifier in the preceding stage driving circuit; the other end of the first resistor is connected with the negative input end of the first differential operational amplifier and one end of the second resistor; the other end of the second resistor is connected with the third resistor and the positive input end of a third differential operational amplifier in the preceding stage driving circuit; the other end of the third resistor is connected with a grounding point; the positive input end of the first differential operational amplifier is connected with the reference voltage input end, the positive power supply end of the first differential operational amplifier is connected with the output end of the first charge pump, and the negative power supply of the first differential operational amplifier is connected with the grounding point; the input end of the first charge pump is connected with an external clock;
in the preceding stage driving circuit, a drain electrode of the second NMOS transistor is connected to a voltage source, a gate electrode of the second NMOS transistor is connected to an output end of the second differential operational amplifier, and a source electrode of the second NMOS transistor is connected to one end of a fourth resistor and a negative input end of the second differential operational amplifier; the other end of the fourth resistor is connected with the source electrode of the first PMOS transistor and the negative input end of the third differential operational amplifier; the drain electrode of the first PMOS transistor is connected with the grounding point, and the grid electrode of the first PMOS transistor is connected with the output end of the third differential operational amplifier; the positive input end of the second differential operational amplifier is connected with the source electrode of the first NMOS transistor in the level conversion circuit and one end of the first resistor; the positive input end of the third differential operational amplifier is connected with one end of the level conversion circuit, which is connected with the second resistor and the third resistor; the positive power supply of the second differential operational amplifier is connected with the output end of the second charge pump, and the negative power supply of the second differential operational amplifier is connected with the grounding point; the negative power supply of the third differential operational amplifier is connected with the output end of the third charge pump, and the positive power supply of the third differential operational amplifier is connected with a voltage source; the input terminals of the second charge pump and the third charge pump are connected with an external clock.
Preferably, the circuit further comprises:
and the rear-stage driving circuit comprises a third NMOS transistor, a second PMOS transistor and a fifth resistor and is used for outputting the reference voltage image output by the front-stage driving circuit to the rear-stage circuit according to the third NMOS transistor, the second PMOS transistor and the fifth resistor.
Preferably, in the rear-stage driving circuit, a drain of the third NMOS transistor is connected to a voltage source, and a gate of the third NMOS transistor is connected to a gate of the second NMOS transistor in the front-stage driving circuit and an output terminal of the second differential operational amplifier; one end of the fifth resistor is connected with the source electrode of the third NMOS transistor, and the other end of the fifth resistor is connected with the source electrode of the second PMOS transistor; and the drain electrode of the second PMOS transistor is connected with the grounding point, and the grid electrode of the second PMOS transistor is connected with the grid electrode of the first PMOS transistor in the preceding stage driving circuit and the output end of the third differential operational amplifier.
Compared with the prior art, the reference voltage generation circuit provided by the embodiment of the invention has the following advantages that:
(1) in the embodiment of the invention, the positive power supply voltage of the first differential operational amplifier and the second differential operational amplifier respectively reaches 2 times of VDD through the first charge pump and the second charge pump, so that the grid voltage of the first NMOS transistor used as the source electrode follower of the first differential operational amplifier and the grid voltage of the second NMOS transistor used as the source electrode follower of the second differential operational amplifier can break through the limitation of the voltage supply voltage VDD, thereby increasing the output swing amplitude; similarly, the third charge pump makes the negative power voltage of the third differential operational amplifier lower to-VDD, and the gate voltage of the first PMOS transistor as the source follower can be less than 0V, so that the output swing can be further increased.
(2) In the embodiment of the invention, the substrate coupling noise can be effectively isolated through the first PMOS transistor, so that the establishing precision is improved, the stability of the whole circuit is ensured, and the overall performance of the circuit is improved.
Drawings
Fig. 1 is a schematic diagram illustrating a structure of a reference voltage generating circuit in the prior art.
FIG. 2 is a schematic diagram of a reference voltage generating circuit according to the present invention.
FIG. 3 is a schematic diagram of a specific structure of the reference voltage generating circuit according to the present invention.
Fig. 4 is a circuit diagram of a first differential operational amplifier and a second differential operational amplifier according to the present invention.
Fig. 5 is a circuit diagram of a third differential operational amplifier according to the present invention.
Fig. 6 is a circuit diagram of the first charge pump and the second charge pump of the present invention.
Fig. 7 is a circuit diagram of a third charge pump according to the present invention.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict.
It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
The following further describes embodiments of the present invention with reference to the drawings.
An embodiment of the present invention provides a reference voltage generating circuit, as shown in fig. 2, the circuit including: a level conversion circuit 20 and a preceding stage drive circuit 21; wherein,
the level conversion circuit comprises a first charge pump, a first differential operational amplifier, a first NMOS transistor, a first resistor, a second resistor and a third resistor, wherein the first differential operational amplifier, the first charge pump, the first NMOS transistor and the first resistor form a first unit gain structure; the first unit gain structure is used for outputting a reference voltage, and the reference voltage is output to the front-stage driving circuit in a differential mode through a first resistor, a second resistor and a third resistor;
the pre-stage driving circuit comprises a second differential operational amplifier, a third differential operational amplifier, a second charge pump, a third charge pump, a second NMOS transistor, a first PMOS transistor and a fourth resistor, wherein the second differential operational amplifier, the second charge pump and the second NMOS transistor form a second unit gain structure, and the third differential operational amplifier, the third charge pump and the first PMOS transistor form a third unit gain structure; and the circuit is used for driving the reference voltage output by the level conversion circuit according to the second unit gain structure and the third unit gain structure.
Further, the circuit further comprises:
and the rear-stage driving circuit 22 comprises a third NMOS transistor, a second PMOS transistor and a fifth resistor, and outputs the reference voltage image output by the front-stage driving circuit to the rear-stage circuit according to the third NMOS transistor, the second PMOS transistor and the fifth resistor.
The division manner of the upper functional sub-circuit is only a preferred implementation manner given by the embodiment of the present invention, and the division manner of the functional sub-circuit does not limit the present invention. For convenience of description, the parts of the reference voltage circuit described above are described functionally as various sub-circuits. Of course, the functions of the various sub-circuits may be implemented in the same one or more software or hardware implementations of the invention.
The following detailed description is made in practical application with reference to the reference voltage generating circuit shown in fig. 3 for the specific structure of the level converting circuit 20, the front-stage driving circuit 21, and the rear-stage driving circuit, and the connection relationship among the devices:
in the level shift circuit 20, the drain of the first NMOS transistor N0 is connected to a voltage source VDD, the gate of the first NMOS transistor N0 is connected to the output terminal of a first differential operational amplifier a0, and the source of the first NMOS transistor N0 is connected to one end of the first resistor R0 and the positive input terminal of the second differential operational amplifier a1 in the previous stage driver circuit 21; the other end of the first resistor R0 is connected with the negative input end of the first differential operational amplifier A0 and one end of the second resistor R1; the other end of the second resistor R1 is connected to the third resistor R2 and the positive input end of a third differential operational amplifier a2 in the pre-driver circuit; the third resistorThe other end of R2 is connected with the grounding point GND; a positive input terminal and a reference voltage input terminal V of the first differential operational amplifier A0REFThe positive power supply end of the first differential operational amplifier A0 is connected with the output end of the first charge pump CP0, and the negative power supply end of the first differential operational amplifier A0 is connected with the grounding point GND; an input terminal of the first charge pump CP0 is connected to an external clock CLK;
in the pre-stage driving circuit 21, a drain of the second NMOS transistor N1 is connected to a voltage source VDD, a gate of the second NMOS transistor N1 is connected to an output terminal of the second differential operational amplifier a1, and a source of the second NMOS transistor N1 is connected to one end of a fourth resistor R3 and a negative input terminal of the second differential operational amplifier a 1; the other end of the fourth resistor R3 is connected with the source of the first PMOS transistor P0 and the negative input end of the third differential operational amplifier A2; the drain of the first PMOS transistor P0 is connected to the ground GND, and the gate of the first PMOS transistor P0 is connected to the output terminal of the third differential operational amplifier a 2; the positive input terminal of the second differential operational amplifier a1 is connected to the source of the first NMOS transistor N0 in the level shifter circuit 20 and one terminal of the first resistor R0; the positive input end of the third differential operational amplifier a2 is connected to the end of the level shift circuit 20 where the second resistor R1 and the third resistor R2 are connected; the positive power supply of the second differential operational amplifier a1 is connected with the output end of the second charge pump CP1, and the negative power supply of the second differential operational amplifier a1 is connected with the ground GND; the negative power supply of the third differential operational amplifier A2 is connected with the output end of the third charge pump CP2, and the positive power supply of the third differential operational amplifier A2 is connected with the voltage source VDD; the input terminals of the second and third charge pumps CP1 and CP2 are connected to an external clock CLK;
in the back-stage driving circuit 22, the drain of the third NMOS transistor N2 is connected to the voltage source VDD, and the gate of the third NMOS transistor N2 is connected to the gate of the second NMOS transistor N1 in the front-stage driving circuit 21 and the output terminal of the second differential operational amplifier a 1; one end of the fifth resistor R4 is connected with the source of the third NMOS transistor N2, and the other end of the fifth resistor R4 is connected with the source of the second PMOS transistor P1; the drain of the second PMOS transistor P1 is connected to the ground GND, and the gate of the second PMOS transistor P1 is connected to the gate of the first PMOS transistor P0 in the pre-driver circuit 21 and the output terminal of the third differential operational amplifier a 2.
The circuit diagrams of the first differential operational amplifier and the second differential operational amplifier provided by the embodiment of the invention are shown in fig. 4, the first differential operational amplifier and the second differential operational amplifier have the same structure and internal working principle, the structure and internal working principle of the first differential operational amplifier and the second differential operational amplifier belong to the prior art, and repeated parts are not repeated.
A circuit diagram of the third differential operational amplifier provided in the embodiment of the present invention is shown in fig. 5, and the structure and the internal working principle of the third differential operational amplifier belong to the prior art, and repeated details are not repeated.
The circuit diagram of the first charge pump and the second charge pump provided by the embodiment of the invention is shown in fig. 6, the first charge pump and the second charge pump have the same structure and internal working principle, the structure and internal working principle of the first charge pump and the second charge pump belong to the prior art, and repeated parts are not described again.
A circuit diagram of a third charge pump according to an embodiment of the present invention is shown in fig. 7, and the structure and the internal working principle of the third charge pump belong to the prior art, and repeated descriptions are omitted.
In the embodiment of the present invention, based on the above circuit composition structure and the connection relationship between the devices, the operating principle of the reference voltage generating circuit is as follows:
step 1: the level shift circuit 20 outputs a reference voltage through a first unit gain structure and outputs the reference voltage to the preceding stage driving circuit in a differential form through a first resistor R0, a second resistor R1, and a third resistor R2;
in this step, the first differential operational amplifier A0A first charge pump CP0, a first NMOS transistor N0And a first resistor R0Forming a first unity gain structure, a first differential operational amplifier A0Has a high gain such that the voltage at its negative input is equal to the voltage V at the external reference voltage inputREFThe reference voltage output by the level conversion circuit 20 is converted into a differential form by a first resistor, a second resistor and a third resistor and is output to the preceding stage driving circuit 21; the output of the first charge pump is connected to the positive supply of the first differential operational amplifier, so that the first charge pump CP is connected to the positive supply of the first differential operational amplifier0The positive power supply voltage of the first differential operational amplifier a0 is bootstrapped to 2 times VDD by the external clock CLK, so that the gate voltage of the first NMOS transistor N0 as the source follower can break through the limitation of the voltage supply voltage VDD and exceed VDD, thereby increasing the output swing.
Step 2: the pre-stage driving circuit 21 drives the reference voltage output by the level conversion circuit 20 according to a second unit gain structure and a third unit gain structure;
in this step, the second differential operational amplifier A1A second charge pump CP1A second NMOS transistor N1Forming a second unity gain structure, the second charge pump CP1Is connected to the positive supply of the second differential operational amplifier, so that the second charge pump CP is connected1The positive power supply voltage of the second differential operational amplifier A1 is bootstrapped to 2 times VDD by an external clock CLK, so that the gate voltage of the second NMOS transistor N1 as a source follower can break through the limitation of the voltage supply voltage VDD and exceed VDD, and the output swing is increased;
in this step, the third differential operational amplifier A2A third charge pump CP2A first PMOS transistor P0Forming a third unity gain structure, the third charge pump CP2And the output terminal of the third differential operational amplifier A2Is connected such that the third charge pump CP2The negative supply voltage of the third differential operational amplifier is lowered to-VDD by the external clock CLK, causing the first PMOS transistor P as a source follower0The gate voltage of the transistor can be less than 0V, so that the output swing amplitude can be further increased;
in addition, the first PMOS transistor P0Substrate coupling noise can be effectively isolated, and therefore building accuracy is improved; suppose a third differential operational amplifier A2With a small signal gain of A, a first PMOS transistor P0Has a transconductance of gmp0A first PMOS transistor P0The gate-drain capacitance of CgdA first PMOS transistor P0The source-drain capacitance is CdsA first PMOS transistor P0At a substrate terminal voltage of VgndA third differential operational amplifier A2At an output terminal voltage of VoutThen the gain of coupling noise from the substrate to the output is:
as can be seen from formula (1), provided that g ismp0Greater than CgdThe gain of the substrate coupled noise to the output terminal is much smaller than 1, while the gain of the prior reference voltage generating circuit structure coupled noise from the substrate to the output terminal is equal to 1.
And step 3: the subsequent stage driving circuit 22 mirror-outputs the reference voltage outputted from the previous stage driving circuit 21 to a subsequent stage circuit.
In this step, in the rear stage driving circuit 22, the third NMOS transistor N2And a second NMOS transistor N1Of the second PMOS transistor P1And a first PMOS transistor P0And a fifth resistance R4And a fourth resistor R3The sizes of the first stage driving circuit and the second stage driving circuit are all proportional to realize that the second stage circuit is driven according to the reference voltage output by the first stage driving circuit; a second PMOS transistor P as a source follower with respect to the resistive load1Is smaller, and therefore, the internal resistance ofThe stability of the reference voltage output by the stage driving circuit is better, so that the establishing precision is further improved.
In summary, the embodiments of the present invention have higher establishing precision and larger output swing compared to the existing reference voltage generating circuit structure, can meet the requirement of a high precision a/D converter, and particularly meet the design of a reference voltage generating circuit in a simulation or digital-analog hybrid integrated circuit under a deep submicron process.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (3)

1. A reference voltage generating circuit, comprising:
the level conversion circuit comprises a first charge pump, a first differential operational amplifier, a first NMOS transistor, a first resistor, a second resistor and a third resistor, wherein the first differential operational amplifier, the first charge pump, the first NMOS transistor and the first resistor form a first unit gain structure; the first unit gain structure is used for outputting a reference voltage, and the reference voltage is output to a preceding stage driving circuit in a differential mode through a first resistor, a second resistor and a third resistor;
the pre-stage driving circuit comprises a second differential operational amplifier, a third differential operational amplifier, a second charge pump, a third charge pump, a second NMOS transistor, a first PMOS transistor and a fourth resistor, wherein the second differential operational amplifier, the second charge pump and the second NMOS transistor form a second unit gain structure, and the third differential operational amplifier, the third charge pump and the first PMOS transistor form a third unit gain structure; the reference voltage output by the level conversion circuit is driven according to the second unit gain structure and the third unit gain structure;
in the level shift circuit, a drain of the first NMOS transistor is connected to a voltage source, a gate of the first NMOS transistor is connected to an output terminal of a first differential operational amplifier, and a source of the first NMOS transistor is connected to one end of the first resistor and a positive input terminal of the second differential operational amplifier in the preceding stage driving circuit; the other end of the first resistor is connected with the negative input end of the first differential operational amplifier and one end of the second resistor; the other end of the second resistor is connected with the third resistor and the positive input end of a third differential operational amplifier in the preceding stage driving circuit; the other end of the third resistor is connected with a grounding point; the positive input end of the first differential operational amplifier is connected with the reference voltage input end, the positive power supply end of the first differential operational amplifier is connected with the output end of the first charge pump, and the negative power supply of the first differential operational amplifier is connected with the grounding point; the input end of the first charge pump is connected with an external clock;
in the preceding stage driving circuit, a drain electrode of the second NMOS transistor is connected to a voltage source, a gate electrode of the second NMOS transistor is connected to an output end of the second differential operational amplifier, and a source electrode of the second NMOS transistor is connected to one end of a fourth resistor and a negative input end of the second differential operational amplifier; the other end of the fourth resistor is connected with the source electrode of the first PMOS transistor and the negative input end of the third differential operational amplifier; the drain electrode of the first PMOS transistor is connected with the grounding point, and the grid electrode of the first PMOS transistor is connected with the output end of the third differential operational amplifier; the positive input end of the second differential operational amplifier is connected with the source electrode of the first NMOS transistor in the level conversion circuit and one end of the first resistor; the positive input end of the third differential operational amplifier is connected with one end of the level conversion circuit, which is connected with the second resistor and the third resistor; the positive power supply of the second differential operational amplifier is connected with the output end of the second charge pump, and the negative power supply of the second differential operational amplifier is connected with the grounding point; the negative power supply of the third differential operational amplifier is connected with the output end of the third charge pump, and the positive power supply of the third differential operational amplifier is connected with a voltage source; the input terminals of the second charge pump and the third charge pump are connected with an external clock.
2. The reference voltage generating circuit according to claim 1, further comprising:
and the rear-stage driving circuit comprises a third NMOS transistor, a second PMOS transistor and a fifth resistor and is used for outputting the reference voltage image output by the front-stage driving circuit to the rear-stage circuit according to the third NMOS transistor, the second PMOS transistor and the fifth resistor.
3. The reference voltage generation circuit according to claim 2,
in the rear-stage driving circuit, the drain electrode of the third NMOS transistor is connected with a voltage source, and the grid electrode of the third NMOS transistor is connected with the grid electrode of the second NMOS transistor in the front-stage driving circuit and the output end of the second differential operational amplifier; one end of the fifth resistor is connected with the source electrode of the third NMOS transistor, and the other end of the fifth resistor is connected with the source electrode of the second PMOS transistor; and the drain electrode of the second PMOS transistor is connected with the grounding point, and the grid electrode of the second PMOS transistor is connected with the grid electrode of the first PMOS transistor in the preceding stage driving circuit and the output end of the third differential operational amplifier.
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US8222927B2 (en) * 2009-04-09 2012-07-17 Mediatek Inc. Reference buffer circuit
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