CN105700609B - A kind of generating circuit from reference voltage - Google Patents
A kind of generating circuit from reference voltage Download PDFInfo
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- CN105700609B CN105700609B CN201610256167.3A CN201610256167A CN105700609B CN 105700609 B CN105700609 B CN 105700609B CN 201610256167 A CN201610256167 A CN 201610256167A CN 105700609 B CN105700609 B CN 105700609B
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- operational amplifier
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
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Abstract
The present invention provides a kind of generating circuit from reference voltage, including：Level shifting circuit, including the first charge pump, the first differential operational amplifier, the first nmos pass transistor, first resistor, second resistance and 3rd resistor, wherein, the first differential operational amplifier, the first charge pump, the first nmos pass transistor and first resistor form the first unit gain structure；For by the first unit gain structure output reference voltage, and by first resistor, second resistance and 3rd resistor with difference form by the reference voltage output to the pre-driver circuitry；Pre-driver circuitry, including the second differential operational amplifier and the 3rd differential operational amplifier, the second charge pump and tricharged pump, the second nmos pass transistor, the first PMOS transistor and the 4th resistance, wherein, second differential operational amplifier, the second charge pump, the second nmos pass transistor form the second unit gain structure, and the 3rd differential operational amplifier, tricharged pump, the first PMOS transistor form the 3rd unit gain structure；Reference voltage for being exported according to the second unit gain structure and the 3rd unit gain structure to the level shifting circuit is driven；In this way, generating circuit from reference voltage provided in an embodiment of the present invention establishes precision and bigger output voltage swing with higher.
Description
Technical field
The present invention relates to a kind of IC design field, more particularly to a kind of generating circuit from reference voltage.
Background technology
With the continuous improvement of modulus a/d transducer performance, A/D converter chip internal reference voltage generation circuit is wanted
Seek also more and more higher, but the structure of existing generating circuit from reference voltage is generally straightforward, exist establish precision it is not high and
The defects of output voltage swing is small, therefore, existing generating circuit from reference voltage limit the dynamic property of A/D converter, particularly exist
In the application in high-precision a/d converter field, its not competent requirement to dynamic property of existing generating circuit from reference voltage.
Existing generating circuit from reference voltage is as shown in figure 1, the generating circuit from reference voltage includes differential operational amplifier
A0, N-channel metal-oxide semiconductor (MOS) (Negative channel Metal Oxide Semiconductor, NMOS) crystal
Pipe N0、N1With resistance R1, R2；Wherein, A0And N0A unit gain structure is formed so that N0Source voltage be equal to VREF；Resistance
R0Effect be regulation N0The size of bias current；N0And N1, R1And R0Size is proportional, N1And R1Form a driver driving
Late-class circuit.In this way, in existing generating circuit from reference voltage with A0The connected reference voltage V of positive input terminalREFPass through the circuit
Output reference voltage simultaneously drives late-class circuit.But there is both sides in existing generating circuit from reference voltage structure：First,
The supply voltage of circuit is restricted its output voltage swing under deep submicron process, so as to limit the signal to noise ratio of A/D converter,
With 0.18 μm of standard CMOS (Complementary Metal Oxide Semiconductor,
CMOS) exemplified by technique, nmos pass transistor threshold voltage VTHAbout 0.5V, it is contemplated that bulk effect, N0VTHIt is approximately equal to 0.7V, then
Plus 0.1V or so overdrive voltage VDSAT, then N0Gate source voltage VGSAt least it is greater than 0.8V, and N0Grid voltage is up to
Supply voltage 1.8V, so the maximum Single-end output amplitude of oscillation of the circuit can only arrive 1V；Secondly, negative reference voltage output end VRNEasily
Disturbed by Substrate Coupling Noise, influence it and establish precision, so as to influence the dynamic property of integrated circuit.Therefore above-mentioned 2 points
Limit application of such circuit structure in high-precision field.
The content of the invention
In view of the above the shortcomings that prior art, it is an object of the invention to provide a kind of generating circuit from reference voltage,
Relative to existing generating circuit from reference voltage structure precision and bigger output voltage swing are established with higher.
In order to achieve the above objects and other related objects, the technical proposal of the invention is realized in this way：
The invention provides a kind of generating circuit from reference voltage, the circuit includes：
Level shifting circuit, including the first charge pump, the first differential operational amplifier, the first nmos pass transistor, the first electricity
Resistance, second resistance and 3rd resistor, wherein, the first differential operational amplifier, the first charge pump, the first nmos pass transistor and first
Resistance forms the first unit gain structure；For by the first unit gain structure output reference voltage, and pass through first
Resistance, second resistance and 3rd resistor are with difference form by the reference voltage output to pre-driver circuitry；
Pre-driver circuitry, including the second differential operational amplifier and the 3rd differential operational amplifier, the second charge pump and
Tricharged pump, the second nmos pass transistor, the first P-channel metal-oxide-semiconductor (Positive channel Metal
Oxide Semiconductor, PMOS) transistor and the 4th resistance, wherein, the second differential operational amplifier, the second electric charge
Pump, the second nmos pass transistor form the second unit gain structure, the 3rd differential operational amplifier, tricharged pump, the first PMOS
Transistor forms the 3rd unit gain structure；For according to the second unit gain structure and the 3rd unit gain structure to institute
The reference voltage for stating level shifting circuit output is driven.
Preferably, in the level shifting circuit, the drain electrode of first nmos pass transistor is connected with voltage source, described
The grid of first nmos pass transistor is connected with the output end of the first differential operational amplifier, the source electrode of first nmos pass transistor
It is connected with the positive input terminal of the second differential operational amplifier described in one end of the first resistor and the pre-driver circuitry；
The other end of the first resistor connects with the negative input end of first differential operational amplifier and one end of the second resistance
Connect；The other end of the second resistance and the 3rd differential operational amplifier in the 3rd resistor and the pre-driver circuitry
Positive input terminal connects；The other end of the 3rd resistor is connected with earth point；The positive input of first differential operational amplifier
End is connected with reference voltage input terminal, and the positive power source terminal of first differential operational amplifier and the output end of the first charge pump connect
Connect, the negative supply of first differential operational amplifier is connected with earth point；The input of first charge pump with it is outside when
Clock connects；
In the pre-driver circuitry, the drain electrode of second nmos pass transistor is connected with voltage source, and described second
The grid of nmos pass transistor is connected with the output end of second differential operational amplifier, the source electrode of second nmos pass transistor
It is connected with one end of the 4th resistance and the negative input end of second differential operational amplifier；The other end of 4th resistance with
The negative input end of the source electrode of first PMOS transistor and the 3rd differential operational amplifier connects；First PMOS is brilliant
The drain electrode of body pipe is connected with earth point, the output of the grid of first PMOS transistor and the 3rd differential operational amplifier
End connection；The source of the positive input terminal of second differential operational amplifier and the first nmos pass transistor in the level shifting circuit
Pole and the connection of one end of first resistor；The positive input terminal of 3rd differential operational amplifier is connected in the level shifting circuit
One end that second resistance is connected with 3rd resistor；The positive supply of second differential operational amplifier and second charge pump
Output end is connected, and the negative supply of second differential operational amplifier is connected with earth point；3rd differential operational amplifier
Negative supply be connected with the output end of the tricharged pump, the positive supply of the 3rd differential operational amplifier connects with voltage source
Connect；The input of second charge pump and the tricharged pump is all connected with external clock.
Preferably, the circuit also includes：
Post-stage drive circuit, including the 3rd nmos pass transistor, the second PMOS transistor and the 5th resistance, for according to
The reference voltage mirror image that three nmos pass transistors, the second PMOS transistor and the 5th resistance export the pre-driver circuitry is defeated
Go out to late-class circuit.
Preferably, in the rear in stage drive circuit, the drain electrode of the 3rd nmos pass transistor is connected with voltage source, described
The grid of 3rd nmos pass transistor is put with the grid of the second nmos pass transistor in the pre-driver circuitry and the second calculus of differences
The output end connection of big device；One end of 5th resistance is connected with the source electrode of the 3rd nmos pass transistor, the 5th electricity
The other end of resistance is connected with the source electrode of second PMOS transistor；The drain electrode of second PMOS transistor connects with earth point
Connect, the grid and the grid and the 3rd difference of the first PMOS transistor in the pre-driver circuitry of second PMOS transistor
The output end connection of operational amplifier.
The generating circuit from reference voltage that the embodiment of the present invention is provided compared with prior art, achieves following progress：
(1) in the embodiment of the present invention by the first charge pump and the second charge pump make respectively the first differential operational amplifier and
The positive voltage of second differential operational amplifier reaches 2 times of VDD, so, is followed as the first differential operational amplifier source electrode
The grid of first nmos pass transistor of device and the second nmos pass transistor as the second differential operational amplifier source follower
Voltage can break through voltage source voltage VDD limitation, so as to increase output voltage swing；Similarly, it is the 3rd poor to be made by tricharged pump
Divide the negative supply voltage as little as-VDD of operational amplifier, the grid voltage as the first PMOS transistor of source follower
Less than 0V, therefore it can further increase output voltage swing.
(2) Substrate Coupling Noise can be effectively isolated by the first PMOS transistor in the embodiment of the present invention, so as to improve
Precision is established, it ensure that the stability of whole circuit, improves the overall performance of circuit.
Brief description of the drawings
Fig. 1 is shown as the composition structural representation of generating circuit from reference voltage of the prior art.
Fig. 2 is shown as the composition structural representation of the generating circuit from reference voltage of the present invention.
Fig. 3 is shown as the concrete composition structural representation of the generating circuit from reference voltage of the present invention.
Fig. 4 is shown as the first differential operational amplifier of the present invention and the circuit diagram of the second differential operational amplifier.
Fig. 5 is shown as the circuit diagram of the 3rd differential operational amplifier of the present invention.
Fig. 6 is shown as the first charge pump of the present invention and the circuit diagram of the second charge pump.
Fig. 7 is shown as the circuit diagram of the tricharged pump of the present invention.
Embodiment
Illustrate embodiments of the present invention below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through specific realities different in addition
The mode of applying is embodied or practiced, the various details in this specification can also be based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.It should be noted that in the case where not conflicting, following examples and implementation
Feature in example can be mutually combined.
It should be noted that the diagram provided in following examples only illustrates the basic structure of the present invention in a schematic way
Think, only show the component relevant with the present invention in schema then rather than according to component count, shape and the size during actual implement
Draw, kenel, quantity and the ratio of each component can be a kind of random change during its actual implementation, and its assembly layout kenel
It is likely more complexity.
The specific embodiment of the invention is described further below in conjunction with the accompanying drawings.
The embodiment of the present invention proposes a kind of generating circuit from reference voltage, as shown in Fig. 2 the circuit includes：Level conversion
Circuit 20, pre-driver circuitry 21；Wherein,
Level shifting circuit, including the first charge pump, the first differential operational amplifier, the first nmos pass transistor, the first electricity
Resistance, second resistance and 3rd resistor, wherein, the first differential operational amplifier, the first charge pump, the first nmos pass transistor and first
Resistance forms the first unit gain structure；For by the first unit gain structure output reference voltage, and pass through first
Resistance, second resistance and 3rd resistor are with difference form by the reference voltage output to the pre-driver circuitry；
Pre-driver circuitry, including the second differential operational amplifier and the 3rd differential operational amplifier, the second charge pump and
Tricharged pump, the second nmos pass transistor, the first PMOS transistor and the 4th resistance, wherein, the second differential operational amplifier,
Second charge pump, the second nmos pass transistor form the second unit gain structure, the 3rd differential operational amplifier, tricharged pump,
First PMOS transistor forms the 3rd unit gain structure；For according to the second unit gain structure and the 3rd unit gain
The reference voltage that structure exports to the level shifting circuit is driven.
Further, the circuit also includes：
Post-stage drive circuit 22, including the 3rd nmos pass transistor, the second PMOS transistor and the 5th resistance, according to the 3rd
The reference voltage mirror image that nmos pass transistor, the second PMOS transistor and the 5th resistance export the pre-driver circuitry exports
To late-class circuit.
The dividing mode of upper function sub-circuit is only a kind of preferred implementation that the embodiment of the present invention provides, and function is electric
The dividing mode on road is not construed as limiting the invention.For convenience of description, each several part of reference voltage circuit described above
Each subcircuits description is divided into function.Certainly, can be the function of each sub-circuit same or more when implementing of the invention
Realized in individual software or hardware.
Below in actual applications the generating circuit from reference voltage with reference to shown in Fig. 3 respectively to level shifting circuit 20, preceding
The annexation of stage drive circuit 21, the concrete composition structure of post-stage drive circuit and each device is described in detail：
In the level shifting circuit 20, the drain electrode of the first nmos pass transistor N0 is connected with voltage source VDD, described
First nmos pass transistor N0 grid is connected with the first differential operational amplifier A0 output end, the first nmos pass transistor N0
Source electrode and the first resistor R0 one end and the pre-driver circuitry 21 described in the second differential operational amplifier A1
Positive input terminal connects；The other end of the first resistor R0 and the first differential operational amplifier A0 negative input end and described
Second resistance R1 one end connection；The other end of the second resistance R1 and the 3rd resistor R2 and the pre-driver circuitry
In the 3rd differential operational amplifier A2 positive input terminal connection；The other end of the 3rd resistor R2 is connected with earth point GND；Institute
State the first differential operational amplifier A0 positive input terminal and reference voltage input terminal VREFConnection, the first calculus of differences amplification
Device A0 positive power source terminal is connected with the first charge pump CP0 output end, the negative supply of the first differential operational amplifier A0 with
Earth point GND connections；The input of the first charge pump CP0 is connected with external clock CLK；
In the pre-driver circuitry 21, the drain electrode of the second nmos pass transistor N1 is connected with voltage source VDD, described
Second nmos pass transistor N1 grid is connected with the output end of the second differential operational amplifier A1, the 2nd NMOS crystal
Pipe N1 source electrode is connected with the 4th resistance R3 one end and the negative input end of the second differential operational amplifier A1；Described 4th
The resistance R3 other end and the source electrode of the first PMOS transistor P0 and the negative input of the 3rd differential operational amplifier A2
End connection；The drain electrode of the first PMOS transistor P0 is connected with earth point GND, the grid of the first PMOS transistor P0 with
The output end connection of the 3rd differential operational amplifier A2；The positive input terminal of the second differential operational amplifier A1 with it is described
First nmos pass transistor N0 source electrode and first resistor R0 one end connect in level shifting circuit 20；3rd calculus of differences
Amplifier A2 positive input terminal connects one end that second resistance R1 is connected with 3rd resistor R2 in the level shifting circuit 20；Institute
The positive supply for stating the second differential operational amplifier A1 is connected with the output end of the second charge pump CP1, the second difference fortune
The negative supply for calculating amplifier A1 is connected with earth point GND；The negative supply and the described 3rd of the 3rd differential operational amplifier A2
Charge pump CP2 output end connection, the positive supply of the 3rd differential operational amplifier A2 are connected with voltage source VDD；Described
Two charge pump CP1 and the tricharged pump CP2 input are connected with external clock CLK；
In the rear in stage drive circuit 22, the drain electrode of the 3rd nmos pass transistor N2 is connected with voltage source VDD, described
The grid and the second difference of 3rd nmos pass transistor N2 grid and the second nmos pass transistor N1 in the pre-driver circuitry 21
The output end connection of operational amplifier A 1；One end of the 5th resistance R4 and the source electrode phase of the 3rd nmos pass transistor N2
Even, the other end of the 5th resistance R4 is connected with the source electrode of the second PMOS transistor P1；Second PMOS transistor
P1 drain electrode is connected with earth point GND, the grid of the second PMOS transistor P1 and in the pre-driver circuitry 21 first
PMOS transistor P0 grid and the 3rd differential operational amplifier A2 output end connect.
Circuit diagram such as Fig. 4 of first differential operational amplifier and the second differential operational amplifier provided in an embodiment of the present invention
Shown, the first differential operational amplifier and the second differential operational amplifier have identical structure and inner workings, described
The structure and inner workings of first differential operational amplifier and the second differential operational amplifier belong to prior art, repetition
Place repeats no more.
The circuit diagram of 3rd differential operational amplifier provided in an embodiment of the present invention is as shown in figure 5, the 3rd difference is transported
Calculate the structure of amplifier and inner workings belong to prior art, repeat part and repeat no more.
The circuit diagram of first charge pump and the second charge pump provided in an embodiment of the present invention is as shown in fig. 6, first electricity
Lotus pump and second charge pump have identical structure and inner workings, first charge pump and the second charge pump
Structure and inner workings belong to prior art, repeat part and repeat no more.
The circuit diagram of tricharged pump provided in an embodiment of the present invention as shown in fig. 7, the structure of the tricharged pump and
Inner workings belong to prior art, repeat part and repeat no more.
In the embodiment of the present invention, the annexation between structure and device, the reference voltage production are formed based on foregoing circuit
The operation principle of raw circuit is such：
Step 1：The level shifting circuit 20 passes through the first electricity by the first unit gain structure output reference voltage
R0, second resistance R1 and 3rd resistor R2 are hindered with difference form by the reference voltage output to the pre-driver circuitry；
In this step, the first differential operational amplifier A0, the first charge pump CP0, the first nmos pass transistor N0And first resistor
R0Form the first unit gain structure, the first differential operational amplifier A0High-gain make its negative input end voltage be equal to outside
Reference voltage input terminal voltage VREF, the level shifting circuit 20 is exported by first resistor, second resistance and 3rd resistor
Reference voltage is converted into difference form and is output to the pre-driver circuitry 21；The output end of first charge pump and the first difference
The positive supply of operational amplifier is connected, so, the first charge pump CP0First calculus of differences is put by external clock CLK
Big device A0 positive voltage is booted to 2 times of VDD so that the grid voltage as the first nmos pass transistor N0 of source follower
Voltage source voltage VDD limitation can be broken through and more than VDD, so as to increase output voltage swing.
Step 2：The pre-driver circuitry 21 is according to the second unit gain structure and the 3rd unit gain structure to described
The reference voltage that level shifting circuit 20 exports is driven；
In this step, the second differential operational amplifier A1, the second charge pump CP1, the second nmos pass transistor N1It is single to form second
Position gaining structure, second charge pump CP1Output end be connected with the positive supply of the second differential operational amplifier, so, second
Charge pump CP1The positive voltage of the second differential operational amplifier A1 is booted to 2 times of VDD by external clock CLK, made
Voltage source voltage VDD limitation must can be broken through as the second nmos pass transistor N1 of source follower grid voltage and exceed
VDD, so as to increase output voltage swing；
In this step, the 3rd differential operational amplifier A2, tricharged pump CP2, the first PMOS transistor P0It is single to form the 3rd
Position gaining structure, tricharged pump CP2Output end and the 3rd differential operational amplifier A2Negative supply connection, so, the 3rd
Charge pump CP2Make the negative supply voltage as little as-VDD of the 3rd differential operational amplifier by external clock CLK, make as source electrode with
With the first PMOS transistor P of device0Grid voltage i.e. be smaller than 0V, therefore, it is possible to further increase output voltage swing；
In addition, the first PMOS transistor P0Substrate Coupling Noise can be effectively isolated, precision is established so as to improve；It is false
If the 3rd differential operational amplifier A2Small-signal gain be A, the first PMOS transistor P0Mutual conductance be gmp0, the first PMOS crystal
Pipe P0Gate leakage capacitance be Cgd, the first PMOS transistor P0Source drain capacitance be Cds, the first PMOS transistor P0Substrate terminal electricity
Press as Vgnd, the 3rd differential operational amplifier A2Output end voltage be Vout, then by the increasing of Substrate Coupling Noise to output end
Benefit is：
From formula (1), as long as gmp0More than Cgd, by Substrate Coupling Noise to output end gain just be far smaller than 1, and
Gain of the existing generating circuit from reference voltage structure from Substrate Coupling Noise to output end is equal to 1.
Step 3：The reference voltage mirror image that the pre-driver circuitry 21 exports is output to by the post-stage drive circuit 22
Late-class circuit.
In this step, in the rear in stage drive circuit 22, the 3rd nmos pass transistor N2With the second nmos pass transistor N1Chi
It is very little, the second PMOS transistor P1With the first PMOS transistor P0Size, and the 5th resistance R4With the 4th resistance R3Size it is equal
It is proportional, to realize that the reference voltage exported according to the pre-driver circuitry drives late-class circuit；Relative to ohmic load
Speech, the second PMOS transistor P as source follower1Internal resistance it is smaller, therefore, reference of post-stage drive circuit output is electric
The stability of pressure is more preferable, and precision is established so as to further increase.
In summary, the embodiment of the present invention establishes precision relative to existing generating circuit from reference voltage structure with higher
Bigger output voltage swing, disclosure satisfy that the requirement of high-precision a/d converter, especially meet deep submicron process Imitating or
The design of generating circuit from reference voltage in hybrid digital-analog integrated circuit.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete without departing from disclosed spirit and institute under technological thought such as
Into all equivalent modifications or change, should by the present invention claim be covered.
Claims (3)
1. a kind of generating circuit from reference voltage, it is characterised in that the circuit includes：
Level shifting circuit, including the first charge pump, the first differential operational amplifier, the first nmos pass transistor, first resistor,
Two resistance and 3rd resistor, wherein, the first differential operational amplifier, the first charge pump, the first nmos pass transistor and first resistor
Form the first unit gain structure；For by the first unit gain structure output reference voltage, and by first resistor,
Second resistance and 3rd resistor are with difference form by the reference voltage output to pre-driver circuitry；
Pre-driver circuitry, including the second differential operational amplifier and the 3rd differential operational amplifier, the second charge pump and the 3rd
Charge pump, the second nmos pass transistor, the first PMOS transistor and the 4th resistance, wherein, the second differential operational amplifier, second
Charge pump, the second nmos pass transistor form the second unit gain structure, the 3rd differential operational amplifier, tricharged pump, first
PMOS transistor forms the 3rd unit gain structure；For according to the second unit gain structure and the 3rd unit gain structure
The reference voltage of level shifting circuit output is driven；
In the level shifting circuit, the drain electrode of first nmos pass transistor is connected with voltage source, and the first NMOS is brilliant
The grid of body pipe is connected with the output end of the first differential operational amplifier, the source electrode of first nmos pass transistor and described first
The positive input terminal connection of second differential operational amplifier described in one end of resistance and the pre-driver circuitry；First electricity
The other end of resistance is connected with the negative input end of first differential operational amplifier and one end of the second resistance；Described second
The positive input terminal of the other end of resistance and the 3rd differential operational amplifier in the 3rd resistor and the pre-driver circuitry connects
Connect；The other end of the 3rd resistor is connected with earth point；The positive input terminal of first differential operational amplifier and reference electricity
Input connection is pressed, the positive power source terminal of first differential operational amplifier is connected with the output end of the first charge pump, and described the
The negative supply of one differential operational amplifier is connected with earth point；The input of first charge pump is connected with external clock；
In the pre-driver circuitry, the drain electrode of second nmos pass transistor is connected with voltage source, and the 2nd NMOS is brilliant
The grid of body pipe is connected with the output end of second differential operational amplifier, the source electrode and the 4th of second nmos pass transistor
The negative input end of one end of resistance and second differential operational amplifier connects；The other end of 4th resistance and described the
The negative input end of the source electrode of one PMOS transistor and the 3rd differential operational amplifier connects；First PMOS transistor
Drain electrode is connected with earth point, and the output end of the grid of first PMOS transistor and the 3rd differential operational amplifier connects
Connect；The source electrode of the positive input terminal of second differential operational amplifier and the first nmos pass transistor in the level shifting circuit and
One end connection of first resistor；The positive input terminal of 3rd differential operational amplifier is connected second in the level shifting circuit
One end that resistance is connected with 3rd resistor；The positive supply of second differential operational amplifier and the output of second charge pump
End connection, the negative supply of second differential operational amplifier are connected with earth point；3rd differential operational amplifier is born
Power supply is connected with the output end of the tricharged pump, and the positive supply of the 3rd differential operational amplifier is connected with voltage source；
The input of second charge pump and the tricharged pump is all connected with external clock.
2. generating circuit from reference voltage according to claim 1, it is characterised in that the circuit also includes：
Post-stage drive circuit, including the 3rd nmos pass transistor, the second PMOS transistor and the 5th resistance, for according to the 3rd
The reference voltage mirror image that nmos pass transistor, the second PMOS transistor and the 5th resistance export the pre-driver circuitry exports
To late-class circuit.
3. generating circuit from reference voltage according to claim 2, it is characterised in that
In the rear in stage drive circuit, the drain electrode of the 3rd nmos pass transistor is connected with voltage source, and the 3rd NMOS is brilliant
The output of the grid of body pipe and the grid and the second differential operational amplifier of the second nmos pass transistor in the pre-driver circuitry
End connection；One end of 5th resistance is connected with the source electrode of the 3rd nmos pass transistor, the other end of the 5th resistance
It is connected with the source electrode of second PMOS transistor；The drain electrode of second PMOS transistor is connected with earth point, and described second
The grid of PMOS transistor and the grid and the 3rd differential operational amplifier of the first PMOS transistor in the pre-driver circuitry
Output end connection.
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| US6188212B1 (en) * | 2000-04-28 | 2001-02-13 | Burr-Brown Corporation | Low dropout voltage regulator circuit including gate offset servo circuit powered by charge pump |
| JP4458457B2 (en) * | 2003-07-04 | 2010-04-28 | 株式会社リコー | Semiconductor device |
| CN1928766A (en) * | 2005-09-07 | 2007-03-14 | 株式会社瑞萨科技 | Reference voltage generating circuit, a semiconductor integrated circuit and a semiconductor integrated circuit apparatus |
| US8222927B2 (en) * | 2009-04-09 | 2012-07-17 | Mediatek Inc. | Reference buffer circuit |
| CN101930245A (en) * | 2009-10-10 | 2010-12-29 | 曹先国 | Precise reference voltage generator |
| JP5829072B2 (en) * | 2011-08-11 | 2015-12-09 | ルネサスエレクトロニクス株式会社 | Voltage generation circuit |
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