CN105677932A - Statistical timing analysis method used for post-silicon adjustable register circuits - Google Patents

Abstract

The invention belongs to the technical field of integrated circuits, in particular to a statistical timing analysis method used for post-silicon adjustable register circuits.The method comprises following steps: compressing a principal component to obtain N independent random variables; generating sparse grid collocation points; calculating the minimum clock cycle of each collocation point; calculating the generalized polynomial chaos coefficient of the minimum clock cycle; and calculating the yield rate of post-silicon adjustable register circuits.The statistical timing analysis method used for post-silicon adjustable register circuits has following beneficial effects: the method is high in feasibility and helps greatly reduce program operation time while obtaining precision comparable to the conventional method; and the statistical timing analysis method can be used for solving the large-scale statistical timing analysis problem of post-silicon adjustable register circuits.

Description

Statistical timing analysis method for post-strip silicon adjustable register circuit

Technical Field

The invention belongs to the technical field of integrated circuits, and relates to a statistical timing analysis method for a post-silicon adjustable register circuit.

Technical Field

As integrated circuit feature sizes have decreased below 100nm, process variation has become one of the major challenges for circuit timing performance. The post-silicon tunable clock tree is a powerful technique for repairing timing violations caused by process deviations [1,2 ]. In the post-silicon tunable clock tree, post-silicon tunable registers are inserted into the clock tree during the design phase. The delay of the post-silicon adjustable register can be adjusted by changing the control signal. A typical post-silicon tunable register structure is shown in FIG. 2 [1 ]. After chip production, the time margins of the register states can be balanced by changing the delay of the post-silicon tunable registers, a process known as post-silicon tuning. During post-silicon tuning, more time margin is allocated into the critical path to fix timing violations. The post-silicon tunable clock tree technique has been widely applied to clock networks [3-6] in Intel processors, and this technique can significantly improve yield and performance. However, it also introduces additional costs, such as area and power consumption.

Therefore, over the past decades, various approaches have been proposed to optimize circuits with post-silicon tunable registers. These optimization methods focus on reducing the post-silicon tunable register overall size while ensuring yield. For example, document [2] proposes a perturbation method based on post-silicon tunable clock tree synthesis. In this method, a circuit statistical timing analysis with a post-silicon tunable register is invoked in each iteration. The overall size of the post-silicon tunable register may then be optimized based on the results of the statistical timing analysis. In such an optimization process, statistical timing analysis of the circuit with the post-silicon tunable register may be performed over 1000 times. Therefore, the efficiency of statistical timing analysis is crucial for post-silicon tunable register optimization algorithms. In document [2], a monte carlo-based linear programming method is used to perform statistical timing analysis. This optimization process takes over 30 hours for some test cases in the ISCAS89 due to the poor performance of the method.

Several relatively efficient statistical timing analysis methods have been proposed over the past years for statistical timing analysis with post-silicon tunable register circuits in the event of process fluctuations [7-15 ]. These methods use first or second order polynomials to approximate the statistical delay of the combinatorial circuit between registers. However, the statistical timing analysis with post-silicon tunable register circuits is different from the conventional statistical timing analysis problem. For conventional statistical timing analysis, the combinatorial circuits between registers are modeled as a non-circular graph. Conventional statistical timing analysis methods look for statistical polynomial approximations of the delay of the combinational circuit by traversing the acyclic graph. For statistical timing analysis of circuits with post-silicon tunable registers, the combined circuit and the post-silicon tunable registers in the clock tree are considered together to determine the time yield of the circuit. Thus, such a circuit can be modeled as a loop diagram. Statistical timing analysis looks at finding the statistical minimum average loop (circuit statistics minimum clock period) from the loop map. This problem is very similar to the statistical timing analysis of transparent latch circuits [16 ]. The difficulty with this problem is that the number of rings in a cyclic graph is exponential to the number of edges.

Due to the lengthy running time of the direct model carro method, a fast statistical timing analysis method for post-band silicon tunable register circuits has recently been proposed in document [17 ]. To avoid exhausting all of the rings, the vertices in the graph are subtracted one by one until there is only one vertex in the graph. To maintain the balance of the pruned graph, some extra edges are added to the graph. A heuristic method is proposed in document [17] that reduces the number of edges by removing the least weighted edges. However, the efficiency and accuracy of this approach is highly dependent on the circuit architecture.

The prior art related to the present invention is the following references:

[1]J.-L.Tsai,D.Baik,C.C.-P.Chen,andK.K.Saluja,“Ayieldimprovementmethodologyusingpre-andpost-siliconstatisticalclockscheduling,”inProceedingsofthe2004IEEE/ACMInternationalconferenceonComputer-aideddesign.IEEEComputerSociety,2004,pp.611–618.

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[10]L.Zhang,W.Chen,Y.Hu,J.A.Gubner,andC.C.-P.Chen,“Correlation-preservednon-gaussianstatisticaltiminganalysiswithquadratictimingmodel,”inProceedingsofthe42ndannualDesignAutomationConference.ACM,2005,pp.83–88.

[11]Y.Zhan,A.J.Strojwas,X.Li,L.T.Pileggi,D.Newmark,andM.Sharma,“Correlation-awarestatisticaltiminganalysiswithnon-gaussiandelaydistributions,”inDesignAutomationConference,2005.Proceedings.42nd.IEEE,2005,pp.77–82.

[12]V.KhandelwalandA.Srivastava,“Ageneralframeworkforaccuratestatisticaltiminganalysisconsideringcorrelations,”inProceedingsofthe42ndannualDesignAutomationConference.ACM,2005,pp.89–94.

[13]C.Visweswariah,K.Ravindran,K.Kalafala,S.G.Walker,S.Narayan,D.K.Beece,J.Piaget,N.Venkateswaran,andJ.G.Hemmett,“First-orderincrementalblock-basedstatisticaltiminganalysis,”Computer-AidedDesignofIntegratedCircuitsandSystems,IEEETransactionson,vol.25,no.10,pp.2170–2180,2006.

[14]K.Kang,B.C.Paul,andK.Roy,“Statisticaltiminganalysisusinglevelizedcovariancepropagation,”inDesign,AutomationandTestinEurope,2005.Proceedings.IEEE,2005,pp.764–769.

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[16]R.ChenandH.Zhou,“Statisticaltimingverificationfortransparentlylatchedcircuits,”Computer-AidedDesignofIntegratedCircuitsandSystems,IEEETransactionson,vol.25,no.9,pp.1847–1855,2006.

[17]B.Li,N.Chen,andU.Schlichtmann,“Faststatisticaltiminganalysisforcircuitswithpost-silicontunableclockbuffers,”inComputer-AidedDesign(ICCAD),2011IEEE/ACMInternationalConferenceon.IEEE,2011,pp.111–117.

[18]H.Zhu,X.Zeng,W.Cai,J.Xue,andD.Zhou,“Asparsegridbasedspectralstochasticcollocationmethodforvariations-awarecapacitanceextractionofinterconnectsundernanometerprocesstechnology,”inDATE.IEEE,2007,pp.1–6.

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disclosure of Invention

The invention aims to provide a brand-new random configuration-based statistical timing analysis method for a post-strip silicon adjustable register circuit. The method of the invention adopts Howard algorithm to calculate the clock period of the circuit on less than 100 determined sparse grid configuration points. Then, the yield of the circuit is estimated according to the random configuration theory based on the obtained clock cycles. Compared with the prior art, the method can obviously reduce the program running time and improve the efficiency of the statistical time sequence analysis of the adjustable register circuit with the back silicon under the condition of obtaining the precision which is comparable to that of the prior art.

The statistical timing analysis method for the post-silicon adjustable register circuit comprises the following steps, and the flow is shown in figure 1.

And step 1, compressing the principal component to obtain N independent random variables.

The present invention uses a generalized random configuration approach to address process fluctuations [18,19 ]]. For relevant process parameters, the invention can firstly carry out Principal Component Analysis (PCA) or Independent Component Analysis (ICA) to obtain a group of N random variablesFor post-band silicon tunable register circuits, from register FFi to FF_jMaximum and minimum delay of logic pathAre all independent random variablesAs a function of (c). In the present invention, we useIndicating a delay in the event of process fluctuations. Counting the minimum clock period T_minIs also a function of these independent random variables, and can be approximated by generalized polynomial chaotic spreading_min，

$T_{\min }\left(\stackrel{\→}{\mathrm{\ξ}}\right)\≈{\tilde{T}}_{\min }\left(\stackrel{\→}{\mathrm{\ξ}}\right)={\mathrm{\Σ}}_{i_1+...+i_N=0}^M{t}_{i_1,...,i_N}{H}_N^{i_1,...,i_N},$

Wherein M is the maximum valence of the polynomial,representing N-dimensional generalized polynomial chaos, i₁+…+i_NIs the order of the generalized polynomial chaos. Coefficient of performanceBy making the clock period T at a set of configuration points_minAnd corresponding polynomial chaos is equal.Is a precise valueAre approximations.

And 2, generating sparse grid configuration points.

Generating sparse grid configuration pointsP is the number of configuration points. The generalized polynomial chaotic coefficient can obtain a high-precision numerical solution through Gauss-Hermite integration. The gaussian-hermite integral of order l precision of the one-dimensional integral in the generalized form is shown as follows,

${\∫}_{-\∞}^{+\∞}f\left(\mathrm{\ξ}\right)\mathrm{\ρ}\left(\mathrm{\ξ}\right)\mathrm{d\ξ}\≈{\mathrm{\Σ}}_{i=1}^{l}f\left({\mathrm{\ξ}}_i^l\right)w_i^l,$

where f (ξ) is the integrand, ρ (ξ) d ξ is a Gaussian measure,is a configuration point of the ith real root of a one-dimensional hermitian polynomial of the order of l,are the corresponding weights [18,19]。

To solve for multidimensional integrals, document [22 ]]A tensor product approach is proposed to construct the multidimensional configuration points. Order to ${\mathrm{\Θ}}_1^l=\{{\mathrm{\ξ}}_1^l,...,{\mathrm{\ξ}}_l^l\}$ Represents a one-dimensional configuration point and is, $W_1^l=\{{\mathrm{\ξ}}_1^l,...,{\mathrm{\ξ}}_l^l\}$ representing the corresponding weight. The multi-dimensional configuration points and corresponding weights may be formalized,

$T_d^l={\mathrm{\Θ}}_1^{i_1}\⊗...\⊗{\mathrm{\Θ}}_l^{i_d},---\left(2\right)$

$W_d^l=W_1^{i_1}\⊗...\⊗W_l^{i_d},---\left(3\right)$

wherein i_j1, 2. The number of multidimensional Gauss-Hermite integral configuration points is (l +1)^dI.e. grows exponentially with the dimension d. Therefore, in practical applications, it is desirable to reduce the number of configuration points.

The invention uses sparse grid techniques [18,19 ]]To reduce the number of multi-dimensional integral configuration points, letRepresents one dimension i_jA price precision Gaussian integral configuration point is configured,the corresponding weight can be calculated by the following steps:

2.1 computing multidimensional configuration points

For a d-dimensional integral of k-order precision, a set of configuration points generated using a sparse grid isIs given by the equation,

${\mathrm{\Θ}}_d^l={{\∪}_{l+1\≤\left|\stackrel{\→}{l}\right|\≤d+l}\mathrm{\Θ}}_1^{i_1}\×...\×{\mathrm{\Θ}}_l^{i_d},$

wherein, $\left|\stackrel{\→}{l}\right|=i_1+...+i_d.$

2.2 computing the corresponding weights of the multidimensional configuration points

Corresponding to the configuration pointThe weight of (a) is given by,

$w_{j_{i_1,...,j_{i_d}}={(-1)}^{d+l-\left|\stackrel{\→}{l}\right|}\left(\begin{array}{c}d-1\\ d+l-\left|\stackrel{\→}{l}\right|\end{array}\right)({\stackrel{\→}{\mathrm{\Θ}}}_{j_{i_1}}^{i_1}...{\stackrel{\→}{\mathrm{\Θ}}}_{j_{i_d}}^{i_d}).---\left(5\right)}^{i_1,...,i_d}$

it can be shown that the sparse grid is accurate for all polynomials with d-variable orders up to (2l + 1). The number of sparse grid configuration points can be calculated by the following formula:

$N_{\mathrm{sg}}=\dim \left({\mathrm{\Θ}}_d^l\right)~\frac{2^l}{l1}{d}^l~2^l\dim \left({\mathrm{\π}}_d^l\right),d>>1,---\left(6\right)$

wherein,and (3) the generalized polynomial chaos of which all d-dimensional orders are at most l is expressed. Compared with the tensor product strategy, the sparse grid technique avoids the exponentially increasing computational cost related to the dimension size.

And 3, calculating the minimum clock period of each configuration point.

For each configuration point, the inventive method uses an efficient minimum loop ratio algorithm to calculate the minimum clock period. This process comprises the following four substeps.

3.1 construct a weighted constraint graph, containing both circuit logic and a circuit clock tree.

Constructing a weighted constraint graph containing circuit logic and circuit clock tree information, wherein the weight of each edge is defined as follows:

${\mathrm{\ω}}_{\mathrm{ij}}=\left\{\begin{array}{c}{T}_{\mathrm{init}}-.D_{\mathrm{ij}},\∀(i,j)\∈E_s,\\ d_{\mathrm{ij}},\∀(j,i)\∈E_h,\\ R_{\mathrm{ij}},\∀(i,j)\∈E_{\mathrm{pst}},\\ 0,\∀(i,j)\∈E_t,\end{array}\right.---\left(7\right)$

wherein E is_pstRepresenting a set of clock tree edges with post-silicon adjustable registers, R_ijRepresenting the delay adjustment range of the post-silicon adjustable register corresponding to the clock tree edge (i, j), E_tRepresenting the set of edges of the normal clock tree,R_ij＝R_ji。T_initis the initial value of the clock cycle which must be large enough to ensure that there are no negative rings in the weighted graph. The method of the invention uses T_initIs set to D_ijIs measured. The delay of the post-silicon tunable register may be defined as a_ij＝t_i-t_j. Then the constraint of the post-silicon tunable register | a_ij|≤R_ijCan be formalized as:

$\left\{\begin{array}{c}{t}_i-t_j\≤R_{\mathrm{ij}},\\ t_j-t_i\≤R_{\mathrm{ij}}.\end{array}\right.$

3.2 calculate each edge to correspond.

Each side corresponding to_ijCan be calculated by the following formula:

${\mathrm{\δ}}_{\mathrm{ij}}=\left\{\begin{array}{c}\mathrm{1,0}\∀(i,j)\∈E_s,\\ 0,\∀(j,i)\∈E_h,\\ 0,\∀(i,j)\∈E_{\mathrm{pst}},\\ 0,\∀(i,j)\∈E_t.\end{array}\right.---\left(8\right)$

3.3 apply Howard's algorithm to solve the minimum loop ratio problem.

Delay a of each post-silicon adjustable register_ijFrom its adjustable range R_ijConstraint, i.e. | a_ij|≤R_ij. The time constraint of the post-band silicon tunable register circuit can be formalized as:

$C_0\left(T\right)=\left\{\begin{array}{c}{t}_i-t_j-T\≤-{\tilde{D}}_{\mathrm{ij}},\∀(i,j)\∈E_s,\\ t_j-t_i\≤{\tilde{d}}_{\mathrm{ij}},\∀(j,i)\∈E_h,\\ t_i={\mathrm{\Σ}}_{\∀(s,t)\∈P_i}{a}_{\mathrm{st}}+d_i^0,\∀i\∈N,\\ \left|a_{\mathrm{st}}\right|\≤R_{\mathrm{st}},\∀{\mathrm{buf}}_{\mathrm{st}}\∈\mathrm{Buf},\end{array}\right.---\left(9\right)$

wherein Buf represents a set of post-silicon tunable registers in a clock tree, P_iRepresenting data from the root node of the clock tree to register FF_iThe clock path of (a) is,representing a clock path P_iInitial delay of (a)_stPost-representation silicon tunable register buf_stTime delay of R_stPost-representation silicon tunable register buf_stThe adjustable range of (2).Represents from FF_iTo FF_jMaximum and minimum delay. For simplicity, we assume

The method of the invention adopts a minimum loop ratio algorithm to calculate the minimum clock period. In the present invention, the Howard algorithm [20] is used to solve the minimum loop ratio problem. The optimization problem of calculating the minimum clock period can be expressed as follows,

$\begin{array}{cc}\mathrm{Maximize}& \mathrm{\λ},\\ \mathrm{Subjectto}& t_i-t_j\≤{\mathrm{\ω}}_{\mathrm{ij}}-\mathrm{\λ}\·{\mathrm{\δ}}_{\mathrm{ij}},\∀(i,j)\∈E,\\ \mathrm{Varibles}& \mathrm{\λ},t.\end{array}---\left(10\right)$

the constraint in the above problem is equivalent to the constraint in equation (9). It can be seen that the setup time constraint and the hold time constraint do not change after the transformation, the only difference being the post-silicon tunable register constraint. The invention assumes that the arrival time of each vertex clock in the clock tree is t_i. For each rising edge (i, j) in the clock tree, the delay of the post-silicon tunable register is a_ij＝t_i-t_j. Adjustable register buf for each post-silicon_ijIt is at E_pstThere are two corresponding edges (i, j) and (j, i). Therefore, constrain | a_ij|≤R_ij，R_ij＝R_ji，Equivalent to t_i-t_j≤R_ij， $\∀(i,j)\∈E_{\mathrm{pst}}.$

3.4 calculate the minimum clock period.

After solving the minimum loop ratio problem, the maximum value of λ can be obtained, which is denoted as λ ×. The minimum clock period is T_min＝T_init-λ*。

And 4, calculating the minimum clock period generalized polynomial chaotic expansion coefficient.

Unknown coefficientThe Galerkin method [21 ] can be used]By minimizationAndthe error between the two is obtained, i.e.,

$<T_{\min }\left(\stackrel{\&RightArrow;}{\mathrm{\&xi;}}\right)-{\tilde{T}}_{\min }\left(\stackrel{\&RightArrow;}{\mathrm{\&xi;}}\right),H_N^{i_1,...,i_N}\left(\stackrel{\&RightArrow;}{\mathrm{\&xi;}}\right)>=0,---\left(11\right)$

for all (i)₁+…+i_N) 0, 1, …, M. Here,. represents the inner product [19,20 ]]. By exploiting the orthogonality of the polynomial chaos, the unknown coefficients can be calculated [18,19 ]]，

$t_{i_1,...,i_N}={<T}_{\min }\left(\stackrel{\&RightArrow;}{\mathrm{\&xi;}}\right),H_N^{i_1,...,i_N}\left(\stackrel{\&RightArrow;}{\mathrm{\&xi;}}\right)>.---\left(12\right)$

Equation (12) is a multidimensional integral that can be approximated by numerical integration at the configuration points, i.e.:

$t_{i_1,...,i_N}={\mathrm{\&Sigma;}}_{k=1}^P{w}_k{T}_{\min }\left({\stackrel{\&RightArrow;}{\mathrm{\&xi;}}}_k\right)H_N^{i_{1,...,i_N}}\left({\stackrel{\&RightArrow;}{\mathrm{\&xi;}}}_k\right),---\left(13\right)$

wherein,is the point of the k-th configuration,is a point of deploymentThis value has been calculated in step 3 at the minimum clock period.

And 5, calculating the yield of the silicon adjustable register circuit with the band.

Statistical timing analysis of the post-strip silicon tunable register circuit is defined as finding yield y (T),

y(T)＝Prob(T≤T₀)，(14)

where Prob represents a probability function.

At the time of obtaining statistical minimum clock periodAfter the polynomial chaotic expansion of (a),may also be calculated. The yield of the register circuit with the post-silicon adjustable can be determined according toThe cumulative probability function of (a) is calculated.

Through the steps, the invention can obtain the final result of the statistical timing analysis of the post-silicon adjustable register circuit. The method for analyzing the statistical timing sequence of the circuit with the post-silicon adjustable register has the following advantages:

1. the invention applies the random configuration method in the statistical timing analysis of the circuit of the post-silicon adjustable register for the first time, reduces the number of configuration points of multi-dimensional integration by using the sparse grid technology, and avoids the exponentially increased calculation cost related to the dimension size.

2. The method is relatively efficient, can obviously reduce the program running time under the condition of obtaining the precision which is comparable to that of the existing method, and can be used for solving the problem of statistical time sequence analysis of a large-scale post-silicon adjustable register circuit.

Drawings

FIG. 1 is a flow chart of the method of the present invention;

FIG. 2 is a diagram of an exemplary post-silicon tunable register structure;

FIG. 3(a) is a timing circuit diagram according to a first embodiment of the present invention;

FIG. 3(b) is a timing constraint diagram of the first embodiment of the present invention;

FIG. 3(c) is a schematic diagram of the first embodiment of the present invention with weight constraint;

FIG. 3(d) is a diagram illustrating the corresponding calculation according to the first embodiment of the present invention.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. It is specifically noted that the particular embodiments and drawings are illustrative only and that various modifications and changes in light thereof will be suggested to persons skilled in the art and are to be included within the spirit and purview of this application. In addition, the present invention incorporates publications which are intended to describe the invention more clearly and which are incorporated herein by reference in their entirety and to the extent that they have been repeated in their entirety.

Example 1 serves to illustrate the main steps of the process of the invention.

The implementation steps of the statistical timing analysis method for the circuit with the post-silicon adjustable register are shown in figure 1.

FIG. 3(a) is an example of a sequential circuit with logic path delay. Fig. 3(b) is its corresponding timing constraint. Each vertex in fig. 3(b) represents one register in fig. 3 (a). Each logic path in fig. 3(a) corresponds to two timing constraint edges in fig. 3 (b). For example, from FF in FIG. 3(a)₁To FF₂The logical path delay of (3). From FF₁To FF₂The maximum delay and the minimum delay are both 3. Then two corresponding timing constraint edges should be added in fig. 3 (b). The edges (1, 2) correspond to establishing a time constraint as:

t_i-t_j≤T-3。

the edges (1, 2) correspond to a retention time constraint of:

t_i-t_j≤3。

the circuit statistical timing analysis process is as follows:

and step 1, compressing the principal component to obtain N independent random variables.

And 2, generating sparse grid configuration points.

The configuration points are as follows:

${\mathrm{\&Theta;}}_d^l={\&cup;}_{l+1\&le;\left|\stackrel{\&RightArrow;}{l}\right|\&le;d+l}{\mathrm{\&Theta;}}_1^{i_1}\&times;...\&times;{\mathrm{\&Theta;}}_l^{i_d},$

wherein, $\left|\stackrel{\&RightArrow;}{l}\right|=i_1+...+i_d.$ the corresponding weights are:

$w_{j_{i_1,...,j_{i_d}}={(-1)}^{d+l-\left|\stackrel{\&RightArrow;}{l}\right|}\left(\begin{array}{c}d-1\\ d+l-\left|\stackrel{\&RightArrow;}{l}\right|\end{array}\right)({\stackrel{\&RightArrow;}{\mathrm{\&Theta;}}}_{j_{i_1}}^{i_1}...{\stackrel{\&RightArrow;}{\mathrm{\&Theta;}}}_{j_{i_d}}^{i_d}).}^{i_1,...,i_d}$

and 3, calculating the minimum clock period of each configuration point, and comprising the following steps:

step 3.1: and constructing a weighted constraint graph, and simultaneously containing circuit logic and a circuit clock tree. FIG. 3(c) is a diagram of the weighted constraint, which includes the circuit of FIG. 3(a) and a clock tree. The solid lines represent logical paths and the dashed lines represent clock tree edges.

Step 3.2: each edge correspondence is calculated. The correspondence of the constraint map shown in fig. 3(c) is shown in fig. 3 (d).

Step 3.3: and solving the problem of the minimum ring ratio by applying Howard algorithm. Solving the minimum loop ratio problem to obtain the optimal value lambda.

Step 3.4: the minimum clock period is calculated. After solving the minimum loop ratio problem, we can get the maximum value of λ, denoted as λ ×. The minimum clock period is T_min＝T_init-λ*。

And 4, calculating the minimum clock period generalized polynomial chaotic expansion coefficient.

$t_{i_1,...,i_N}={\mathrm{\&Sigma;}}_{k=1}^P{w}_k{T}_{\min }\left({\stackrel{\&RightArrow;}{\mathrm{\&xi;}}}_k\right)H_N^{i_1,...,i_N}\left({\stackrel{\&RightArrow;}{\mathrm{\&xi;}}}_k\right),$

Wherein,is the point of the k-th configuration,is a point of deploymentThis value has been calculated in step 3 at the minimum clock period.

And 5, calculating the yield of the silicon adjustable register circuit with the band.

Statistical timing analysis of the post-strip silicon tunable register circuit is defined as finding yield y (T),

y(T)＝Prob(T≤t₀)，

where Prob represents a probability function.

Example 2 is used to show that the statistical timing analysis method proposed by the present invention can significantly reduce the program running time while obtaining a precision comparable to that of the existing method.

In the present embodiment, a similar arrangement to that of document [17] is employed. The results obtained by the Monte Carlo method with 10000 sampling points are used as a comparison standard for judging the accuracy. The test circuit is from ISCAS89, and the basic cell gates in the test circuit are mapped to the internal 65nm cell library. In this embodiment, each register has a post-silicon adjustable register, and the adjustment range of each register is set to be 0.3 times of the delay of the longest path of the circuit. In the monte carlo method and the method of the present invention, 6 random variables (transistor length, transistor width, threshold voltage of NMOSFET and PMOSFET) are used to model the process fluctuations. The standard deviation of these independent random variables was set to 10% of the nominal value. In this example, a quadratic delay model is used and a logic path quadratic delay expression is obtained with SSTA method based on random configuration points [23 ]. In this SSTA engine, a deterministic STA engine is used to derive the latency of each configuration point logical path. And finally, deriving a secondary delay expression according to a random configuration theory. Test cases and results are shown in table 1. # Nodes and # Edges denote the number of vertices and Edges in the timing constraint graph. Err (μ) represents the minimum clock cycle mean relative error and Err (σ) represents the minimum clock cycle standard deviation relative error. Merge represents the method in document [17 ]. Runtime includes random configuration point generation, minimum clock cycle calculation, and yield calculation.

The average value of the minimum clock period relative error of the method is 0.16 percent and is obviously smaller than the method in the document [17 ]. The mean value of the standard deviation relative error of the minimum clock period of the method of the invention is 0.48%, slightly higher than that of the method of document [17], but still sufficiently accurate. Therefore, the accuracy of the method of the present invention can be compared with the method of document [17 ].

As can be seen from Table 1, the process run time for small scale circuits is comparable to or longer than that of document [17 ]. However, the method of the present invention can achieve over 10 times speed-up ratio for large scale circuits. The method in document [17] is highly dependent on the circuit structure, e.g. the test circuit s1423 is much smaller in scale than s13207, but the run time of s1423 is longer than s 13207. The scale of S15850 is approximately 4 times that of S13207, but the run time of S15850 is 36 times that of S13207. In contrast, the method of the present invention is approximately linear with the number of timing constraint edges. The run time of the method of the invention is predictable and has a weak correlation with the circuit structure, which is a very good characteristic in practical application.

TABLE 1 comparison of the results of the process of the invention with the prior art process

Claims (5)

1. A statistical timing analysis method for a post-strip silicon adjustable register circuit is characterized by comprising the following steps: the method comprises the following steps:

step 1, compressing principal components to obtain N independent random variables;

step 2, generating sparse grid configuration points;

step 3, calculating the minimum clock period of each configuration point;

step 4, calculating a generalized polynomial chaotic expansion coefficient with a minimum clock period;

and 5, calculating the yield of the silicon adjustable register circuit with the band.

2. The statistical timing analysis method for a post-silicon tunable register circuit according to claim 1, wherein the generating of sparse grid configuration points in step 2 comprises the following two substeps:

step 2.1: calculating a multi-dimensional configuration point;

step 2.2: and calculating the corresponding weight of the multi-dimensional configuration point.

3. The statistical timing analysis method for a post-silicon tunable register circuit according to claim 1, wherein the step 3 of calculating the minimum clock period for each configuration point comprises the following 4 sub-steps:

step 3.1: constructing a weighted constraint graph, and simultaneously containing circuit logic and a circuit clock tree, wherein each edge is defined as follows:

${\mathrm{\&omega;}}_{\mathrm{ij}}=\left\{\begin{array}{cc}{T}_{\mathrm{init}}-D_{\mathrm{ij}},& \&ForAll;(i,j)\&Element;E_s,\\ d_{\mathrm{ij}},& \&ForAll;(j,i)\&Element;E_h,\\ R_{\mathrm{ij}},& \&ForAll;(i,j)\&Element;E_{\mathrm{pst}},\\ 0,& \&ForAll;(i,j)\&Element;E_t.\end{array}\right.$

step 3.2: the correspondence of each edge is calculated,

${\mathrm{\&delta;}}_{\mathrm{ij}}=\left\{\begin{array}{cc}1,& \&ForAll;(i,j)\&Element;E_s,\\ 0,& \&ForAll;(j,i)\&Element;E_h,\\ 0,& \&ForAll;(i,j)\&Element;E_{\mathrm{pst}},\\ 0,& \&ForAll;(i,j)\&Element;E_t.\end{array}\right.$

step 3.3: and solving the problem of the minimum ring ratio by applying Howard algorithm.

Step 3.4: the minimum clock period is calculated.

4. The statistical timing analysis method for the post-silicon tunable register circuit according to claim 1, wherein the minimum clock period generalized polynomial chaotic expansion coefficient is calculated in step 4, and is obtained by the following calculation:

$t_{i_1,...,i_N}={\mathrm{\&Sigma;}}_{k=1}^p{w}_k{T}_{\min }\left({\stackrel{\&RightArrow;}{\mathrm{\&xi;}}}_k\right)H_N^{i_1,...,i_N}\left({\stackrel{\&RightArrow;}{\mathrm{\&xi;}}}_k\right),$

wherein,is the point of the k-th configuration,is a point of deploymentAt the minimum clock period of the clock signal,representing an N-dimensional generalized polynomial chaos.

5. The statistical timing analysis method for the post-band silicon tunable register circuit according to claim 1, wherein the step 5 of calculating the yield of the post-band silicon tunable register circuit comprises: at the time of obtaining statistical minimum clock periodAfter the polynomial chaotic expansion of (a),is calculated based on the cumulative probability function of the post-strip silicon tunable register circuitThe cumulative probability function of (2) is calculated.