CN105677932A - Statistical timing analysis method used for post-silicon adjustable register circuits - Google Patents

Abstract

The invention belongs to the technical field of integrated circuits, in particular to a statistical timing analysis method used for post-silicon adjustable register circuits.The method comprises following steps: compressing a principal component to obtain N independent random variables; generating sparse grid collocation points; calculating the minimum clock cycle of each collocation point; calculating the generalized polynomial chaos coefficient of the minimum clock cycle; and calculating the yield rate of post-silicon adjustable register circuits.The statistical timing analysis method used for post-silicon adjustable register circuits has following beneficial effects: the method is high in feasibility and helps greatly reduce program operation time while obtaining precision comparable to the conventional method; and the statistical timing analysis method can be used for solving the large-scale statistical timing analysis problem of post-silicon adjustable register circuits.

Description

For with after the statistical timing analysis method of the adjustable register circuit of silicon

Technical field

The invention belongs to technical field of integrated circuits, relate to the statistical timing analysis method of the adjustable register circuit of silicon after being with.

Technical background

Along with integrated circuit feature is reduced in size to below 100nm, process deviation has become as one of significant challenge of circuit sequence performance. Rear silicon adjustable clock tree is sequential fault technology [1,2] that a kind of strong reparation causes due to process deviation. In rear silicon adjustable clock tree, rear silicon is adjustable, and depositor is inserted into clock trees in the design phase. The time delay of rear silicon is adjustable depositor can adjust by changing control signal. One the typical rear adjustable register architecture of silicon [1] as shown in Figure 2. After chip production, it is possible to balance the argin of buffer status by the time delay of the adjustable depositor of silicon after changing, this process is referred to as the tuning of rear silicon. In rear silicon tuning process, more argin is assigned in critical path and repairs sequential breaks rules. Rear silicon adjustable clock tree technology has been widely applied to the clock network [3-6] in Intel processor, and this technology can be obviously improved yield and performance. But, it also can introduce extra cost, for instance area and power consumption.

Therefore, in past many decades, various methods are suggested and optimize the circuit with the adjustable depositor of rear silicon. These optimization methods be conceived to when ensure yield reduce after the adjustable depositor overall dimension of silicon. Such as, document [2] proposes a kind of perturbation motion method comprehensive based on rear silicon adjustable clock tree. In the method, the circuit statistical timing analysis with the adjustable depositor of rear silicon is called in each iteration. Then, the overall dimension of the adjustable depositor of rear silicon can the result of Corpus--based Method Time-Series analysis be optimized. In such a kind of optimization process, the circuit statistical timing analysis with the adjustable depositor of rear silicon can be executed more than 1000 times. Therefore, the efficiency of statistical timing analysis is for most important rear silicon adjustable optimization of registers algorithm. In document [2], a kind of linear programming method based on Monte Carlo is used to carry out statistical timing analysis. Due to the performance that the method is poor, this optimization process needs consuming more than 30 hours for some test cases in ISCAS89.

The statistical timing analysis method of some relative efficiencies is suggested for statistical timing analysis [7-15] with the adjustable register circuit of rear silicon in technological fluctuation situation in the several years in past.These methods use single order or quadratic polynomial to carry out the statistical time lag of combinational circuit between Approximation Register. But, the statistical timing analysis with the adjustable register circuit of rear silicon is different from traditional statistical timing analysis problem. For conventional statistics Time-Series analysis, between depositor, combinational circuit is modeled as acyclic figure. Conventional statistics Time Series Analysis Method finds the statistics polynomial approximation of combinational circuit time delay by traveling through acyclic figure. For the statistical timing analysis with the adjustable register circuit of rear silicon, combinational circuit and after in clock trees the adjustable depositor of silicon considered to determine the time yield of circuit simultaneously. Therefore, this circuit can be modeled as ring figure. Statistical timing analysis is conceived to from there being ring figure to find statistics minimum average B configuration ring (circuit statistics minimum clock cycle). This problem and transparent latch circuit statistical timing analysis much like [16]. The where the shoe pinches of this problem is in that the number exponent function relation on number and the limit having ring figure medium ring.

Owing to direct model's Caro method runs overlong time, recently propose in the document [17] a kind of quickly for after the statistical timing analysis method of the adjustable register circuit of silicon. In order to avoid exhaustive go out all of ring, the summit in figure by one by one abatement until figure in only have a summit. In order to safeguard the balance of figure after abatement, some extra limits are added in figure. Being suggested at a kind of heuristic of document [17], the method reduces the number on limit by removing the limit of minimal weight. But, efficiency and the precision of this method are highly dependent on circuit structure.

Prior art related to the present invention has following list of references:

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[17]B.Li,N.Chen,andU.Schlichtmann,“Faststatisticaltiminganalysisforcircuitswithpost-silicontunableclockbuffers,”inComputer-AidedDesign(ICCAD),2011IEEE/ACMInternationalConferenceon.IEEE,2011,pp.111–117.

[18]H.Zhu,X.Zeng,W.Cai,J.Xue,andD.Zhou,“Asparsegridbasedspectralstochasticcollocationmethodforvariations-awarecapacitanceextractionofinterconnectsundernanometerprocesstechnology,”inDATE.IEEE,2007,pp.1–6.

[19]H.Zhu,X.Zeng,X.Luo,andW.Cai,“Generalizedstochasticcollocationmethodforvariation-awarecapacitanceextractionofinterconnectsconsideringarbitraryrandomprobability,”IEICEtransactionsonelectronics,vol.92,no.4,pp.508–516,2009.

[20]R.A.Howard,DynamicProgrammingandMarkovProcess.TheMITpress,1960.

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Summary of the invention

It is an object of the invention to provide a kind of brand-new based on random arrangement for the adjustable register circuit statistical timing analysis method of silicon after band. The inventive method adopts Howard algorithm clock cycle of counting circuit on the sparse grid collocation point determined less than 100. Then calculate the yield of circuit according to random arrangement theory from these clock cycle tried to achieve. Comparing with existing method, the present invention under obtaining the precise manner comparable with existing method, can substantially reduce program runtime, improves the efficiency of the statistical timing analysis of the adjustable register circuit of silicon after being with.

The present invention propose for after the statistical timing analysis method of the adjustable register circuit of silicon, comprise the steps, flow process is as shown in Figure 1.

The compression of step 1. pivot obtains N number of independent random variable.

The present invention uses broad sense random arrangement method to process technological fluctuation [18,19]. For relevant technological parameter, the present invention can first carry out a pivot analysis (PCA) or independent component analysis (ICA) obtains one group of N number of stochastic variableFor the adjustable register circuit of silicon after band, from depositor FFi to FF_jLogical path time delay maximum, minimumIt it is all independent random variableFunction. In the present invention, Wo MenyongRepresent the time delay in technological fluctuation situation. Statistics minimum clock cycle T_minAlso it is the function of these independent random variables, and T can be similar to the extension of generalized polynomial chaos_min,

$T_{\min }\left(\stackrel{\→}{\mathrm{\ξ}}\right)\≈{\tilde{T}}_{\min }\left(\stackrel{\→}{\mathrm{\ξ}}\right)={\mathrm{\Σ}}_{i_1+...+i_N=0}^M{t}_{i_1,...,i_N}{H}_N^{i_1,...,i_N},$

Wherein, M is multinomial highest price,Represent that N ties up generalized polynomial chaos, i₁+…+i_NIt it is generalized polynomial chaos exponent number. CoefficientCan pass through to make clock cycle T on one group of collocation point_minWith corresponding polynomial chaos is equal obtains.It it is exact valueIt it is approximation.

Step 2. generates sparse grid collocation point.

Generate sparse grid collocation pointP is collocation point number. Generalized polynomial chaotic parameter can obtain high-precision numerical solution by Gauss-Hermite integration. The l rank precision Gauss-Hermite integration of the one-dimensional integration of generalized form is shown below,

${\∫}_{-\∞}^{+\∞}f\left(\mathrm{\ξ}\right)\mathrm{\ρ}\left(\mathrm{\ξ}\right)\mathrm{d\ξ}\≈{\mathrm{\Σ}}_{i=1}^{l}f\left({\mathrm{\ξ}}_i^l\right)w_i^l,$

Wherein, f (ξ) is integrand, and ρ (ξ) d ξ is Guass measure,It is the collocation point taking the one-dimensional Hermite polynomial i-th real root in l rank,It is corresponding weight [18,19].

In order to solve multidimensional integral, document [22] proposes tensor product method and builds multidimensional collocation point. Order ${\mathrm{\Θ}}_1^l=\{{\mathrm{\ξ}}_1^l,...,{\mathrm{\ξ}}_l^l\}$ Represent one-dimensional collocation point, $W_1^l=\{{\mathrm{\ξ}}_1^l,...,{\mathrm{\ξ}}_l^l\}$ Represent respective weights. Then multidimensional collocation point and respective weights can form turn to,

$T_d^l={\mathrm{\Θ}}_1^{i_1}\⊗...\⊗{\mathrm{\Θ}}_l^{i_d},---\left(2\right)$

$W_d^l=W_1^{i_1}\⊗...\⊗W_l^{i_d},---\left(3\right)$

Wherein, i_j=l, j=1,2 ..., d. Multidimensional Gauss-Hermite integration collocation point number is (l+1)^d, namely it is exponentially increased with dimension size d. Therefore need to reduce the number of collocation point in actual applications.

The present invention uses sparse grid technology [18,19] to reduce the number of multidimensional integral collocation point, orderRepresent one-dimensional i_jValency precision Gauss integration collocation point,For respective weights, then can calculate as follows and obtain:

2.1 calculate multidimensional collocation point

D-for a k-rank precision ties up integration, and the one group of collocation point generated with sparse grid isThe linear combination of tensor product, be given by,

${\mathrm{\Θ}}_d^l={{\∪}_{l+1\≤\left|\stackrel{\→}{l}\right|\≤d+l}\mathrm{\Θ}}_1^{i_1}\×...\×{\mathrm{\Θ}}_l^{i_d},$

Wherein, $\left|\stackrel{\→}{l}\right|=i_1+...+i_d.$

2.2 calculate the corresponding weight of multidimensional collocation point

Corresponding to collocation pointWeight be given by,

$w_{j_{i_1,...,j_{i_d}}={(-1)}^{d+l-\left|\stackrel{\→}{l}\right|}\left(\begin{array}{c}d-1\\ d+l-\left|\stackrel{\→}{l}\right|\end{array}\right)({\stackrel{\→}{\mathrm{\Θ}}}_{j_{i_1}}^{i_1}...{\stackrel{\→}{\mathrm{\Θ}}}_{j_{i_d}}^{i_d}).---\left(5\right)}^{i_1,...,i_d}$

May certify that, all d-variable exponent numbers being at most to the multinomial of (2l+1), sparse grid is accurate. Sparse grid collocation point number can be calculated by following formula and obtain:

$N_{\mathrm{sg}}=\dim \left({\mathrm{\Θ}}_d^l\right)~\frac{2^l}{l1}{d}^l~2^l\dim \left({\mathrm{\π}}_d^l\right),d>>1,---\left(6\right)$

Wherein,Represent that all d-tie up exponent number and are at most the generalized polynomial chaos of l. Compare with tensor product strategy, sparse grid technology avoid relevant with dimension size be exponentially increased assess the cost.

Step 3. calculates the minimum clock cycle of each collocation point.

For each collocation point, the inventive method uses efficient minimum ring ratio algorithm to calculate minimum clock cycle. This process comprises following four sub-steps.

3.1 build cum rights constraints graph, comprise circuit logic and circuit clock tree simultaneously.

Building and comprise circuit logic and the cum rights constraints graph of circuit clock tree information, the weight definition of each edge is as follows:

${\mathrm{\ω}}_{\mathrm{ij}}=\left\{\begin{array}{c}{T}_{\mathrm{init}}-.D_{\mathrm{ij}},\∀(i,j)\∈E_s,\\ d_{\mathrm{ij}},\∀(j,i)\∈E_h,\\ R_{\mathrm{ij}},\∀(i,j)\∈E_{\mathrm{pst}},\\ 0,\∀(i,j)\∈E_t,\end{array}\right.---\left(7\right)$

Wherein, E_pstRepresent and gather with rear silicon adjustable register clock tree limit, R_ijRepresent corresponding to clock trees limit (i, the adjustable depositor delay adjustment scope of rear silicon j), E_tRepresent the set of normal clock tree limit,R_ij=R_ji。T_initBeing clock cycle initial value, this value must be large enough to ensure to be absent from negative ring in weighted graph. The inventive method is by T_initIt is set to D_ijMaximum. The time delay of rear silicon is adjustable depositor can be defined as a_ij=t_i-t_j. The constraint of the adjustable depositor of silicon after then | a_ij|≤R_ijCan be turned to by form:

$\left\{\begin{array}{c}{t}_i-t_j\≤R_{\mathrm{ij}},\\ t_j-t_i\≤R_{\mathrm{ij}}.\end{array}\right.$

3.2 calculate the corresponding δ of each edge.

The δ that each edge is corresponding_ijCan be calculated by equation below and obtain:

${\mathrm{\δ}}_{\mathrm{ij}}=\left\{\begin{array}{c}\mathrm{1,0}\∀(i,j)\∈E_s,\\ 0,\∀(j,i)\∈E_h,\\ 0,\∀(i,j)\∈E_{\mathrm{pst}},\\ 0,\∀(i,j)\∈E_t.\end{array}\right.---\left(8\right)$

3.3 application Howard Algorithm for Solving minimum ring ratio problems.

Each rear silicon is adjustable depositor time delay a_ijBy its adjustable extent R_ijConstraint, namely | a_ij|≤R_ij. Then after band, the time-constrain of the adjustable register circuit of silicon can form turn to:

$C_0\left(T\right)=\left\{\begin{array}{c}{t}_i-t_j-T\≤-{\tilde{D}}_{\mathrm{ij}},\∀(i,j)\∈E_s,\\ t_j-t_i\≤{\tilde{d}}_{\mathrm{ij}},\∀(j,i)\∈E_h,\\ t_i={\mathrm{\Σ}}_{\∀(s,t)\∈P_i}{a}_{\mathrm{st}}+d_i^0,\∀i\∈N,\\ \left|a_{\mathrm{st}}\right|\≤R_{\mathrm{st}},\∀{\mathrm{buf}}_{\mathrm{st}}\∈\mathrm{Buf},\end{array}\right.---\left(9\right)$

Wherein, Buf represents the adjustable set of registers of silicon after in clock trees, P_iRepresent from clock trees root node to depositor FF_iClock path,Represent clock path P_iOn initial time delay, a_stThe adjustable depositor buf of silicon after expression_stTime delay, R_stThe adjustable depositor buf of silicon after expression_stAdjustable extent.Represent from FF_iTo FF_jMinimum and maximum time delay. For the sake of simplicity, it is assumed that

The inventive method adopts minimum ring ratio algorithm to calculate minimum clock cycle. In the present invention, Howard algorithm [20] is used to solve minimum ring ratio problem. The optimization problem calculating minimum clock cycle can be expressed as follows,

$\begin{array}{cc}\mathrm{Maximize}& \mathrm{\λ},\\ \mathrm{Subjectto}& t_i-t_j\≤{\mathrm{\ω}}_{\mathrm{ij}}-\mathrm{\λ}\·{\mathrm{\δ}}_{\mathrm{ij}},\∀(i,j)\∈E,\\ \mathrm{Varibles}& \mathrm{\λ},t.\end{array}---\left(10\right)$

Constraint in the problems referred to above and the constraint in formula (9) are of equal value. It can be seen that setup time constraint and retention time constraint do not change after the conversion, difference is only that the adjustable depositor constraint of rear silicon. Present invention assumes that in clock trees that each summit clock time of advent is t_i. For every rising edge in clock trees, (i, j), the time delay of rear silicon is adjustable depositor is a_ij=t_i-t_j. For the adjustable depositor buf of each rear silicon_ij, it is at E_pstHave two corresponding limits (i, j) and (j, i). Therefore, constraint | a_ij|≤R_ij, R_ij=R_ji,It is equivalent to t_i-t_j≤R_ij, $\∀(i,j)\∈E_{\mathrm{pst}}.$

3.4 calculate minimum clock cycle.

After having solved above-mentioned minimum ring ratio problem, it is possible to obtain the maximum of λ, be designated as λ *. Then minimum clock cycle is T_min=T_init-λ*。

Step 4. calculates minimum clock cycle generalized polynomial chaos expansion coefficient.

Unknowm coefficientGalerkin method [21] can be adopted, by minimizingWithBetween error obtain, even,

$<T_{\min }\left(\stackrel{\&RightArrow;}{\mathrm{\&xi;}}\right)-{\tilde{T}}_{\min }\left(\stackrel{\&RightArrow;}{\mathrm{\&xi;}}\right),H_N^{i_1,...,i_N}\left(\stackrel{\&RightArrow;}{\mathrm{\&xi;}}\right)>=0,---\left(11\right)$

For all (i₁+…+i_N)=0,1 ..., M. Here <, > represent inner product [19,20]. By utilizing the orthogonality of polynomial chaos, unknowm coefficient can be computed [18,19],

$t_{i_1,...,i_N}={<T}_{\min }\left(\stackrel{\&RightArrow;}{\mathrm{\&xi;}}\right),H_N^{i_1,...,i_N}\left(\stackrel{\&RightArrow;}{\mathrm{\&xi;}}\right)>.---\left(12\right)$

Formula (12) is multidimensional integral, it is possible to by being similar in the numerical integration at collocation point place, it may be assumed that

$t_{i_1,...,i_N}={\mathrm{\&Sigma;}}_{k=1}^P{w}_k{T}_{\min }\left({\stackrel{\&RightArrow;}{\mathrm{\&xi;}}}_k\right)H_N^{i_{1,...,i_N}}\left({\stackrel{\&RightArrow;}{\mathrm{\&xi;}}}_k\right),---\left(13\right)$

Wherein,It is kth collocation point,It it is collocation pointPlace's minimum clock cycle, this value calculates in step 3 and obtains.

Step 5. calculates the yield of the adjustable register circuit of silicon after being with.

After band, the statistical timing analysis of the adjustable register circuit of silicon is defined as finding yield y (T),

Y (T)=Prob (T≤T₀), (14)

Wherein, Prob represents probability function.

Obtaining statistics minimum clock cyclePolynomial chaos expression formula after,Cumulative probability function can also be computed. After band, the yield of the adjustable register circuit of silicon just can basisCumulative probability function calculate out.

By above step, the present invention can obtain the final result of the adjustable register circuit statistical timing analysis of silicon after band. The present invention has the advantage that for the adjustable register circuit statistical timing analysis method of silicon after band

1. the method that the present invention applies random arrangement first after band in the adjustable register circuit statistical timing analysis of silicon, by using sparse grid technology to reduce the collocation point number of multidimensional integral, it is to avoid relevant with dimension size be exponentially increased assess the cost.

2. this method is comparatively efficient, it is possible to is obtaining and under the comparable precise manner of existing method, is substantially reducing program runtime, can be used for solving the statistical timing analysis problem of the adjustable register circuit of silicon after extensive band.

Accompanying drawing explanation

Fig. 1 is the inventive method flow chart;

Fig. 2 is a typical rear adjustable register architecture schematic diagram of silicon;

Fig. 3 (a) is first embodiment of the invention sequence circuit schematic diagram;

Fig. 3 (b) is first embodiment of the invention temporal constraint figure schematic diagram;

Fig. 3 (c) is first embodiment of the invention cum rights constraints graph schematic diagram;

Fig. 3 (d) calculates schematic diagram for the corresponding δ of first embodiment of the invention.

Detailed description of the invention

Understandable for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from, further illustrate the present invention below by specific embodiments and the drawings.It needs to be noted, specific embodiments and the drawings are merely to explanation, the present invention according to illustrating herein, can be made various amendment and change by obvious those of ordinary skill in the art within the scope of the present invention, and these are revised and change and also include in the scope of the invention. It addition, the present invention refer to open source literature, these documents are to more clearly describe the present invention, and their entire contents is all incorporated herein carrying out reference, are equivalent to their full text repeated description mistake in this article.

Embodiment 1 is used for the inventive method key step is described.

The present invention realizes step as shown in Figure 1 for the adjustable register circuit statistical timing analysis method of silicon after band.

Fig. 3 (a) is a sequence circuit example with logical path time delay. Fig. 3 (b) is its corresponding temporal constraint. A depositor in each summit representative graph 3 (a) in Fig. 3 (b). In Fig. 3 (a), each logical path is corresponding in Fig. 3 (b) two temporal constraint limits. Such as, from FF in Fig. 3 (a)₁To FF₂Logical path time delay be 3. From FF₁To FF₂Maximum delay and minimum time delay are all 3. So, Fig. 3 (b) should increase by two corresponding temporal constraint limits. Limit (1,2) corresponding to setup time constraint is:

t_i-t_j≤T-3。

Limit (1,2) was constrained to corresponding to the retention time:

t_i-t_j≤3。

This circuit statistical timing analysis process is as follows:

The compression of step 1. pivot obtains N number of independent random variable.

Step 2. generates sparse grid collocation point.

Collocation point is:

${\mathrm{\&Theta;}}_d^l={\&cup;}_{l+1\&le;\left|\stackrel{\&RightArrow;}{l}\right|\&le;d+l}{\mathrm{\&Theta;}}_1^{i_1}\&times;...\&times;{\mathrm{\&Theta;}}_l^{i_d},$

Wherein, $\left|\stackrel{\&RightArrow;}{l}\right|=i_1+...+i_d.$ Respective weights is:

$w_{j_{i_1,...,j_{i_d}}={(-1)}^{d+l-\left|\stackrel{\&RightArrow;}{l}\right|}\left(\begin{array}{c}d-1\\ d+l-\left|\stackrel{\&RightArrow;}{l}\right|\end{array}\right)({\stackrel{\&RightArrow;}{\mathrm{\&Theta;}}}_{j_{i_1}}^{i_1}...{\stackrel{\&RightArrow;}{\mathrm{\&Theta;}}}_{j_{i_d}}^{i_d}).}^{i_1,...,i_d}$

Step 3. calculates the minimum clock cycle of each collocation point, and step is as follows:

Step 3.1: build cum rights constraints graph, comprise circuit logic and circuit clock tree simultaneously. Fig. 3 (c) show cum rights constraints graph, comprises Fig. 3 (a) circuit and a clock trees simultaneously. Solid line represents that logical path, dotted line represent clock trees limit.

Step 3.2: calculate the corresponding δ of each edge. The corresponding δ of constraints graph shown in Fig. 3 (c) is shown in Fig. 3 (d).

Step 3.3: application Howard Algorithm for Solving minimum ring ratio problem. Solve minimum ring ratio problem and obtain optimal value λ *.

Step 3.4: calculate minimum clock cycle. After having solved above-mentioned minimum ring ratio problem, we can obtain the maximum of λ, is designated as λ *. Then minimum clock cycle is T_min=T_init-λ*。

Step 4. calculates minimum clock cycle generalized polynomial chaos expansion coefficient.

$t_{i_1,...,i_N}={\mathrm{\&Sigma;}}_{k=1}^P{w}_k{T}_{\min }\left({\stackrel{\&RightArrow;}{\mathrm{\&xi;}}}_k\right)H_N^{i_1,...,i_N}\left({\stackrel{\&RightArrow;}{\mathrm{\&xi;}}}_k\right),$

Wherein,It is kth collocation point,It it is collocation pointPlace's minimum clock cycle, this value calculates in step 3 and obtains.

Step 5. calculates the yield of the adjustable register circuit of silicon after being with.

After band, the statistical timing analysis of the adjustable register circuit of silicon is defined as finding yield y (T),

Y (T)=Prob (T≤t₀),

Wherein, Prob represents probability function.

Embodiment 2 is used for showing that the statistical timing analysis method that the present invention proposes obtaining and while the comparable precision of existing method, can significantly reduce program runtime.

In the present embodiment, the setting similar with document [17] is adopted. By the monte carlo method acquired results of 10000 sampled points standard of comparison as judgment accuracy. Test circuit is from ISCAS89, and the elementary cell door in test circuit is mapped to SMIC's 65nm cell library. In the present embodiment, each depositor have one after the adjustable depositor of silicon, each depositor range of accommodation is set to 0.3 times of circuit longest path time delay. In monte carlo method and the inventive method, 6 stochastic variables (transistor length, transistor width, the threshold voltage of NMOSFET and PMOSFET) are used technological fluctuation is modeled.The standard deviation of these independent random variables is set to the 10% of nominal value. In this example, use secondary delay model, and obtain logical path secondary delay expression formula [23] by the SSTA method based on random arrangement point. In this SSTA engine, definitiveness STA engine is used to derive the time delay of each collocation point logical path. Finally, theoretical according to random arrangement, derive secondary delay expression formula. Test case and result are as shown in table 1. #Nodes and #Edges represents the number on summit and limit in temporal constraint figure. Err (μ) represents minimum clock cycle meansigma methods relative error, and Err (σ) represents minimum clock cycle standard deviation relative error. Merge represents the method in document [17]. The operation time includes random arrangement point and generates, and minimum clock cycle calculates and yield calculates.

The meansigma methods of the inventive method minimum clock cycle meansigma methods relative error is 0.16%, hence it is evident that less than the method in document [17]. The meansigma methods of the inventive method minimum clock cycle standard deviation relative error is 0.48%, slightly above the method in document [17], but remains sufficiently accurate. Therefore, the accuracy of the inventive method can be comparable with the method in document [17].

It will be seen that for small scale in circuitry from form 1, the inventive method runs time and document [17] quite or longer. But, the speed-up ratio more than 10 times can be obtained for large-scale circuit the inventive method. Method in document [17] is highly dependent on circuit structure, for instance, test circuit s1423 scale is much smaller than s13207, but the operation time of s1423 is but longer than s13207. The scale of S15850 is about 4 times of s13207, but the operation time of S15850 is but 36 times of s13207. Comparing, the quantity on the inventive method and temporal constraint limit is linear approximate relationship. The operation time of the inventive method is predictable, and and circuit structure relatedness more weak, this is very good characteristic in actual applications.

Table 1 the inventive method and existing method comparative result

Claims (5)

1. one kind for after the statistical timing analysis method of the adjustable register circuit of silicon, it is characterised in that: comprise the steps:

The compression of step 1. pivot obtains N number of independent random variable;

Step 2. generates sparse grid collocation point;

Step 3. calculates the minimum clock cycle of each collocation point;

Step 4. calculates minimum clock cycle generalized polynomial chaos expansion coefficient;

Step 5. calculates the yield of the adjustable register circuit of silicon after being with.

2. as claimed in claim 1 for after the statistical timing analysis method of the adjustable register circuit of silicon, it is characterised in that step 2 generates sparse grid collocation point, comprises following two sub-steps:

Step 2.1: calculate multidimensional collocation point;

Step 2.2: calculate the corresponding weight of multidimensional collocation point.

3. as claimed in claim 1 for after the statistical timing analysis method of the adjustable register circuit of silicon, it is characterised in that step 3 calculates the minimum clock cycle of each collocation point, comprises following 4 sub-steps:

Step 3.1: building cum rights constraints graph, comprise circuit logic and circuit clock tree simultaneously, wherein the definition of each edge is as follows:

${\mathrm{\&omega;}}_{\mathrm{ij}}=\left\{\begin{array}{cc}{T}_{\mathrm{init}}-D_{\mathrm{ij}},& \&ForAll;(i,j)\&Element;E_s,\\ d_{\mathrm{ij}},& \&ForAll;(j,i)\&Element;E_h,\\ R_{\mathrm{ij}},& \&ForAll;(i,j)\&Element;E_{\mathrm{pst}},\\ 0,& \&ForAll;(i,j)\&Element;E_t.\end{array}\right.$

Step 3.2: calculate the corresponding δ of each edge,

${\mathrm{\&delta;}}_{\mathrm{ij}}=\left\{\begin{array}{cc}1,& \&ForAll;(i,j)\&Element;E_s,\\ 0,& \&ForAll;(j,i)\&Element;E_h,\\ 0,& \&ForAll;(i,j)\&Element;E_{\mathrm{pst}},\\ 0,& \&ForAll;(i,j)\&Element;E_t.\end{array}\right.$

Step 3.3: application Howard Algorithm for Solving minimum ring ratio problem.

Step 3.4: calculate minimum clock cycle.

4. as claimed in claim 1 for after the statistical timing analysis method of the adjustable register circuit of silicon, it is characterised in that step 4 calculates minimum clock cycle generalized polynomial chaos expansion coefficient, is calculated by following formula and obtain:

$t_{i_1,...,i_N}={\mathrm{\&Sigma;}}_{k=1}^p{w}_k{T}_{\min }\left({\stackrel{\&RightArrow;}{\mathrm{\&xi;}}}_k\right)H_N^{i_1,...,i_N}\left({\stackrel{\&RightArrow;}{\mathrm{\&xi;}}}_k\right),$

Wherein,It is kth collocation point,It it is collocation pointPlace's minimum clock cycle,Represent that N ties up generalized polynomial chaos.

5. as claimed in claim 1 for after the statistical timing analysis method of the adjustable register circuit of silicon, it is characterised in that after calculating band in step 5, the yield process of the adjustable register circuit of silicon is: obtaining statistics minimum clock cyclePolynomial chaos expression formula after,Cumulative probability function be computed, after band the yield of the adjustable register circuit of silicon according toCumulative probability function calculate obtain.