CN105677580B - The method and apparatus of access cache - Google Patents
The method and apparatus of access cache Download PDFInfo
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- CN105677580B CN105677580B CN201511024173.8A CN201511024173A CN105677580B CN 105677580 B CN105677580 B CN 105677580B CN 201511024173 A CN201511024173 A CN 201511024173A CN 105677580 B CN105677580 B CN 105677580B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
Abstract
A kind of method of access cache, comprising: receive the data access request of application program, application program is run in the target core of CPU, and CPU is the CPU for including multicore, and target core is one of multicore, and data access request includes the memory address of target data to be visited；According to data access request, inquiring in the shared caching of multicore whether there is target data, wherein, caching includes the corresponding exclusive address space of target core, exclusive address space is for storing the data that target core is read from memory, and the data that other cores in addition to target core in multicore are read cannot replace the data that target core is stored in exclusive address space；When being stored with target data in caching, target data is read from caching；When not stored target data in caching, according to memory address, target data is read from memory, and target data is stored among exclusive address space.To reduce use competition when multi-core CPU access cache.
Description
Technical field
The present invention relates to the method and apparatus of access cache in computer field more particularly to computer field.
Background technique
In modem computer systems, central processing unit (CPU, Central Processing Unit) passes through bus
With Memory linkage, CPU is limited when accessing internal storage data by Bus Speed, and there are performance bottlenecks.So CPU passes through caching
(cache) efficiency for obtaining data is improved.Cache the data frequently used for saving CPU.The number in memory is accessed as CPU
According to when, whether have data and data whether expired in query caching first, read number from caching if data are not out of date
According to.Otherwise CPU from reading data in memory and is flushed in caching；It can program part to the access of memory when due to program operation
Property feature, i.e., a period of time in may have multiple read-write to identical data, so using processor can be greatly speeded up after caching
Access the speed of data.
For multi-core computer system, current existing level cache, L2 cache and three-level caching.Wherein three-level is slow
It deposits and is shared by all cores on a physical cpu, so there may be use competition when multiple cores access three-level caching simultaneously
The case where.For example, in 64 core systems, when each core access stores the data in three-level caching will with other 63 cores into
Row competition.When application program is run on some core, the data of access can be put into three-level caching by CPU.If this is counted
According to access frequency it is average on 64 cores it is not high, it is possible to replaced by the data that other cores access.Program accesses again
The case where this data needs CPU to read from memory again, data is caused to be read repeatedly.With being continuously increased for CPU core number,
Cache conflict or competition probability between each core are also continuously increased.
Summary of the invention
The present invention provides a kind of method and apparatus of access cache, with when reducing multi-core CPU access cache using competing
It strives.
In a first aspect, the present invention provides a kind of method of access cache, this method comprises: receiving the data of application program
Access request, the application program are run in the target core of central processing unit CPU, which is the CPU for including multicore, the mesh
Marking core is one of the multicore, which includes the memory address of target data to be visited；According to the data access
Request is inquired in the shared caching of the multicore with the presence or absence of the target data, wherein the caching includes that the target core is corresponding solely
Address space is accounted for, the exclusive address space is for storing the data that the target core is read from memory, and removing in the multicore should
The data that other cores except target core are read cannot replace the data that the target core is stored in the exclusive address space；When this is slow
When being stored with the target data in depositing, the target data is read from the caching；When not stored target data in the caching,
According to the memory address, the target data is read from the memory, and the target data is stored among the exclusive address space.
In the present invention, when the data access request of the target core processing application program in CPU, in the caching that multicore is shared
Middle to there is exclusive address space, exclusive address space is for storing the data that target core is read from memory, and removing in multicore
The data that other cores except target core are read cannot replace the data that target core is stored in exclusive address space, to support
In the exclusive use of the exclusive address space of target core in the buffer, reduce use competition when multi-core CPU access cache.
With reference to first aspect, in the first possible implementation of the first aspect, this method further include: receive this and answer
With the instruction information of program, which is used to indicate is arranged the exclusive address space, the instruction packet in the caching
Address and size of the address space in the caching are monopolized containing this；According to the instruction information, this is set in the caching exclusively
Location space.
The possible implementation of with reference to first aspect the first, in second of possible implementation of first aspect
In, the multicore and multiple registers correspond, and according to the instruction information the exclusive address space is arranged, comprising: according to this in this
It indicates information, the exclusive corresponding buffer address of address space and buffer storage length is arranged by the corresponding register of target core.
With reference to first aspect, the first or second of possible implementation of first aspect, in the third of first aspect
In the possible implementation of kind, which includes resident address space, which is used to store the mesh
The first data in data are marked, and first data being located in the resident address space cannot be replaced by any data.
Resident address space is set by setting in exclusive address space, and is arranged and is located at the first of resident address space
Data cannot be replaced by any data, to lock the first data in the buffer, and then be improved slow when reading the first data
The hit rate deposited.
With reference to first aspect, any possible reality of the first of first aspect into the third possible implementation
Existing mode, in a fourth possible implementation of the first aspect in, which is that three-level caches.
Second aspect, the present invention provides a kind of devices of access cache, comprising: receiving module applies journey for receiving
The data access request of sequence, the application program are run in the target core of central processing unit CPU, the CPU be include multicore
CPU, the target core are one of the multicore, which includes the memory address of target data to be visited；Inquire mould
Block, for according to the data access request, inquiring in the shared caching of the multicore with the presence or absence of the target data, wherein this is slow
Bag deposit includes the corresponding exclusive address space of the target core, and the exclusive address space is for storing what the target core was read from memory
Data, and the data of other cores reading in addition to the target core in the multicore cannot replace the target core and be stored in this exclusively
Data in the space of location；Execution module, for reading the target from the caching when being stored with the target data in the caching
Data；The execution module is also used to when not stored target data in the caching, according to the memory address, is read from the memory
The target data is taken, and the target data is stored among the exclusive address space.
In conjunction with second aspect, in the first possible implementation of the second aspect, which is also used to receive
The instruction information of application program, which is used to indicate is arranged the exclusive address space, the instruction information in the caching
Address and size of the address space in the caching are monopolized comprising this；Wherein the execution module is also used to according to the instruction information,
The exclusive address space is set in the caching.
In conjunction with the first possible implementation of second aspect, in second of possible implementation of second aspect
In, the multicore and multiple registers correspond, which is specifically used for being checked according to the instruction information by the target
The exclusive corresponding buffer address of address space and buffer storage length is arranged in the register answered.
In conjunction with second aspect, the first or second of possible implementation of second aspect, in the third of second aspect
In the possible implementation of kind, which includes resident address space, which is used to store the mesh
The first data in data are marked, and first data being located in the resident address space cannot be replaced by any data.
In conjunction with second aspect, any possible reality of the first of second aspect into the third possible implementation
Existing mode, in the fourth possible implementation of the second aspect, the caching are three-level caching.
The third aspect, the present invention provides a kind of methods of access cache, receive the data access request of application program, should
Application program is run in the target core of central processing unit CPU, which is the CPU for including multicore, which is the multicore
One of, which includes the memory address of target data to be visited；According to the data access request, it is more to inquire this
It whether there is the target data in the shared caching of core, wherein the caching includes the corresponding resident address space of the target core, should
Resident address space is for storing the data that the target core is read from memory, and the target being located in the resident address space
Data cannot be replaced by any data；When being stored with the target data in the caching, the target data is read from the caching；
When not stored target data in the caching, according to the memory address, the target data is read from the memory, and by the mesh
Mark data are stored among the caching.
In the present invention, it when the target core in CPU handles the data access request of the application program, is shared in multicore slow
The resident address space of middle presence is deposited, resident address space is stored in and stays for storing the data that target core is read from memory
Stay the target data in address space that cannot be replaced by any data, to support empty in the resident address of target core in the buffer
Between exclusive use, use competition when reducing multi-core CPU access cache.
In conjunction with the third aspect, in the first possible implementation of the third aspect, journey is applied this method comprises: receiving
The instruction information of sequence, which is used to indicate is arranged the resident address space in the caching, which includes should
Resident address and size of the address space in the caching；According to the instruction information, it is empty which is set in the caching
Between.
Fourth aspect, the present invention provides a kind of device of access cache, which includes processor and memory；This is deposited
Reservoir is used for store code；Code that the processor is stored by reading the memory, to be provided for executing first aspect
Method.
Detailed description of the invention
In order to illustrate the technical solution of the embodiments of the present invention more clearly, will make below to required in the embodiment of the present invention
Attached drawing is briefly described, it should be apparent that, drawings described below is only some embodiments of the present invention, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing.
Fig. 1 is the flow diagram of the method for access cache according to an embodiment of the present invention.
Fig. 2 is the multi-core computer system architecture diagram of another embodiment according to the present invention.
Fig. 3 is the architecture diagram of the method for access cache according to yet another embodiment of the invention.
Fig. 4 is the schematic diagram of the device of access cache according to another embodiment of the present invention.
Fig. 5 is the schematic diagram of the device of access cache according to another embodiment of the present invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiment is a part of the embodiments of the present invention, rather than whole embodiments.Based on this hair
Embodiment in bright, those of ordinary skill in the art's every other reality obtained without making creative work
Example is applied, all should belong to the scope of protection of the invention.
It should be understood that the method for the access cache in the embodiment of the present invention can be applied to multi-core computer system, the multicore
Computer system can be general multi-core computer system.CPU in the multi-core computer system may include multiple cores, more
It can be communicated by system bus or corsspoint switch matrix between a core, may include in CPU in the multi-core computer system
The shared caching of multicore.
Fig. 1 shows the schematic diagram of the method 100 of one of embodiment of the present invention access cache.As shown in Figure 1, the party
Method 100 includes:
S110 receives the data access request of application program, which runs on the target of central processing unit CPU
In core, which is the CPU for including multicore, which is one of the multicore, which includes target to be visited
The memory address of data；
S120 is inquired in the shared caching of the multicore according to the data access request with the presence or absence of the number of targets
According to, wherein the caching includes the corresponding exclusive address space of the target core, and the exclusive address space is described for storing
The data that target core is read from memory, and the data that other cores in addition to the target core in the multicore are read cannot
Replace the data that the target core is stored in the exclusive address space；
S130 reads the target data when being stored with the target data in the caching from the caching；
S140, according to the memory address, reads the target when not stored target data in the caching from the memory
Data, and the target data is stored among the exclusive address space.
In embodiments of the present invention, shared in multicore when the data access request of the target core processing application program in CPU
Caching in there is exclusive address space, exclusive address space is for storing the data that target core is read from memory, and multicore
In the data that read of other cores in addition to target core cannot replace the data that target core is stored in exclusive address space, from
And support the exclusive use of the exclusive address space in target core in the buffer, reduce use when multi-core CPU access cache
Competition.
It should be understood that the present invention implement in, due to multicore share caching in be provided with it is corresponding with target core exclusively
Location space, so that the target data that target core is read will not be substituted by other data in addition to target core, so improving slow
The hit rate deposited.
It should be understood that the memory address of the target data in the embodiment of the present invention, can refer to the virtual address of target data,
It can refer to the physical address of target data, the present invention does not limit this.
It should be understood that the caching that the multicore in the embodiment of the present invention is shared, can be three-level caching (i.e. L3 cache), or
It is other cachings that can be shared by multicore, the present invention is not limited thereto.For example, all cores on the same physical cpu can be with
Shared three-level caching, each core can be used alone corresponding level cache or L2 cache.
It is alternatively possible to address and the size of the exclusive address space be arranged by software systems, for example, behaviour can be passed through
Make system setting, or the exclusive address space can also be set by application program.For example, can receive software systems (behaviour
Make system or application program) the instruction information that issues, which is used to indicate address and the size of exclusive address space, can
The exclusive address space according to the instruction information, to be arranged in the buffer.
Optionally, the data that other cores are read in addition to target core can be stored in exclusive address space, but it is other
The data that core is read cannot replace the data of target core reading, can only use the number not read by target core in exclusive address space
According to the space occupied.
Optionally, as one embodiment, the method 100 of the access cache further include: receive the instruction letter of application program
Breath, which is used to indicate is arranged the exclusive address space in the caching, which includes that the exclusive address is empty
Between address in the caching and size；According to the instruction information, which is set in the caching.
It should be understood that in embodiments of the present invention, according to instruction information, which is set in the buffer, it can be with
It is to monopolize in the corresponding register of address space address and the size of the exclusive address space are set according at this.
Optionally, it is corresponded as one embodiment, the multicore and multiple registers, in the method for the access cache
In 100, according to the instruction information the exclusive address space is arranged, comprising: according to the instruction information, check by the target in this
The exclusive corresponding buffer address of address space and buffer storage length is arranged in the register answered.
In order to make it easy to understand, Fig. 2 shows the inner bay composition of the multi-core computer system of the embodiment of the present invention, such as Fig. 2
It is shown, it may include multiple cores inside CPU, multiple cores can share a caching.For example, the shared caching can be located at
On hardware chip where CPU.Multiple cores in CPU can be corresponded with multiple registers, and each register can be deposited
Store up the instruction of corresponding core.The relevant information of exclusive address space can be arranged in core in CPU by register.
For example, the configuration information for the exclusive address space that can be arranged in a register in the shared caching of the multicore.Example
Such as, register may include the buffer address flag bit of exclusive address space, monopolize the buffer storage length flag bit of address space with
And the enabler flags position of exclusive address space.Wherein buffer address flag bit can be used for being arranged the address of exclusive address space,
Buffer storage length flag bit can be used for being arranged the length of exclusive address space, and it is empty that enabler flags position can be used for being arranged exclusive address
Between it is effectively or invalid.For example, the enabler flags position can be named as exclusive (exclusive) flag bit.For example, the multicore
Shared caching can be three-level caching, when the program is started, can be by (abbreviation on the in CPU the 0th core of programmatic binding
" CPU0 core "), while the exclusive address space that can be arranged on the corresponding register of CPU0 core in three-level caching, it will
Exclusive are assigned a value of 1, and it is the currently active to represent exclusive address space；Buffer address flag bit is assigned a value of 0x10000, is delayed
It deposits length mark position and is assigned a value of 0x10000, indicate that CPU0 core monopolizes the spatial cache that address field is 0x10000 to 0x1ffff.?
In the exclusive address space corresponding enabler flags position effective period, address is 0x10000 to the three-level between 0x1ffff
The data of spatial cache storage are arranged to be replaced by the data that other cores in addition to target core are read from memory.
In order to make it easy to understand, Fig. 3 shows the architecture diagram of the method for the access cache of the embodiment of the present invention, as shown in figure 3,
Software systems (for example, operating system or application program) can be carried out by cached configuration interface to register and exclusive address
The setting of space correlation.Wherein cached configuration interface can be the interface of software systems access register.
Optionally, it after the enabler flags position that exclusive address space is arranged by register is effective, can notify except described
The address of other cores except target core exclusive address space, notifies the exclusive corresponding address range of address space in currently quilt
Target core is exclusive.When carrying out data cached update, target core can be preferentially using exclusive address space.For example, can pass through
System bus monitoring protocols are by the address broadcast of exclusive address space to other cores in addition to target core.
Optionally, as one embodiment, the method 100 of the access cache further include: the exclusive address space includes staying
Address space is stayed, which is used to store the first data in the target data, and is located at the resident address space
In data cannot be replaced by any data.
In the embodiment of the present invention, resident address space is arranged in exclusive address space by setting, and be arranged to be located at and stay
Staying the first data of address space cannot be replaced by any data, to lock the first data in the buffer, and then improve
The hit rate cached when reading the first data.
It should be understood that the first data in the embodiment of the present invention, can refer to the partial data or total data in target data.
For example, first data can be the critical data in target data, which can be stored in resident address space it
In, in the resident address space valid period, which will not be replaced during application program is run by any data, or
Person, it can be understood as, the critical data is locked, will not be swapped out by subsequent.
Optionally, which can be determined by application program, can also be determined by operating system, for example, can connect
The first information that application program or operating system are sent is received, which can serve to indicate that the first data and resident address
Resident address space can be arranged according to the first information in space address in the buffer and size in exclusive address space,
And the first data are stored in using the resident address space.
It should be understood that the resident address space can be stored in the data that other cores are read in addition to target core, can also be stored in
Data in target data in addition to first data, still, any data in the resident address space cannot be replaced
First data are changed, in other words, first data will not be replaced after being stored in the resident address space.
It should be understood that the resident address space in the embodiment of the present invention, can be arranged before accessing the first data, it can also be with
It is arranged when accessing the first data, this is not limited by the present invention.
For example, the long scale of the address mark position of resident address space, resident address space can be arranged in a register
Will position and the enabler flags position of resident address space.By the way that above each flag bit is arranged, the ground of resident address space is set
Location, size and whether effectively.For example, can name the enabler flags position of the resident address space is non-replaced (noswap)
When resident address space being arranged in the corresponding register of target core, the buffer address of the resident address space is can be set in position
And buffer storage length, and by the position noswap be effectively (for example, set 1 be it is effective, it is invalid for setting 0).
Optionally, when application program does not use first data, the resident address space can be cancelled, for target
Other data that core is read use.For example, after determination does not use the first data, it can be in the corresponding register of target core
In, it sets the enabler flags position for storing the resident address space of first data in vain, is then stored in and stays after invalid
The other data replacement for staying the data of address space that can be read by target core.
In the embodiment of the present invention, when application program, which does not need resident address space, stores the first data, stayed by cancelling
Address space is stayed, resident address space the space occupied is reverted to and is used by the data that target core is read, is improved exclusively
The utilization rate of location space and caching.
It should be understood that a resident address space can be set, multiple resident addresses also can be set in the embodiment of the present invention
Space.
Optionally, as one embodiment, the method 100 of the access cache further include: determine that the target core does not need to make
Address space is monopolized with this；Cancel the exclusive address space, in order to which other cores in addition to the target core use this exclusively
Location space.
In the embodiment of the present invention, the exclusive address space not used by cancelling target core accounts for exclusive address space
Space reverts to multicore and shares, and improves the utilization rate of caching.
For example, in embodiments of the present invention, it includes: to use which, which does not need the case where monopolizing address space using this,
The application program operation of the exclusive address space finishes, which no longer needs the caching shared using the multicore.
For example, cancelling the concrete operations of the exclusive address space, it can be and be arranged solely in the corresponding register of target core
Address in the buffer and the length of address space are accounted for, and sets invalid for the enabler flags position for monopolizing address space.Example
Such as, when application program is using exclusive address space, the address provided with exclusive address space is 0x10000, and is provided with only
The length for accounting for address space is 0x10000, and the enabler flags position assignment of exclusive address space is effective.Indicate address field in caching
0x10000 is monopolized to the space between 0x1ffff by target core.When target core is not needed using exclusive address space (for example,
The application program run in target core terminates), the address that exclusive address space can be arranged in a register is 0x10000,
The length that exclusive address space is arranged is 0x10000, and sets invalid for the enabler flags position of address space.It indicates in caching
The space of address field 0x10000 to 0x1ffff is no longer monopolized by target core, and the shared state of multicore can be reverted to, in other words,
The more new strategy of caching is reverted to the more new strategy of default.To determine that cancellation is exclusive when not needing exclusive address space
The space of exclusive address space hold is reverted to multicore and shared, improves the utilization rate of caching by address space.
A kind of method 100 of access cache is illustrated above in association with Fig. 1 to Fig. 3, a kind of visit is discussed in detail below
Ask that the method 200 of caching, this method 200 include:
S210 receives the data access request of application program, which runs on the target of central processing unit CPU
In core, which is the CPU for including multicore, which is one of the multicore, which includes target to be visited
The memory address of data；
S220, according to the data access request, inquiring in the shared caching of the multicore whether there is the target data,
In, which includes the corresponding resident address space of the target core, and the resident address space is for storing the target core from memory
The data of middle reading, and the target data being located in the resident address space cannot be replaced by any data；
S230 reads the target data when being stored with the target data in the caching from the caching；
S240, according to the memory address, reads the target when not stored target data in the caching from the memory
Data, and the target data is stored among the caching.
In the present invention, it when the target core in CPU handles the data access request of the application program, is shared in multicore slow
The resident address space of middle presence is deposited, resident address space is stored in and stays for storing the data that target core is read from memory
Stay the target data in address space that cannot be replaced by any data, to support empty in the resident address of target core in the buffer
Between exclusive use, use competition when reducing multi-core CPU access cache.
Optionally, as one embodiment, this method 200 includes: to receive the instruction information of application program, the instruction information
It is used to indicate and the resident address space is set in the caching, which includes the resident address space in the caching
Address and size；According to the instruction information, which is set in the caching.
The method of access cache is illustrated above in association with Fig. 1 to Fig. 3, is described in detail and visits below in conjunction with Fig. 4 to Fig. 5
Ask the device of caching.
Fig. 4 shows the schematic diagram of the device 400 of access cache according to an embodiment of the present invention.It should be understood that the present invention is real
The following of the modules in the device 400 of example and other operation and/or functions are applied respectively to realize that Fig. 1 is each into Fig. 3
The corresponding process of a method, for sake of simplicity, details are not described herein, as shown in figure 4, the device 400 includes:
Receiving module 410, for receiving the data access request of application program, which runs on central processing list
In the target core of first CPU, which is the CPU for including multicore, which is one of the multicore, which includes
The memory address of target data to be visited；
Enquiry module 420, for according to the data access request, inquiring in the shared caching of the multicore with the presence or absence of the mesh
Mark data, wherein the caching includes the corresponding exclusive address space of the target core, and the exclusive address space is for storing the target
The data that core is read from memory, and the data that other cores in addition to the target core in the multicore are read cannot replace the mesh
Mark core is stored in the data in the exclusive address space；
Execution module 430, for reading the number of targets from the caching when being stored with the target data in the caching
According to；
The execution module 430 is also used to when not stored target data in the caching, interior from this according to the memory address
Middle reading target data is deposited, and the target data is stored among the exclusive address space.
Optionally, as one embodiment, which is also used to receive the instruction information of the application program, should
Instruction information is used to indicate is arranged the exclusive address space in the caching, which includes the exclusive address space at this
Address and size in caching；Wherein the execution module 430 is also used to that it is exclusive that this is arranged in the caching according to the instruction information
Address space.
Optionally, it is corresponded as one embodiment, the multicore and multiple registers, which specifically uses
According to the instruction information, it is gentle which is arranged by the corresponding register of target core
Deposit length.
Optionally, as one embodiment, which includes resident address space, which uses
The first data in the storage target data, and first data being located in the resident address space cannot be by any data
Replacement.
Optionally, as one embodiment, which is three-level caching.
In embodiments of the present invention, shared in multicore when the data access request of the target core processing application program in CPU
Caching in there is exclusive address space, exclusive address space is for storing the data that target core is read from memory, and multicore
In the data that read of other cores in addition to target core cannot replace the data that target core is stored in exclusive address space, from
And support the exclusive use of the exclusive address space in target core in the buffer, reduce use when multi-core CPU access cache
Competition.
Fig. 5 shows the schematic diagram of the device of access cache according to an embodiment of the present invention.As shown in figure 5, the device 500
It include: processor 510, memory 520, bus system 530, wherein the processor 500 and the memory 520 pass through total linear system
System 530 is connected, and for storing instruction, which is used to execute the instruction of the memory 520 storage to the memory 520.
Wherein, which is used for: receiving the data access request of application program, which runs on center
In the target core of processing unit CPU, which is the CPU for including multicore, which is one of the multicore, which asks
Seek the memory address comprising target data to be visited；According to the data access request, inquiring in the shared caching of the multicore is
No there are the target datas, wherein the caching includes the corresponding exclusive address space of the target core, which is used for
The data that the target core is read from memory are stored, and the data that other cores in addition to the target core in the multicore are read are not
The data that the target core is stored in the exclusive address space can be replaced；It is slow from this when being stored with the target data in the caching
Deposit middle reading target data；When not stored target data in the caching, according to the memory address, read from the memory
The target data, and the target data is stored among the exclusive address space.
In embodiments of the present invention, shared in multicore when the data access request of the target core processing application program in CPU
Caching in there is exclusive address space, exclusive address space is for storing the data that target core is read from memory, and multicore
In the data that read of other cores in addition to target core cannot replace the data that target core is stored in exclusive address space, from
And support the exclusive use of the exclusive address space in target core in the buffer, reduce use when multi-core CPU access cache
Competition.
Optionally, as one embodiment, which is also used to receive the instruction information of the application program, this refers to
Show that information is used to indicate and the exclusive address space is set in the caching, which includes that the exclusive address space is slow at this
Address and size in depositing；According to the instruction information, which is set in the caching.
Optionally, it is corresponded as one embodiment, the multicore and multiple registers, which is specifically used for
According to the instruction information, the exclusive corresponding buffer address of address space and caching are arranged by the corresponding register of target core
Length.
Optionally, as one embodiment, which includes resident address space, which uses
The first data in the storage target data, and first data being located in the resident address space cannot be by any data
Replacement.
Optionally, as one embodiment, which is three-level caching.
In addition, the terms " system " and " network " are often used interchangeably herein.The terms " and/
Or ", only a kind of incidence relation for describing affiliated partner, indicates may exist three kinds of relationships, for example, A and/or B, it can be with table
Show: individualism A exists simultaneously A and B, these three situations of individualism B.In addition, character "/" herein, typicallys represent front and back
Affiliated partner is a kind of relationship of "or".
It should be understood that in embodiments of the present invention, " B corresponding with A " indicates that B is associated with A, B can be determined according to A.But
It should also be understood that determining that B is not meant to determine B only according to A according to A, B can also be determined according to A and/or other information.
Those of ordinary skill in the art may be aware that list described in conjunction with the examples disclosed in the embodiments of the present disclosure
Member and algorithm steps, can be realized with electronic hardware, computer software, or a combination of the two, in order to clearly demonstrate hardware
With the interchangeability of software, each exemplary composition and step are generally described according to function in the above description.This
A little functions are implemented in hardware or software actually, the specific application and design constraint depending on technical solution.Specially
Industry technical staff can use different methods to achieve the described function each specific application, but this realization is not
It is considered as beyond the scope of this invention.
It is apparent to those skilled in the art that for convenience of description and succinctly, foregoing description is
The specific work process of system, device and unit, can refer to corresponding processes in the foregoing method embodiment, details are not described herein.
In several embodiments provided herein, it should be understood that disclosed systems, devices and methods, it can be with
It realizes by another way.For example, the apparatus embodiments described above are merely exemplary, for example, the unit is drawn
Point, only a kind of logical function partition, there may be another division manner in actual implementation, such as multiple units or components can
To combine or be desirably integrated into another system, or some features can be ignored or not executed.In addition, shown or discussed
Mutual coupling, direct-coupling or communication connection can be through some interfaces, the INDIRECT COUPLING of device or unit or
Communication connection is also possible to electricity, mechanical or other form connections.
Unit may or may not be physically separated as illustrated by the separation member for this, show as unit
Component may or may not be physical unit, it can it is in one place, or may be distributed over multiple nets
On network unit.Some or all of unit therein can be selected to realize the embodiment of the present invention according to the actual needs
Purpose.
It, can also be in addition, the functional units in various embodiments of the present invention may be integrated into one processing unit
It is that each unit physically exists alone, is also possible to two or more units and is integrated in one unit.It is above-mentioned integrated
Unit both can take the form of hardware realization, can also realize in the form of software functional units.
If the integrated unit is realized in the form of SFU software functional unit and when sold or used as an independent product,
It can store in a computer readable storage medium.Based on this understanding, technical solution of the present invention substantially or
Person says that all or part of the part that contributes to existing technology or the technical solution can body in the form of software products
Reveal and, which is stored in a storage medium, including some instructions are with so that a computer is set
Standby (can be personal computer, server or the network equipment etc.) execute each embodiment this method of the present invention whole or
Part steps.And storage medium above-mentioned include: USB flash disk, mobile hard disk, read-only memory (ROM, Read-Only Memory),
Random access memory (RAM, Random Access Memory), magnetic or disk etc. be various to can store program code
Medium.
Technical characteristic and description in the above a certain embodiment, in order to keep application documents succinctly clear, it is possible to understand that be applicable in
In other embodiments, no longer repeated one by one in other embodiments.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, can readily occur in various equivalent modifications or replace
It changes, these modifications or substitutions should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with right
It is required that protection scope subject to.
Claims (10)
1. a kind of method of access cache characterized by comprising
The data access request of application program is received, which runs in the target core of central processing unit CPU, should
CPU is the CPU for including multicore, which is one of the multicore, which includes target data to be visited
Memory address；
According to the data access request, inquire in the shared caching of the multicore with the presence or absence of the target data, wherein institute
Stating caching includes the corresponding exclusive address space of the target core, and the exclusive address space is for storing the target core from interior
The data of middle reading are deposited, and the data that other cores in addition to the target core in the multicore are read cannot replace the mesh
Mark core is stored in the data in the exclusive address space, and the exclusive address space is also used to store in addition to the target core
The data that other cores are read；
When being stored with the target data in the caching, the target data is read from the caching；
When the not stored target data in the caching, according to the memory address, the mesh is read from the memory
Data are marked, and the target data is stored among the exclusive address space.
2. the method as described in claim 1, which is characterized in that the method also includes:
The instruction information of the application program is received, it is described exclusively that the instruction information is used to indicate the setting in the caching
Location space, the instruction information include address and size of the exclusive address space in the caching；
According to the instruction information, the exclusive address space is set in the caching.
3. method according to claim 2, which is characterized in that the multicore and multiple registers correspond,
It is described according to the instruction information, the exclusive address space is set, comprising:
According to the instruction information, the corresponding caching of the exclusive address space is arranged by the corresponding register of the target core
Address and buffer storage length.
4. method according to any one of claims 1 to 3, which is characterized in that the exclusive address space includes resident ground
Location space, the resident address space are used to store the first data in the target data, and it is empty to be located at the resident address
Between in first data cannot be replaced by any data.
5. method according to any one of claims 1 to 3, which is characterized in that the caching is that three-level caches.
6. a kind of device of access cache characterized by comprising
Receiving module, for receiving the data access request of application program, the application program runs on central processing unit CPU
Target core in, the CPU is the CPU for including multicore, and the target core is one of described multicore, the data access request packet
Memory address containing target data to be visited；
Enquiry module, for inquiring in the shared caching of the multicore with the presence or absence of the mesh according to the data access request
Mark data, wherein the caching includes the corresponding exclusive address space of the target core, and the exclusive address space is for storing
The data that the target core is read from memory, and the data that other cores in addition to the target core in the multicore are read
The data that the target core is stored in the exclusive address space cannot be replaced, the exclusive address space is also used to store except institute
State the data that other cores except target core are read；
Execution module, for reading the number of targets from the caching when being stored with the target data in the caching
According to；
The execution module is also used to when the not stored target data in the caching, according to the memory address, from institute
It states and reads the target data in memory, and the target data is stored among the exclusive address space.
7. device as claimed in claim 6, which is characterized in that the receiving module is also used to receive the finger of the application program
Show information, the instruction information is used to indicate is arranged the exclusive address space in the caching, and the instruction information includes
Address and size of the exclusive address space in the caching；Wherein the execution module is also used to be believed according to the instruction
Breath, is arranged the exclusive address space in the caching.
8. device as claimed in claim 7, which is characterized in that the multicore and multiple registers correspond, the execution
Module is specifically used for according to the instruction information, and the exclusive address space pair is arranged by the corresponding register of the target core
The buffer address and buffer storage length answered.
9. the device as described in any one of claim 6 to 8, which is characterized in that the exclusive address space includes resident ground
Location space, the resident address space are used to store the first data in the target data, and it is empty to be located at the resident address
Between in first data cannot be replaced by any data.
10. the device as described in any one of claim 6 to 8, which is characterized in that the caching is that three-level caches.
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| CN108268384A (en) * | 2016-12-30 | 2018-07-10 | 华为技术有限公司 | Read the method and device of data |
| CN109597776B (en) * | 2017-09-30 | 2020-12-08 | 华为技术有限公司 | Data operation method, memory controller and multiprocessor system |
| CN109783403A (en) * | 2017-11-10 | 2019-05-21 | 深圳超级数据链技术有限公司 | Read the method, apparatus and data processor of data |
| CN108614782B (en) * | 2018-04-28 | 2020-05-01 | 深圳市华阳国际工程造价咨询有限公司 | Cache access method for data processing system |
| CN110765034B (en) * | 2018-07-27 | 2022-06-14 | 华为技术有限公司 | Data prefetching method and terminal equipment |
| CN109617832B (en) * | 2019-01-31 | 2022-07-08 | 新华三技术有限公司合肥分公司 | Message caching method and device |
| CN110096455B (en) * | 2019-04-26 | 2021-09-14 | 海光信息技术股份有限公司 | Exclusive initialization method of cache space and related device |
| CN112241320B (en) * | 2019-07-17 | 2023-11-10 | 华为技术有限公司 | Resource allocation method, storage device and storage system |
| CN112559433B (en) * | 2019-09-25 | 2024-01-02 | 阿里巴巴集团控股有限公司 | Multi-core interconnection bus, inter-core communication method and multi-core processor |
| CN111159062B (en) * | 2019-12-20 | 2023-07-07 | 海光信息技术股份有限公司 | Cache data scheduling method and device, CPU chip and server |
| CN111679728B (en) * | 2019-12-31 | 2021-12-24 | 泰斗微电子科技有限公司 | Data reading method and device |
| CN112527205A (en) * | 2020-12-16 | 2021-03-19 | 江苏国科微电子有限公司 | Data security protection method, device, equipment and medium |
| CN115114192A (en) * | 2021-03-23 | 2022-09-27 | 北京灵汐科技有限公司 | Memory interface, functional core, many-core system and memory data access method |
| CN114036084B (en) * | 2021-11-17 | 2022-12-06 | 海光信息技术股份有限公司 | Data access method, shared cache, chip system and electronic equipment |
| CN114721726B (en) * | 2022-06-10 | 2022-08-12 | 成都登临科技有限公司 | Method for multi-thread group to obtain instructions in parallel, processor and electronic equipment |
| CN115328820B (en) * | 2022-09-28 | 2022-12-20 | 北京微核芯科技有限公司 | Access method of multi-level cache system, data storage method and device |
| CN115827504B (en) * | 2023-01-31 | 2023-07-11 | 南京砺算科技有限公司 | Data access method for multi-core graphic processor, graphic processor and medium |
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