CN110096455B

CN110096455B - Exclusive initialization method of cache space and related device

Info

Publication number: CN110096455B
Application number: CN201910345566.0A
Authority: CN
Inventors: 钟大江; 杜朝晖; 应志伟
Original assignee: Haiguang Information Technology Co Ltd
Current assignee: Haiguang Information Technology Co Ltd
Priority date: 2019-04-26
Filing date: 2019-04-26
Publication date: 2021-09-14
Anticipated expiration: 2039-04-26
Also published as: CN110096455A

Abstract

The embodiment of the invention provides an exclusive initialization method of a cache space and a related device, wherein the exclusive initialization method of the cache space comprises the following steps: receiving an exclusive initialization request of an instruction, wherein the exclusive initialization request comprises an instruction memory address identifier of the instruction; acquiring a current exclusive cache space unit corresponding to the current address identification section of the instruction memory address identification according to the current address identification section of the instruction memory address identification; when the current exclusive cache space unit is in a non-exclusive state, performing exclusive initialization on the current exclusive cache space unit so that the current exclusive cache space unit can be exclusively occupied by the process of the instruction. The exclusive initialization method and the related device for the cache space provided by the embodiment of the invention can reduce the risk that an attacker steals sensitive data in the cache space by utilizing a side channel attack technology and even controls the execution of a program, and improve the safety of the cache space.

Description

Exclusive initialization method of cache space and related device

Technical Field

The embodiment of the invention relates to the technical field of cache security, in particular to an exclusive initialization method of a cache space and a related device.

Background

The Cache (Cache) is a buffer area for data exchange, and can help hardware to run quickly due to the fact that the running speed of the Cache is much higher than that of a memory, so that the Cache is widely applied; in order to fully coordinate the contradiction between the running speed and the cost, a multi-level cache mode is provided.

In order to save cost when using the Cache technology, the operating system and the virtual machine manager share the last level of Cache, however, in this case, despite the encryption technology, an attacker can still use the Cache side channel attack technology to attack, for example, the attacker can use information such as time consumption, power consumption or electromagnetic radiation in the running process to attack, and the Cache side channel attack has the risk that sensitive information is stolen, even the program execution is controlled.

Therefore, how to improve the security of the cache space becomes a problem that needs to be solved by those skilled in the art.

Disclosure of Invention

In view of this, embodiments of the present invention provide a method and a related device for initializing an exclusive cache space, so as to reduce a risk that an attacker steals sensitive data in the cache space by using a side channel attack technique, and even controls program execution, and improve security of the cache space.

In order to achieve the above purpose, the embodiments of the present invention provide the following technical solutions:

the embodiment of the invention provides an exclusive initialization method of a cache space, which comprises the following steps:

receiving an exclusive initialization request of an instruction, wherein the exclusive initialization request comprises an instruction memory address identifier of the instruction;

acquiring a current exclusive cache space unit corresponding to the current address identification section of the instruction memory address identification according to the current address identification section of the instruction memory address identification;

when the current exclusive cache space unit is in a non-exclusive state, performing exclusive initialization on the current exclusive cache space unit so that the current exclusive cache space unit can be exclusively occupied by the process of the instruction.

To solve the foregoing problems, an embodiment of the present invention further provides an apparatus for initializing an exclusive use of a cache space, including:

an exclusive initialization request receiving unit, adapted to receive an exclusive initialization request of an instruction, where the exclusive initialization request includes an instruction memory address identifier of the instruction;

the current exclusive cache space unit obtaining unit is suitable for obtaining a current exclusive cache space unit corresponding to the current address identification section according to the instruction memory address identification;

and the exclusive initialization unit is suitable for performing exclusive initialization on the current exclusive cache space unit when the current exclusive cache space unit is in a non-exclusive state, so that the current exclusive cache space unit can be exclusively occupied by the process of the instruction.

To solve the foregoing problems, an embodiment of the present invention further provides a central processing unit, which is adapted to execute a program for implementing the exclusive initialization method for a cache space.

In order to solve the foregoing problems, an embodiment of the present invention further provides a storage medium, where a program suitable for performing exclusive initialization of a cache space is stored in the storage medium, so as to implement the aforementioned exclusive initialization method for the cache space.

The method and the device for initializing the exclusive ownership of the cache space provided by the embodiment of the invention comprise the following steps: receiving an exclusive initialization request of an instruction, wherein the exclusive initialization request comprises an instruction memory address identifier of the instruction; acquiring a current exclusive cache space unit corresponding to the current address identification section of the instruction memory address identification according to the current address identification section of the instruction memory address identification; when the current exclusive cache space unit is in a non-exclusive state, performing exclusive initialization on the current exclusive cache space unit table entry, so that the current exclusive cache space unit can be exclusively occupied by the process to which the instruction belongs. It can be seen that, in the method for initializing an exclusive cache space provided in the embodiment of the present invention, after receiving an exclusive initialization request of a cache space of an instruction, according to a current address identifier segment of an instruction memory address identifier in the exclusive initialization request, a current exclusive cache space unit corresponding to the current address identifier segment is obtained, and the current exclusive cache space unit is in a state of not being exclusively owned, and can be exclusively owned by an instruction of an affiliated process, so that the current exclusive cache space unit is initialized exclusively, so that the current exclusive cache space unit can be exclusively owned by the affiliated process of the instruction. Therefore, the exclusive initialization method and device of the cache space provided by the invention firstly judge the state of the exclusive cache space unit by acquiring the current exclusive cache space unit, when the current exclusive cache space unit can be exclusively occupied by the process to which the instruction belongs, the current exclusive cache space unit is initialized and updated, so that preparation is provided for the exclusive update of the current exclusive cache space unit by the process, and other processes can be prevented from sharing the current exclusive cache space unit by the exclusive ownership of the current exclusive cache space unit by the process, thereby reducing the risk that an attacker steals sensitive data or even controls the execution of a program by using a side channel attack technology in the cache space, and improving the security of the cache space.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

FIG. 1 is a system architecture diagram;

FIG. 2 is a diagram illustrating a mapping relationship between memory addresses and exclusive cache space units;

FIG. 3 is a diagram of a system architecture for exclusive cache space;

fig. 4 is a flowchart illustrating an exclusive initialization method for a cache space according to an embodiment of the present invention;

fig. 5 is another flowchart illustrating an exclusive initialization method for a cache space according to an embodiment of the present invention;

fig. 6 is a flowchart illustrating a method for initializing an exclusive portion of a cache space according to an embodiment of the present invention;

fig. 7 is a further flowchart illustrating an exclusive initialization method of a cache space according to an embodiment of the present invention;

fig. 8 is an alternative block diagram of an apparatus for initializing an exclusive portion of a cache space according to an embodiment of the present invention;

FIG. 9 is an alternative block diagram of the exclusive initialization unit shown in FIG. 8;

fig. 10 is another alternative block diagram of an apparatus for initializing an exclusive portion of a cache space according to an embodiment of the present invention;

fig. 11 is a further alternative block diagram of an apparatus for initializing an exclusive portion of a cache space according to an embodiment of the present invention;

FIG. 12 is an alternative block diagram of the process of FIG. 11 exclusive to the cache space unit number fetch unit;

fig. 13 is a further alternative block diagram of an apparatus for initializing an exclusive portion of a cache space according to an embodiment of the present invention;

fig. 14 is still another alternative block diagram of an apparatus for initializing an exclusive cache space according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

As an alternative example, fig. 1 shows a system architecture diagram containing a cache space, and as shown in fig. 1, the system architecture may include: a Central Processing Unit (CPU) multi-core exclusive portion and a CPU multi-core shared portion.

The CPU multi-core exclusive part comprises an execution unit 11, a storage management unit 12 and a multi-level cache including a first-level cache 13 except a last-level cache 22; and the CPU multi-core shared portion includes the last level cache 22 and the memory 21 in the cache.

The storage management unit 12 manages the memory 21 and ensures data exchange between the memory 21 and the execution unit 11, and the cache provided between the storage management unit 12 and the memory 21 can accelerate the efficiency of data exchange, and since the cost of the cache is high, when a plurality of levels of caches are provided, the last level of cache 22 is generally set to be shared by multiple cores in order to reduce the cost.

Due to the multi-core sharing arrangement of the last-level cache 22, even under the condition that the security isolation technology is applied, an attacker still can attack the user program by using the cache side channel attack technology, steal sensitive information and even control the program execution.

The security isolation technology is that a new security instruction set is added in a central processing unit, so that a process of a user can be executed in a security enclave environment isolated from an operating system or a virtual machine manager, and when a user program runs, any other process (including the process of the operating system or the process of the virtual machine manager) trying to access a memory space of the security enclave can be prevented by the central processing unit, so that the security is improved in a mode of limiting access. However, when an attacker uses the cache side channel attack technique, the attacker can attack the user program only through information such as time consumption, power consumption or electromagnetic radiation of the last level cache without accessing a memory space.

In order to solve the above problem, an embodiment of the present invention provides an exclusive initialization method for a Cache space, where a process may initialize a Cache space unit (Cache line), that is, an exclusive Cache space unit, so that the process may obtain exclusive use of the exclusive Cache space unit, and prevent other processes from sharing the exclusive Cache space unit, thereby reducing a risk that an attacker steals sensitive data in the Cache space by using a side channel attack technology, and even controls program execution, and improving security of the Cache space.

It can be understood that the cache space is composed of a plurality of cache space units, generally, the size of one cache space unit is 64 bytes, and the memory address and the cache space unit have a corresponding correspondence relationship, so that the cache space unit can be found according to the memory address identifier.

Specifically, since the size of the cache space unit is determined by the hardware structure, in order to ensure that data in the memory address identifier segment corresponding to one cache space unit can be stored in one cache space unit, the size of one memory address identifier segment is also 64 bytes. Due to the limitation of the cache space, at different moments, the same cache space unit may correspond to a plurality of memory address identification segments, that is, after the data of one memory address identification segment is released in the cache space unit a, the data of another memory address identification segment may be stored in the cache space unit a at the next moment; of course, at the same time, the cache space unit and the memory address identifier segment are in a one-to-one correspondence relationship.

Specifically, fig. 2 provides a schematic diagram of a correspondence relationship between a memory address and an exclusive cache space unit, and the correspondence relationship between the memory address and the cache space unit can be clearly seen from the diagram.

To ensure that a cache space unit can be monopolized, an monopolizing status bit needs to be set in the cache space unit to determine the monopolizing status of the cache space unit, for convenience of description, a cache space unit with the monopolizing status bit is referred to as an monopolizing cache space unit, and the cache space units to which the method for initializing monopolizing cache spaces provided by the embodiment of the present invention can be applied are monopolizing cache space units, that is: the cache space units of the last level of shared cache space are all exclusive cache space units with exclusive status bits.

The structure of the specific exclusive cache space unit may continue to refer to fig. 2, for example: the slice 0-core 0, set 1 and 1 way of the last level cache are an exclusive cache space unit, wherein the exclusive position is an exclusive state bit of the exclusive cache space unit.

In a specific embodiment, it may be configured to identify that an exclusive cache space unit is in an exclusive state (state after exclusive update) when an exclusive state bit of the exclusive cache space unit is 1, and identify that the exclusive cache space unit is not occupied when the exclusive state bit of the exclusive cache space unit is 0, it is understood that a non-exclusive state of the exclusive cache space unit includes a state that has been exclusively initialized, but is not exclusively updated and is not exclusively initialized, and in order to clearly identify the state of the exclusive cache space unit, in a specific embodiment, the state may be identified by an exclusive cache space unit table corresponding to the exclusive cache space unit; in other embodiments, the indication may be further identified by setting an initialization status bit in the exclusive cache space unit.

For convenience of description, the embodiment of the present invention is described in a manner of using an exclusive cache space unit table:

referring to fig. 3, fig. 3 is a schematic diagram of a system architecture with exclusive cache space.

In order to timely grasp the exclusive condition of the exclusive cache space unit, in one embodiment, an exclusive cache space unit recorder 23 is established, which includes: the exclusive cache space unit table records the usage of each exclusive cache space unit, and each entry of the exclusive cache space unit table may include an exclusive cache space unit identification bit, an exclusive status bit, and a process identification bit.

In a specific embodiment, the method may be implemented by recording a number of the exclusive cache space unit in the exclusive cache space unit identification bit; the exclusive state bit of the exclusive cache space unit table is used to identify whether the exclusive cache space unit recorded in the exclusive cache space unit identification bit is in an exclusive update state, and in a specific embodiment, the exclusive cache space unit can be identified by a 2-bit binary system, 00 indicates that the exclusive cache space unit is in an exclusive initialized state, and 01 indicates that the exclusive cache space unit is in an exclusive update state; the process identification bit is used to identify whether the exclusive cache space unit recorded in the exclusive cache space unit identification bit is exclusive or not, and if the exclusive cache space unit is exclusive or not by which process, in a specific embodiment, the exclusive cache space unit is in a non-exclusive state by setting all binary bits of the process identification bit to 0, the process identification of the affiliated process by setting the process identification bit to an instruction indicates that the exclusive cache space unit is in a state allocated to the affiliated process, and the exclusive cache space unit can be determined to be either exclusive or initialized exclusively by the affiliated process in combination with the identification of the exclusive state bit.

In one embodiment, the process identifier may be a value stored in a CR3 register of the process, but in other embodiments, the process identifier of the process may be other values as long as the process can be uniquely identified.

Table 1 shows a structure of an exclusive cache space unit table entry according to an embodiment of the present invention.

Table 1 exclusive cache space unit table entries

As shown in table 1, in a specific embodiment, the process identification bit is a simplified process identification, which is because the number of bits of the process identification is generally large, which results in a large space occupied by the exclusive cache space unit table, and in order to reduce the space occupied by the exclusive cache space unit table, a process identification corresponding table may be set, so that the exclusive cache space unit recorder 23 may further include a process identification corresponding table, please refer to table 2, where table 2 is an example of a table entry structure of the process identification corresponding table, it can be seen that the process identification corresponding table may include a process identification bit for recording the process identification and a simplified process identification bit for recording the simplified process identification, as shown in table 1, the simplified process identification bit may only occupy 6 binary bits, and in a specific embodiment, when the exclusive cache space unit is not exclusive, and the 6 bits are all 0, and when the exclusive cache space unit is exclusive, the simplified process identification is recorded, so that the process identification bit in the exclusive cache space unit table only needs to record the simplified process identification, and the space occupied by the exclusive cache space unit table is reduced.

TABLE 2 Process identification mapping Table

Process identification bit	Simplified process identification bits
		Process identification	Simplifying process identification

In another embodiment, the identification bit of the exclusive cache space unit may correspond to the position of the exclusive cache space unit and the position relationship of the table entry in the table, such as: the table entries corresponding to the first exclusive cache space unit are arranged at the first position in the table, so that the length of the exclusive cache space unit table can be further reduced, and the occupied space is further reduced.

Of course, in other embodiments, the length of the exclusive cache space unit table may also be extended as needed, so as to represent richer information of a certain exclusive cache space unit.

Specifically, the calculation formula of the space occupied by the exclusive cache space unit table may be: the size of the exclusive cache space/the size of the exclusive cache space unit is the size of the space occupied by the table entry; such as: if the size of the exclusive cache space is 64MB, the size of the exclusive cache space unit is 64B, and the size of the space occupied by the table entry is 1 byte (in the case that the exclusive cache space unit identification bit is omitted), then the size of the space occupied by the exclusive cache space unit table is 64MB/64B × 1 — 1 MB.

The method comprises the steps that the utilization rate of the cache space is improved to a large extent on the basis of basically meeting the use requirements of processes for exclusive cache space units, the number of the exclusive cache space units which can be exclusively owned by the same process can also be set, and when a new request is received, whether the sum of the number of the applied exclusive cache space units and the number of the exclusive cache space units which are allocated to the same process is smaller than or equal to the number of the exclusive cache space units which can be exclusively owned by the same process or not is judged.

Specifically, the number of entries of the exclusive cache space unit table of the same process identifier may be determined by the process identifier of the process identifier bit in the exclusive cache space unit table, and further, the number of the exclusive cache space units already allocated to the process may be determined, and the number of the applied exclusive cache space units may be determined by the correspondence between the instruction memory address identifier and the cache space units.

The number of exclusive cache space units that can be exclusively owned by the same process can be configured in a dynamic configuration manner, for example: the configuration may be performed by a BIOS (Basic Input Output System), and according to the size of the cache space, options of different sizes of exclusive cache space (which may also be referred to as the number of exclusive cache space units) such as 4K, 8K, 16K, and the like are provided in the BIOS, and then the configuration is performed according to the needs of the process.

In addition to limiting the number of exclusive cache space unit tables that can be simultaneously and exclusively owned by the same process, limited by the cache space, and determining the number of processes that can simultaneously and exclusively own different exclusive cache space units, in a specific embodiment, the number of processes that simultaneously and exclusively own different exclusive cache space units may be set to be 64 at most, and in other embodiments, more or fewer processes that simultaneously are in an exclusive state (including exclusive initialization and exclusive update) may be set as needed.

In order to know how many processes have performed exclusive initialization or exclusive update on the exclusive cache space unit in the current state, the number of processes in the exclusive initialization and exclusive update states may be recorded, and when the number of processes is smaller than the set maximum value, the exclusive cache space unit may be allocated to a new process.

In the case that the process identifier mapping table is set, the process identifier mapping table may be used to implement control over the number of processes, specifically, the total number of entries in the process identifier mapping table may be set to be equal to the maximum number of processes that may be in an exclusive state (including exclusive initialization and exclusive update) at the same time, and when an empty entry is further included in the process identifier mapping table, it is proved that an exclusive cache space unit may also be allocated to a new process that does not exist in the process identifier mapping table.

It can be understood that, in a specific exclusive mechanism of a cache space, in order to ensure smooth exclusive ownership of the cache space, it is necessary to perform exclusive initialization and exclusive update of the cache space, and in order to improve utilization efficiency of the cache space, it is also necessary to release the used cache space in time, which needs to be solved through exclusive ownership of the cache space.

As an optional implementation of the embodiment of the present invention, as shown in fig. 3, the CPU multi-core shared portion further includes, in addition to the memory 21 and the last-level cache 22, a cache space unit recorder 23, which may include a record table of an exclusive cache space unit, and according to needs, in a specific embodiment, the CPU multi-core shared portion may further include a process identifier corresponding table.

In the program running process, if an exclusive initialization request, an exclusive update request, or an exclusive release request of a cache space containing an instruction is included in the program, the storage management unit 12 knows the condition of the cache space unit corresponding to the instruction according to the memory address identifier in the request, specifically, may determine whether the execution requirement is satisfied according to the record in the cache space unit recorder 23 and the exclusive state record of the exclusive cache space unit, if so, change the record in the cache space unit recorder 23, and the execution unit 11 executes the corresponding operation, otherwise, stop executing.

Although there are various ways to identify and determine the exclusive state of the exclusive cache space unit, since the setting of the exclusive cache space unit table can make the specific operation simpler, for this reason, the following embodiment describes a way of establishing the exclusive cache space unit table, and it is understood that the method for implementing the exclusive initialization of the exclusive cache space unit by other ways of identifying, determining and modifying is also within the protection scope of the present invention.

Fig. 4 discloses an optional flow of an exclusive initialization method for a cache space as an optional implementation of the embodiment of the present invention, and based on the flow diagram shown in fig. 4, the embodiment of the present invention may implement exclusive initialization for a cache space unit.

Referring to fig. 4, a flow of an exclusive initialization method provided in an embodiment of the present invention may include:

step S10: receiving an exclusive initialization request of an instruction, wherein the exclusive initialization request comprises an instruction memory address identifier of the instruction and a process identifier of a process to which the instruction belongs.

The exclusive initialization request of the instruction may be set in a program, and when the program executes to a corresponding instruction, the exclusive initialization request is issued, and an execution main body (in an embodiment, the aforementioned storage management unit may be used as the execution main body) of the exclusive initialization method provided by the embodiment of the present invention receives the exclusive initialization request of the instruction, and obtains an instruction memory address identifier in the request and a process identifier of a process to which the instruction belongs.

The instruction may be an instruction for monopolizing a cache space of a code, or an instruction for monopolizing a cache space of data.

When the instruction is a cache space exclusive instruction (CALCI) of a code, in one embodiment, the general register rax and the general register rbx may be used as operands, wherein the general register rax stores a code memory start address requiring an exclusive cache space unit; the general register rbx stores the end address of the code memory which needs to monopolize the cache space unit. If expressed in code in assembly language, the following can be described:

mov i_start_addr,rax

mov i_end_addr,rbx

CALCI

for a cache space exclusive instruction (CALCD) of data, the CALCD may also include two operands, a general register rax and a general register rbx, where a data memory start address requiring an exclusive cache space unit is stored in the general register rax; the general register rbx stores the address length of the data memory needing to monopolize the cache space unit. If expressed in code in assembly language, the following can be described:

mov d_start_addr,rax

mov d_len,rbx

CALCD

it can be seen that in one embodiment, the instruction memory address identifier may be a memory start address and an end address of the instruction, and in other embodiments, the instruction memory address identifier may be a memory start address and a memory address length of the instruction.

And the process identification of the process to which the instruction belongs may indicate the process to which the instruction belongs.

Step S11: and obtaining the current exclusive cache space unit table entry of the current exclusive cache space unit corresponding to the current address identification section of the instruction memory address identification according to the current address identification section of the instruction memory address identification.

The instruction memory address identifier is represented by a memory start address and an instruction end address, or by a memory start address and a memory address length of the instruction, a size of the exclusive cache space unit is usually 64 bytes, and the instruction memory address identifier corresponds to the exclusive cache space unit, and the instruction memory address identifier is divided into a plurality of address identifier segments, wherein one address identifier segment corresponds to one exclusive cache space unit.

The exclusive cache space unit table entries are in one-to-one correspondence with the exclusive cache space units, and record the exclusive condition of the exclusive cache space units.

Specifically, the correspondence between the exclusive cache space unit table entry and the exclusive cache space unit may be determined by recording the number of the exclusive cache space unit in the exclusive cache space unit identification bit of the exclusive cache space unit table entry, and in other embodiments, the correspondence may be determined by the correspondence between the position of the exclusive cache space unit in the exclusive cache space and the position of the exclusive cache space unit table entry in the exclusive cache space unit table, so that the space occupied by the exclusive cache space unit table may be reduced.

When the process is exclusively initialized, the address identification segments are obtained one by one according to the instruction memory address identification, and then the exclusive cache space unit and the exclusive cache space unit table entry corresponding to the address identification segments are obtained. For convenience of description, the address identification segment in which the process exclusive initialization method is being executed is referred to as a current address identification segment.

Therefore, after receiving the initialization request of the exclusive cache of the instruction, the current exclusive cache space unit table entry of the current exclusive cache space unit corresponding to the current address identifier segment of the instruction memory address identifier needs to be obtained according to the current address identifier segment of the instruction memory address identifier.

In other embodiments, if a current exclusive cache space unit table entry for a current exclusive cache space unit is not established and the exclusive state of the current cache space unit is otherwise identified, the exclusive state of the current cache space unit may be obtained in other manners.

Step S12: and judging whether the process identification bit of the current exclusive cache space unit table entry is a non-exclusive identification, if so, executing step S13, and if not, executing step S16.

To clearly identify the exclusive condition of the exclusive cache space unit, the exclusive cache space unit table at least includes a process identification bit and an exclusive status bit, where the process identification bit can identify whether the exclusive cache space unit is exclusively or exclusively initialized? If is exclusive to which process? The exclusive status bit identifies whether the exclusive cache space unit is in the exclusively updated state or the exclusively initialized state.

After acquiring the current exclusive cache space unit table entry in the exclusive cache space unit table according to the current address identification segment, checking the process identification bit of the current cache space unit table entry, and judging whether the process identification bit is a non-exclusive identification, if so, executing step S13; when the non-exclusive id is not the specific process id, the step S16 is executed.

Specifically, the non-exclusive flag may be that each bit of the process flag bit is 0.

It can be seen that the main purpose of determining whether the process identification bit of the current exclusive cache space unit table entry is a non-exclusive identification is to determine whether the current exclusive cache space unit is neither in an exclusive update state nor in an exclusive initialization state, so as to determine that the current exclusive cache space unit can be exclusively initialized, and in an embodiment in which the exclusive cache space unit table is not established, the determination of the current exclusive cache space unit state may be implemented in other manners.

Step S13: and performing exclusive initialization on the current exclusive cache space unit table entry.

When the current exclusive cache space unit table entry is a non-exclusive identifier, it indicates that the current exclusive cache space unit corresponding to the current exclusive cache space unit is not exclusive or initialized, and may perform exclusive initialization for the instruction in the exclusive initialization request.

It can be understood that the specific manner of the exclusive initialization may include initializing and updating the process identification bit of the current exclusive cache space unit table entry to the process identification, initializing and updating the exclusive state bit of the current exclusive cache space unit table entry to an exclusive initialization state, and preparing for allocating the current exclusive cache space unit to the process to which the current exclusive cache space unit belongs to be exclusive finally, so that the current exclusive cache space unit can be exclusive by the process to which the instruction belongs.

In one embodiment, the exclusive status bit of the current exclusive cache space unit table entry may be represented by a two-bit binary bit, where 00 represents an exclusive initialization state and 01 represents an exclusive update state, and therefore, specifically, initializing and updating the exclusive status bit of the current exclusive cache space unit table entry to the exclusive initialization state may be initializing and updating the exclusive status bit to 00.

It can be understood that the exclusive initialization of the current exclusive cache space unit table entry is a specific implementation manner of the exclusive initialization of the current exclusive cache space unit, and in an embodiment where the exclusive cache space unit table is not established, the exclusive initialization of the current exclusive cache space unit may be implemented in other manners.

Step S14: and judging whether an address identification section which does not acquire the exclusive cache space unit table entry exists in the instruction memory address identification, if so, executing step 15, and if not, executing step 110.

The address identifier segment is a memory address segment corresponding to the exclusive cache space unit, and therefore, there may be a plurality of address identifier segments in the instruction memory address identifier, and after the completion of the exclusive initialization of the current address identifier segment, it is necessary to continue the processing of the next address identifier segment, and therefore it is necessary to determine whether there is an address identifier segment in the instruction memory address identifier that has not obtained the table entry of the exclusive cache space unit.

If there is an address identifier segment in the instruction memory address identifier that has not obtained the table entry of the exclusive cache space unit table, step S15 is executed: acquiring the address identification section of the unit table of the exclusive cache space which has not been acquired, and taking the address identification section of the unit table of the exclusive cache space which has not been acquired as the current address identification section; if the address identifier segment that has not acquired the table entry of the exclusive cache space unit table does not exist in the instruction memory address identifier, it indicates that all the address identifier segments in the instruction memory address identifier have been initialized exclusively, step S110 is executed: and finishing the exclusive initialization.

It should be noted that, determining whether an address identifier segment that has not acquired an entry of the exclusive cache space unit table exists in the instruction memory address identifier is a specific implementation manner of determining whether an address identifier segment that has not acquired an exclusive cache space unit exists in the instruction memory address identifier, and in an embodiment that an exclusive cache space unit table is not established, determining whether an address identifier segment that has not acquired an exclusive cache space unit exists in the instruction memory address identifier may be implemented in other manners.

Step S15: and acquiring the address identification section of the exclusive cache space unit table entry which has not been acquired, and taking the address identification section of the exclusive cache space unit table entry which has not been acquired as the current address identification section.

If there is an address identification segment that has not acquired an exclusive cache space unit table entry, the address identification segment is acquired and made to be the current address identification segment, and then step S11 is executed.

In an embodiment where the exclusive cache space unit table is not established, step S15 may be: and acquiring the address identification segment of the exclusive cache space unit which has not been acquired, and taking the address identification segment of the exclusive cache space unit which has not been acquired as the current address identification segment.

Step S16: and judging whether the process identification bit of the current exclusive cache space unit table entry is the process identification, if so, executing step S17, and if not, executing step S18.

When the process identification bit of the current cache space unit table entry is not a non-exclusive identification, judging whether the process identification recorded by the specific process identification bit is the process identification in the exclusive initialization request, if so, indicating that the current exclusive cache space unit corresponding to the current exclusive cache space unit table entry is being exclusive by the process to which the current exclusive cache space unit belongs (including exclusive updating and exclusive initialization); further performing step S17; if not, it indicates that the current exclusive cache space unit corresponding to the current exclusive cache space unit table entry is being exclusively owned by a process other than the process to which the current exclusive cache space unit table entry belongs (including exclusive update and exclusive initialization), and in order to ensure the security of process operation, the current exclusive cache space unit table entry cannot be updated any more, step S18 is executed.

In other embodiments, if the exclusive process or the exclusive initialization process of the current exclusive cache space unit is identified by other methods, the specific identification method may be used to determine whether the process identification bit of the current exclusive cache space unit table entry is the process identification.

Step S17: and judging whether the exclusive state bit of the current exclusive cache space unit table entry is in an exclusive initialization state, if so, executing the step S14, and if not, executing the step S18.

Because the current exclusive cache space unit may be in two states, an exclusive update state and an exclusive initialization state when the process identification bit of the current exclusive cache space unit table entry is the process to which the current exclusive cache space unit belongs, if the current exclusive cache space unit is in the exclusive initialization state, it indicates that the previous exclusive cache space unit has been initialized by the process to which the current exclusive cache space unit belongs, and is in a state that the previous exclusive cache space unit can be exclusively updated by the process to which the current exclusive cache space unit belongs, and step S14 is executed without initializing; if the current exclusive cache space unit is not in the exclusive initialization state, that is, is in the exclusive update state, it indicates that the previous exclusive cache space unit has been exclusively updated by the process to which the current exclusive cache space unit belongs, and is in the state incapable of being initialized, step S18 is executed.

In other embodiments, if the current exclusive cache space unit is identified in the exclusive state by other methods, the specific identification method may be implemented by determining.

Step S18: and clearing the exclusive cache space unit table entries which have completed the exclusive initialization.

When the current table entry of the exclusive cache space unit cannot be initialized, the allocation of the exclusive cache space unit cannot be performed for the entire memory address identifier, and in order to improve the utilization rate of the cache space, the table entry of the exclusive cache space unit that has completed the exclusive initialization may be cleared, and step S19 is executed, and it may be determined whether the exclusive initialization of the cache space needs to be performed again as needed.

In other embodiments, if whether the current exclusive cache space unit is in the exclusive state is identified by other manners, the clearing of the exclusive cache space unit that has completed the exclusive initialization may be implemented by clearing the identification of other manners.

Step S19: an error code is returned.

After the exclusive initialization of the cache space cannot be normally completed, different error codes are returned according to different failure reasons, so that the reason of process termination can be conveniently known.

Step S110: and (6) ending.

Ending the exclusive initialization of the cache space.

It can be seen that, in the method for initializing an exclusive cache space provided in the embodiment of the present invention, after receiving an exclusive initialization request of a cache space of an instruction, according to a current address identifier segment of an instruction memory address identifier in the exclusive initialization request, an entry of a current exclusive cache space unit table corresponding to the current address identifier segment is obtained, and a process identifier bit in the entry of the current exclusive cache space unit table records a process being exclusively owned.

Therefore, the exclusive initialization method of the cache space provided by the invention firstly judges the state of the exclusive cache space unit by obtaining the table entry of the current exclusive cache space unit, when the current exclusive cache space unit can be exclusively occupied by the process to which the instruction belongs, the table entry of the current exclusive cache space unit is initialized and updated, so that preparation is provided for the exclusive update of the current exclusive cache space unit by the process, and other processes can be prevented from sharing the current exclusive cache space unit by the exclusive ownership of the current exclusive cache space unit by the process, thereby reducing the risk that an attacker steals sensitive data by using a side channel attack technology in the cache space and even controls the execution of a program, and improving the safety of the cache space.

When the current exclusive cache space unit table entry of the current exclusive cache space unit is in the exclusive initialization completion state (the process identification bit is the process identification of the process to which the process belongs, and the exclusive state bit is the exclusive initialization state), the searching, judgment and updating of other address identification sections are continued; when the current exclusive cache space unit table entry of the current exclusive cache space unit is in a state where exclusive initialization cannot be performed (the process identification bit is other process identification except the process identification of the process to which the current exclusive cache space unit belongs, or the exclusive state bit is in an exclusive update state), the initialization update of the current exclusive cache space unit table entry is stopped, the exclusive cache space unit table entry which has completed exclusive initialization is cleared, the utilization rate of the cache space is improved, and the space occupied by the exclusive cache space unit table is reduced.

The preparation for exclusive update of the required cache space unit is realized by cycle judgment and exclusive initialization of all address identification sections of the instruction memory address identification.

For the embodiment that the state identifier of the exclusive cache space unit is implemented in other ways, according to the exclusive initialization method for the cache space provided in the embodiment of the present invention, after receiving the exclusive initialization request of the cache space of the instruction, the current exclusive cache space unit corresponding to the current address identifier segment of the instruction memory address identifier in the exclusive initialization request is obtained, and the current exclusive cache space unit is in a state that the current exclusive cache space unit is not exclusively owned, and can be exclusively owned by the instruction of the process to which the current exclusive cache space unit belongs, so that the current exclusive cache space unit can be exclusively owned by the process to which the instruction belongs.

Therefore, the exclusive initialization method and device of the cache space provided by the invention firstly judge the state of the exclusive cache space unit by acquiring the current exclusive cache space unit, when the current exclusive cache space unit can be exclusively occupied by the process to which the instruction belongs, the current exclusive cache space unit is initialized and updated, so that preparation is provided for the exclusive update of the current exclusive cache space unit by the process, and other processes can be prevented from sharing the current exclusive cache space unit by the exclusive ownership of the current exclusive cache space unit by the process, thereby reducing the risk that an attacker steals sensitive data or even controls the execution of a program by using a side channel attack technology in the cache space, and improving the security of the cache space.

Because of the limitation of the cache space, the number of exclusive cache space units that the same process can exclusively initialize and exclusively update at the same time needs to be limited, so that the number of allowed exclusive cache space units that the process can exclusively use is configured, and in order to ensure that the number of the exclusive cache space units can meet the requirement when an exclusive initialization request of an instruction is received, the embodiment of the invention further provides another exclusive initialization method of the cache space.

Referring to fig. 5, fig. 5 is another flowchart illustrating an exclusive initialization method for a cache space according to an embodiment of the present invention.

As can be seen from the figure, the method for initializing the exclusive use of the cache space according to the embodiment of the present invention includes:

step S20: receiving an exclusive initialization request of an instruction, wherein the exclusive initialization request comprises an instruction memory address identifier of the instruction and a process identifier of a process to which the instruction belongs.

Step S20 can refer to the description of step S10 in fig. 4, and will not be described herein.

S21, obtaining the number of cache space units exclusive for application of the instruction according to the memory address identifier, and obtaining the number of cache space units exclusive for the process according to the process identifier.

Because the address identification section of the memory address identification corresponds to the exclusive cache space unit, the number of the exclusive cache space units can be applied according to the memory address identification.

The exclusive cache space unit table entries and the exclusive cache space units have a one-to-one correspondence relationship, and the process identification bits of the exclusive cache space unit table entries corresponding to the exclusive cache space units in the exclusive state (including the exclusive initialization state and the exclusive update state) are the process identifications of the processes, so that the process identifications are searched from the exclusive cache space unit table as the entries of the process identifications of the processes, and the number of the exclusive cache space units which are already exclusive to the processes can be obtained.

In other embodiments, when the exclusive cache space unit table is not established, the obtaining of the number of the exclusive cache space units which have been exclusively owned by the process to which the exclusive cache space unit table belongs may be realized in other ways

Before the program runs, the number of the allowed exclusive cache space units of the process is configured.

Thus, through the above process, the number of the exclusive cache space units applied, the number of the exclusive cache space units of the process and the number of the allowed exclusive cache space units of the process have been obtained.

Step S22: determining whether the sum of the number of the exclusive cache space units and the number of the applied exclusive cache space units is less than or equal to the number of the allowed exclusive cache space units of the process, if so, executing step S23, otherwise, executing step S211.

After obtaining the number of the applied exclusive cache space units, the number of the exclusive cache space units and the number of the allowed exclusive cache space units, calculating the sum of the number of the applied exclusive cache space units and the number of the exclusive cache space units, then judging whether the sum is less than or equal to the number of the allowed exclusive cache space units, if so, executing step S23, otherwise, executing step S211.

Step S23: obtaining a current exclusive cache space unit table entry of a current exclusive cache space unit corresponding to the current address identification section of the instruction memory address identification according to the current address identification section of the instruction memory address identification;

step S23 can refer to the description of step S11 shown in fig. 4, and will not be described herein.

Step S24: and judging whether the process identification bit of the current exclusive cache space unit table entry is a non-exclusive identification, if so, executing step S25, and if not, executing step S28.

Step S24 can be described with reference to step S12 in fig. 4, where when the process flag of the current exclusive cache space unit table entry is a non-exclusive flag, step S25 is executed; otherwise, step S28 is executed.

Step S25: and performing exclusive initialization on the current exclusive cache space unit table entry.

Step S25 can refer to the description of step S13 shown in fig. 4, and will not be described herein.

Step S26: and judging whether the instruction memory address identifier has an address identifier section which does not acquire the exclusive cache space unit table entry, if so, executing step 27, and if not, executing step 212.

Step S26 can be described with reference to step S14 in fig. 4, if there is an address identifier segment in the instruction memory address identifier that has not obtained the table entry of the exclusive cache space unit table, then step S27 is executed: acquiring the address identification section of the unit table of the exclusive cache space which has not been acquired, and taking the address identification section of the unit table of the exclusive cache space which has not been acquired as the current address identification section; if the address identifier segment that has not acquired the table entry of the exclusive cache space unit table does not exist in the instruction memory address identifier, it indicates that all the address identifier segments in the instruction memory address identifier have been initialized exclusively, step S212 is executed: and finishing the exclusive initialization.

Step S27: and acquiring the address identification section of the exclusive cache space unit table which has not been acquired, and taking the address identification section of the exclusive cache space unit table which has not been acquired as the current address identification section.

Step S27 may refer to the description of step S15 of fig. 4, and if there is an address identification segment that has not acquired the exclusive cache space unit table, acquire the address identification segment and let the address identification segment be the current address identification segment, and then execute step S23.

Step S28: and judging whether the process identification bit of the current exclusive cache space unit table entry is the process identification, if so, executing step 29, and if not, executing step 210.

Step S28 can refer to the description of step S16 shown in fig. 4, and when the process flag of the current cache space unit table entry is not a non-exclusive flag, determine whether the process flag recorded by the specific process flag is the process flag in the exclusive initialization request, and if so, indicate that the current exclusive cache space unit corresponding to the current exclusive cache space unit table entry is being exclusive by the process to which the current exclusive cache space unit belongs (including exclusive update and exclusive initialization); further performing step S29; if not, it indicates that the current exclusive cache space unit corresponding to the current exclusive cache space unit table entry is being exclusively owned by other processes (including exclusive update and exclusive initialization) other than the process to which the current exclusive cache space unit table entry belongs, and to ensure the security of process operation, the current exclusive cache space unit table entry cannot be updated any more, and step S210 is executed.

Step S29: and judging whether the exclusive state bit of the current exclusive cache space unit table entry is in an exclusive initialization state, if so, executing step 26, and if not, executing step 210.

Step S29 can refer to the description of step S17 in fig. 4, and if the current exclusive cache space unit is in the exclusive initialization state, it indicates that the previous exclusive cache space unit has been initialized by the process to which the current exclusive cache space unit belongs, and is in a state that the previous exclusive cache space unit can be exclusively updated by the process to which the current exclusive cache space unit belongs, and step S26 is executed without performing initialization; if the current exclusive cache space unit is not in the exclusive initialization state, that is, is in the exclusive update state, it indicates that the previous exclusive cache space unit has been exclusively updated by the process to which the current exclusive cache space unit belongs, and is in the state incapable of being initialized, step S210 is executed.

Step S210: and clearing the exclusive cache space unit table entries which have completed the exclusive initialization.

Step S210 may refer to the description of step S18 in fig. 4, and when the current exclusive cache space unit table entry cannot be initialized, the exclusive cache space unit table entry that has completed the exclusive initialization may be cleared, and step S211 may be performed, and it may be determined whether the exclusive initialization of the cache space needs to be performed again as needed.

Step S211: an error code is returned.

Step S211 can refer to the description of step S19 in fig. 4, and is not described herein again.

Step S212: and (6) ending.

Step S212 can refer to the description of step S110 shown in fig. 4, and is not described herein again.

It can be seen that, in the method for initializing exclusive cache space provided in the embodiment of the present invention, before performing the exclusive initialization of the cache space unit, it is determined in advance whether the requirement for applying for the number of the exclusive cache space units is met, so that on one hand, the requirement for limiting the cache space is met, and on the other hand, after performing the exclusive initialization of a part of entries of the exclusive cache space unit, it can be prevented that there are not enough exclusive cache space units, which causes resource waste and an increase in computation amount.

It can be understood that, when a process runs, a corresponding memory address is allocated, and a memory address corresponding to an instruction in the process should be a part of a process memory address, so that it is necessary to ensure that an instruction memory address identifier is a part of a memory address identifier range of the process to which the instruction memory address identifier belongs, thereby preventing a memory address in the instruction memory address identifier from not belonging to the memory address range of the process to which the instruction memory address identifier belongs and causing a running error. Therefore, the embodiment of the present invention further provides another exclusive initialization method for a cache space.

Referring to fig. 6, fig. 6 is a flowchart illustrating a method for initializing an exclusive ownership of a cache space according to an embodiment of the present invention.

step S30: receiving an exclusive initialization request of an instruction, wherein the exclusive initialization request comprises an instruction memory address identifier of the instruction and a process identifier of a process to which the instruction belongs.

Step S30 can refer to the description of step S10 in fig. 4, and will not be described herein.

S31, obtaining the allocated memory address identifier of the process according to the process identifier.

The allocated memory address identifier (i.e., the memory address range) of the process is allocated before the process runs, or is allocated in advance for the subsequent instruction execution based on the requirement during the process running, so that the allocated memory address identifier of the process can be determined according to the process identifier.

And the instruction memory address identification can be obtained through an exclusive initialization request of the instruction.

Step S32: and judging whether the instruction memory address identifier belongs to the allocated memory address identifier, if so, executing step S33, and if not, executing step S311.

After the allocated memory address identifier and the instruction memory address identifier of the process are obtained, whether the instruction memory address identifier belongs to the allocated memory address identifier can be determined by comparing the instruction memory address identifier with the allocated memory address identifier of the process.

If the instruction memory address id belongs to the allocated memory address id, step S33 is executed, otherwise, step S311 is executed.

Step S33: obtaining a current exclusive cache space unit table entry of a current exclusive cache space unit corresponding to the current address identification section of the instruction memory address identification according to the current address identification section of the instruction memory address identification;

step S33 can refer to the description of step S11 shown in fig. 4, and will not be described herein.

Step S34: and judging whether the process identification bit of the current exclusive cache space unit table entry is a non-exclusive identification, if so, executing step S35, and if not, executing step S38.

Step S34 can be described with reference to step S12 in fig. 4, where when the process flag of the current exclusive cache space unit table entry is a non-exclusive flag, step S35 is executed; otherwise, step S38 is executed.

Step S35: and performing exclusive initialization on the current exclusive cache space unit table entry.

Step S35 can refer to the description of step S13 shown in fig. 4, and will not be described herein.

Step S36: and judging whether an address identifier section which does not acquire the exclusive cache space unit table entry exists in the instruction memory address identifier, if so, executing step 37, and if not, executing step 312.

Step S36 can be described with reference to step S14 in fig. 4, if there is an address identifier segment in the instruction memory address identifier that has not obtained the table entry of the exclusive cache space unit table, then step S37 is executed: acquiring the address identification section of the unit table of the exclusive cache space which has not been acquired, and taking the address identification section of the unit table of the exclusive cache space which has not been acquired as the current address identification section; if the address identifier segment that has not acquired the table entry of the exclusive cache space unit table does not exist in the instruction memory address identifier, it indicates that all the address identifier segments in the instruction memory address identifier have been initialized exclusively, step S312 is executed: and finishing the exclusive initialization.

Step S37: and acquiring the address identification section of the exclusive cache space unit table which has not been acquired, and taking the address identification section of the exclusive cache space unit table which has not been acquired as the current address identification section.

If there is an address identification section for which the exclusive cache space unit table has not been acquired, the address identification section is acquired and made to be the current address identification section, and then step S33 is performed.

Step S38: and judging whether the process identification bit of the current exclusive cache space unit table entry is the process identification, if so, executing step 39, and if not, executing step 310.

When the process identification bit of the current cache space unit table entry is not a non-exclusive identification, judging whether the process identification recorded by the specific process identification bit is the process identification in the exclusive initialization request, if so, indicating that the current exclusive cache space unit corresponding to the current exclusive cache space unit table entry is being exclusive by the process to which the current exclusive cache space unit belongs (including exclusive updating and exclusive initialization); further performing step S39; if not, it indicates that the current exclusive cache space unit corresponding to the current exclusive cache space unit table entry is being exclusively owned by other processes (including exclusive update and exclusive initialization) other than the process to which the current exclusive cache space unit table entry belongs, and to ensure the security of process operation, the current exclusive cache space unit table entry cannot be updated any more, and step S310 is executed.

Step S39: and judging whether the exclusive state bit of the current exclusive cache space unit table entry is in an exclusive initialization state, if so, executing step 36, and if not, executing step 310.

If the current exclusive cache space unit is in the exclusive initialization state, it indicates that the previous exclusive cache space unit has been initialized by the affiliated process, and is in a state that can be exclusively updated by the affiliated process, and step S36 is executed without performing initialization; if the current exclusive cache space unit is not in the exclusive initialization state, that is, is in the exclusive update state, it indicates that the previous exclusive cache space unit has been exclusively updated by the process to which the current exclusive cache space unit belongs, and is in the state incapable of being initialized, step S310 is executed.

Step S310: and clearing the exclusive cache space unit table entries which have completed the exclusive initialization.

Step S310 may refer to the description of step S18 in fig. 4, and when the current exclusive cache space unit table entry cannot be initialized, the exclusive cache space unit table entry that has completed the exclusive initialization may be cleared, and step S311 is performed, and it may be determined whether the exclusive initialization of the cache space needs to be performed again as needed.

Step S311: an error code is returned.

Step S311 can refer to the description of step S19 in fig. 4, and is not described herein again.

Step S312: and (6) ending.

Step S312 can refer to the description of step S110 shown in fig. 4, and is not described herein again.

It can be seen that, in the method for initializing the exclusive memory space provided in the embodiment of the present invention, before the exclusive initialization of the cache space unit is performed, it is determined in advance that the instruction memory address identifier belongs to the allocated memory address identifier range of the process to which the instruction memory address identifier belongs, so as to avoid that, after the exclusive initialization of a part of the entries of the exclusive cache space unit is performed, a part of the memory addresses in the instruction memory address identifier do not belong to the allocated memory address identifier of the process to which the instruction memory address identifier belongs, which causes resource waste and an increase in the amount of operation.

Of course, in another embodiment, the judgment of whether the instruction memory address identifier belongs to the allocated memory address identifier range of the process to which the instruction memory address identifier belongs, and the judgment of whether the sum of the number of the exclusive cache space units and the number of the applied exclusive cache space units is less than or equal to the number of the exclusive cache space units allowed by the process to which the instruction memory address identifier belongs may exist simultaneously, and the table entries of the exclusive cache space units may be obtained, judged and updated only when the two aforementioned conditions are all satisfied, so as to further avoid resource waste and increase of the amount of computation.

In order to save the space occupied by the exclusive cache space unit table, in a specific embodiment, a process identifier corresponding table is further set, and in order to further increase the function of the process identifier corresponding table, the entry of the process identifier corresponding table may be set to be consistent with the number of processes allowed to have exclusive cache space, so that whether the number of processes in the exclusive state reaches the limit or not can be easily judged, and subsequent processing is performed as a result. Therefore, the embodiment of the present invention further provides another exclusive initialization method for a cache space.

Referring to fig. 7, fig. 7 is a further flowchart illustrating an exclusive initialization method for a cache space according to an embodiment of the present invention.

step S40: receiving an exclusive initialization request of an instruction, wherein the exclusive initialization request comprises an instruction memory address identifier of the instruction and a process identifier of a process to which the instruction belongs.

Step S40 can refer to the description of step S10 in fig. 4, and will not be described herein.

S41: and acquiring the number of the cache space units applied for exclusive caching of the instruction according to the memory address identifier, and acquiring the number of the exclusive cache space units of the process according to the process identifier.

Step S41 can refer to the description of step S21 shown in fig. 5, and will not be described herein.

Step S42: determining whether the sum of the number of the exclusive cache space units and the number of the applied exclusive cache space units is less than or equal to the number of the allowed exclusive cache space units of the process, if so, executing step 43, otherwise, executing step 415.

After obtaining the number of the applied exclusive cache space units, the number of the exclusive cache space units and the number of the allowed exclusive cache space units, calculating the sum of the number of the applied exclusive cache space units and the number of the exclusive cache space units, and then judging whether the sum is less than or equal to the number of the allowed exclusive cache space units, if so, executing step S43, otherwise, executing step S415.

Of course, in another specific implementation manner, after further determining that the instruction memory address identifier belongs to the allocated memory address identifier range of the process to which the instruction memory address identifier belongs, step S43 may be executed.

Step S43: and whether the process identification is found in the process identification corresponding table.

The process identifier correspondence table is a table for recording the correspondence between process identifiers and simplified process identifiers, and includes: the simplified process identifier may be a number of an entry of the process identifier mapping table.

After receiving the exclusive initialization request of the instruction, searching the process identifier in the process identifier corresponding table, if the process identifier is found, indicating that the simplified process identifier has been allocated to the process to which the instruction belongs, and executing step S44; if not, indicating that the simplified process identifier is not allocated to the process at the current time, step S410 is executed.

Step S44: and recording the simplified process identification corresponding to the process identification in the table entry of the process identification corresponding table.

If the process identification of the process is found, the simplified process identification corresponding to the process identification can be found according to the table entry where the process identification is located, and then the simplified process identification is recorded to prepare for the subsequent initialization updating of the exclusive cache space unit.

Step S45: obtaining a current exclusive cache space unit table entry of a current exclusive cache space unit corresponding to the current address identification section of the instruction memory address identification according to the current address identification section of the instruction memory address identification;

step S45 can refer to the description of step S11 shown in fig. 4, and will not be described herein.

Step S46: and judging whether the process identification bit of the current exclusive cache space unit table entry is a non-exclusive identification, if so, executing step 47, and if not, executing step 412.

Step S46 can be described with reference to step S12 in fig. 4, where when the process flag of the current exclusive cache space unit table entry is a non-exclusive flag, step S47 is executed; otherwise, step S412 is executed.

Step S47: and performing exclusive initialization on the current exclusive cache space unit table entry.

Step S47 can refer to the description of step S13 shown in fig. 4, and will not be described herein.

Step S48: and judging whether an address identifier section which does not acquire the exclusive cache space unit table entry exists in the instruction memory address identifier, if so, executing step 49, and if not, executing step 416.

Step S48 can be described with reference to step S14 in fig. 4, if there is an address identifier segment in the instruction memory address identifier that has not obtained the table entry of the exclusive cache space unit table, then step S48 is executed: acquiring the address identification section of the unit table of the exclusive cache space which has not been acquired, and taking the address identification section of the unit table of the exclusive cache space which has not been acquired as the current address identification section; if the address identifier segment that has not acquired the table entry of the exclusive cache space unit table does not exist in the instruction memory address identifier, it indicates that all the address identifier segments in the instruction memory address identifier have been initialized exclusively, step S416 is executed: and finishing the exclusive initialization.

Step S49: and acquiring the address identification section of the exclusive cache space unit table which has not been acquired, and taking the address identification section of the exclusive cache space unit table which has not been acquired as the current address identification section.

If there is an address identification segment for which the exclusive cache space unit table has not been acquired, the address identification segment is acquired and is made to be the current address identification segment, and then step S410 is performed.

Step S410: and determining whether the process identification corresponding table has an empty table entry.

When the process identifier of the process to which the process belongs is not found in the process identifier corresponding table, further determining whether an empty entry still exists in the process identifier corresponding table, if so, indicating that although the process to which the process belongs does not have an exclusive cache space unit (including exclusive initialization and exclusive update), the process which can monopolize the cache space can still be added, and executing step S411; if there is no empty entry, it indicates that the number of the current exclusive cache space has reached the maximum value, and the exclusive initialization of the cache space for the new process may no longer be performed, then step S415 is executed.

Step S411: and selecting a null table entry from the process identifier corresponding table to obtain a selected null table entry, and updating the selected null table entry.

And if a new process for monopolizing the cache space can be added, selecting a null table item from the process identification corresponding table to obtain a selected null table item, and updating the selected null table item.

It is understood that the specific updating manner includes: and updating the process identification bit of the empty table entry to the process identification of the process to which the empty table entry belongs, and updating the simplified process identification bit of the empty table entry to the simplified process identification corresponding to the empty table entry. Of course, when the simplified process flag is the entry number, the simplified process flag is updated to the entry number, and then step S44 is executed to record the simplified process flag.

Step S412: and judging whether the process identification bit of the current exclusive cache space unit table entry is the process identification, if so, executing step S413, and if not, executing step S414.

When the process identification bit of the current cache space unit table entry is not a non-exclusive identification, judging whether the process identification recorded by the specific process identification bit is the process identification in the exclusive initialization request, if so, indicating that the current exclusive cache space unit corresponding to the current exclusive cache space unit table entry is being exclusive by the process to which the current exclusive cache space unit belongs (including exclusive updating and exclusive initialization); step S413 is further performed; if not, it indicates that the current exclusive cache space unit corresponding to the current exclusive cache space unit table entry is being exclusively owned by other processes (including exclusive update and exclusive initialization) other than the process to which the current exclusive cache space unit table entry belongs, and to ensure the security of process operation, the current exclusive cache space unit table entry cannot be updated any more, and step S414 is executed.

Step S413: and judging whether the exclusive state bit of the current exclusive cache space unit table entry is in an exclusive initialization state, if so, executing step 48, and if not, executing step 414.

If the current exclusive cache space unit is in the exclusive initialization state, it indicates that the previous exclusive cache space unit has been initialized by the affiliated process, and is in a state that can be exclusively updated by the affiliated process, and step S48 is executed without performing initialization; if the current exclusive cache space unit is not in the exclusive initialization state, that is, is in the exclusive update state, it indicates that the previous exclusive cache space unit has been exclusively updated by the process to which the current exclusive cache space unit belongs, and is in the state incapable of being initialized, step S414 is executed.

Step S414: clearing the initialized exclusive cache space unit table entries and the updated empty entries of the process identification corresponding table.

Step S414 may refer to the description of step S18 in fig. 4, and may clear the exclusive cache space unit table entry that has completed the exclusive initialization when the current exclusive cache space unit table entry cannot be initialized, however, in the case of the process identifier corresponding table, if the simplified process identifier is obtained by acquiring the empty entry, the empty entry of the updated process identifier corresponding table needs to be cleared.

It is to be understood that clearing the initialized exclusive cache space unit table entry as described herein refers to clearing the contents in the exclusive cache space unit table entry, and that clearing the empty entry of the updated process identification correspondence table refers to clearing the contents filled after the empty entry is updated.

Step S415: an error code is returned.

Step S415 may refer to the description of step S19 in fig. 4, and will not be described herein.

Step S416: and (6) ending.

Step S416 may refer to the description of step S110 shown in fig. 4, and is not described herein again.

It can be seen that, in the method for initializing the exclusive cache space provided in the embodiment of the present invention, by setting the process identifier mapping table, on one hand, the space occupied by the exclusive cache space unit table can be reduced; on the other hand, the number of processes monopolizing the cache space at the moment when the exclusive initialization request of the instruction is received can be determined, so that the number of processes monopolizing the cache space at the same time can be ensured to be within a specified range, the utilization rate of the cache space is ensured, and the implementation mode is simple.

Of course, in other embodiments, the control of the number of processes that have exclusive cache space at the same time may be implemented in other ways, such as: and setting the maximum value of the number of processes which simultaneously monopolize the cache space, acquiring the number of the processes which simultaneously monopolize the cache space at the time of receiving the monopolizing initialization request of the instruction, and determining whether the processes can be subjected to monopolizing initialization for the processes in a comparison and judgment mode.

The following describes an exclusive initialization apparatus for a cache space provided in an embodiment of the present invention from the perspective of an execution apparatus (e.g., a storage management unit), where the exclusive initialization apparatus for a cache space described below may be considered as a program module that is required by the execution apparatus to implement the exclusive initialization method for a cache space provided in the embodiment of the present invention. The exclusive initialization device of the cache space described below may be referred to in correspondence with the contents of the above-described scheme.

Fig. 8 is an alternative block diagram of an apparatus for initializing an exclusive cache space according to an embodiment of the present invention, where the apparatus may include:

an exclusive initialization request receiving unit 100, adapted to receive an exclusive initialization request of an instruction, where the exclusive initialization request includes an instruction memory address identifier of the instruction;

a current exclusive cache space unit obtaining unit 110, adapted to obtain, according to the current address identifier segment of the instruction memory address identifier, a current exclusive cache space unit corresponding to the current address identifier segment;

an exclusive initialization unit 120, adapted to perform exclusive initialization on the current exclusive cache space unit when the current exclusive cache space unit is in a non-exclusive state, so that the current exclusive cache space unit can be exclusively owned by the process to which the instruction belongs.

In a specific embodiment, the specific condition of the exclusive cache space unit may be grasped by establishing an exclusive cache space unit table, so that the current exclusive cache space unit obtaining unit 110 obtains the current exclusive cache space unit table entry corresponding to the current address identification section of the instruction memory address identification, and the exclusive initializing unit 120 performs exclusive initialization on the current exclusive cache space unit table entry when the process identification bit of the current exclusive cache space unit table entry is a non-exclusive identification, so that the current exclusive cache space unit can be exclusively owned by the process to which the instruction belongs.

Therefore, the exclusive initializing device for cache space provided in the embodiment of the present invention first receives an exclusive initializing request of an instruction by using the exclusive initializing request receiving unit 100, then determines the state of the exclusive cache space unit by using the current exclusive cache space unit obtaining unit 110 to obtain the current exclusive cache space unit, when the current exclusive cache space unit is exclusive to the process to which the instruction belongs, the exclusive initializing unit 120 performs an initialization update on the current exclusive cache space unit to prepare for the exclusive update of the current exclusive cache space unit by the process, and prevents other processes from sharing the current exclusive cache space unit by monopolizing the current exclusive cache space unit by the process, thereby reducing the risk that an attacker steals sensitive data or even controls the execution of a program in a cache space using side channel attack technology, the safety of the cache space is improved.

In a specific embodiment, as shown in fig. 9, fig. 9 is an optional block diagram of the exclusive initialization unit shown in fig. 8, and the exclusive initialization unit 120 may include:

an entry process identification bit initialization updating unit 121, adapted to initialize and update the process identification bit of the current exclusive cache space unit entry to the process identification;

an entry exclusive state bit initialization updating unit 122, adapted to initialize and update the exclusive state bit of the current exclusive cache space unit entry to an exclusive initialization state.

Specifically, the process identification bit and the exclusive state bit of the current exclusive cache space unit table entry are initialized and updated, so that the current exclusive cache space unit table entry and the current exclusive cache space unit are initialized and updated.

Since there may be multiple address identifier segments in the instruction memory address identifier, and after the exclusive initialization of the current address identifier segment is completed, processing of the next address identifier segment needs to be continued, for this reason, another exclusive initialization apparatus for a cache space is further provided in the embodiment of the present invention, as shown in fig. 10, fig. 10 is another optional block diagram of the exclusive initialization apparatus for a cache space provided in the embodiment of the present invention.

The exclusive initialization device for a cache space provided in the embodiment of the present invention includes, in addition to the exclusive initialization request receiving unit 200, the current exclusive cache space unit obtaining unit 210, and the exclusive initialization unit 220, the following: the current address identifier segment obtaining unit 230 is adapted to, after performing exclusive initialization on a previous exclusive cache space unit, obtain, if an address identifier segment of an exclusive cache space unit has not been obtained yet in the instruction memory address identifier, the address identifier segment of the exclusive cache space unit has not been obtained yet, and send, as a current address identifier segment, the address identifier segment of the exclusive cache space unit that has not been obtained yet to the current exclusive cache space unit obtaining unit 210.

The current address identifier segment obtaining unit 230 is further adapted to, when the current exclusive cache space unit is in an exclusive initialization state by the process to which the current exclusive cache space unit belongs, obtain, if an address identifier segment that has not obtained the exclusive cache space unit exists in the instruction memory address identifier, the address identifier segment that has not obtained the exclusive cache space unit, and send, as the current address identifier segment, the address identifier segment that has not obtained the exclusive cache space unit to the current exclusive cache space unit obtaining unit 210.

In order to ensure that the number of the exclusive cache space units can meet the requirement when an exclusive initialization request of an instruction is received, another exclusive initialization apparatus for a cache space is further provided in the embodiment of the present invention, as shown in fig. 11, fig. 11 is another optional block diagram of the exclusive initialization apparatus for a cache space provided in the embodiment of the present invention.

As shown in the figure, another exclusive initializing device for a cache space according to an embodiment of the present invention includes an exclusive initializing request receiving unit 300, a current exclusive cache space unit obtaining unit 310, an exclusive initializing unit 320, and a current address identifier segment obtaining unit 330, and further includes:

an exclusive cache space unit application number obtaining unit 340, adapted to obtain the number of exclusive cache space units application for the instruction according to the instruction memory address identifier;

a process exclusive cache space unit number obtaining unit 350, adapted to obtain, according to the process identifier, the number of exclusive cache space units of the process;

the unit 310 for obtaining the current exclusive cache space unit is adapted to obtain the current exclusive cache space unit corresponding to the current address identifier segment of the instruction memory address identifier according to the current address identifier segment of the instruction memory address identifier when the sum of the number of the process exclusive cache space units and the number of the applied exclusive cache space units is less than or equal to the number of the allowed exclusive cache space units of the process.

When the sum of the number of the process-owned cache space units and the number of the applied exclusive cache space units is greater than the number of the process-allowed exclusive cache space units, the current exclusive cache space unit obtaining unit 310 ends the exclusive initialization.

To reduce the space occupied by the exclusive cache space unit table, a simplified process identifier may be set, so in an embodiment, as shown in fig. 12, fig. 12 is an optional block diagram of the unit for acquiring the number of process-exclusive cache space units shown in fig. 11, and the unit for acquiring the number of process-exclusive cache space units 350 may include:

a simplified process identifier obtaining unit 351, adapted to find a simplified process identifier according to the process identifier;

a process-monopolized number obtaining unit 352 adapted to search the list items of the process-monopolized cache space unit table according to the simplified process identifier to obtain the number of process-monopolized cache space units;

and the table entry process identification bit initialization updating unit is suitable for initializing and updating the process identification bit of the current exclusive cache space unit table entry into the simplified process identification.

In order to facilitate searching, a process identification corresponding table can be further set, wherein the process identification corresponding table comprises a process identification bit for recording the process identification and a simplified process identification bit for recording the simplified process identification;

the simplified process identifier obtaining unit 351 is adapted to obtain the simplified process identifier from the process identifier mapping table according to the process identifier.

Under the condition of setting the process identification corresponding table, in order to further increase the function of the process identification corresponding table, in a specific embodiment, the table entry of the process identification corresponding table can be set to be consistent with the number of the processes which are allowed to monopolize the cache space, so that whether the number of the processes in the monopolize state reaches the limit or not can be easily judged, and the subsequent processing can be carried out as a result. Therefore, the embodiment of the present invention further provides another apparatus for initializing an exclusive cache space.

Referring to fig. 13, fig. 13 is a block diagram illustrating still another alternative block diagram of an apparatus for initializing an exclusive portion of a cache space according to an embodiment of the present invention.

Another exclusive initialization apparatus for a cache space provided in an embodiment of the present invention includes: an exclusive initialization request receiving unit 400, a current exclusive cache space unit obtaining unit 410, an exclusive initialization unit 420, a current address identification segment obtaining unit 430, an exclusive cache space unit application number obtaining unit 440, a process-exclusive cache space unit number obtaining unit 450, and a selected empty entry updating unit 460.

A selected empty entry updating unit 460, adapted to select an empty entry from the process identifier corresponding table to obtain a selected empty entry and update the selected empty entry to establish a relationship between the process identifier and the simplified process identifier and send the simplified process identifier of the selected empty entry to the simplified process identifier obtaining unit when the process identifier is not found in the process identifier corresponding table and an empty entry exists in the process identifier corresponding table.

In the foregoing case, if the process identification bit of the current exclusive cache space unit table entry is a process identification and the process identification is different from the process identification of the process to which the current exclusive cache space unit table entry belongs, or the exclusive state bit of the exclusive cache space unit table entry is an exclusive update state, the empty table entries of the exclusive cache space unit table entry that has completed the exclusive initialization and the updated process identification corresponding table need to be cleared to improve the utilization rate of the cache space unit

A first clearing unit 470, adapted to clear the exclusive initialization of the exclusive cache space unit having completed the exclusive initialization and clear the empty table entry of the updated process identification mapping table when the current exclusive cache space unit is exclusively initialized or exclusively initialized by a process different from the process to which the instruction belongs

When the process identifier mapping table is not established, in order to implement the foregoing function, another exclusive initialization apparatus for a cache space is provided in an embodiment of the present invention, as shown in fig. 14, and fig. 14 shows another optional block diagram of the exclusive initialization apparatus for a cache space provided in the embodiment of the present invention.

The apparatus for initializing an exclusive cache space provided in the embodiment of the present invention includes an exclusive initialization request receiving unit 500, a current exclusive cache space unit obtaining unit 510, an exclusive initialization unit 520, a current address identifier obtaining unit 530, an exclusive cache space unit quantity applying obtaining unit 540, a process-exclusive cache space unit quantity obtaining unit 550, and a second clearing unit 570.

A second clearing unit 570, adapted to clear the exclusive initialization of the exclusive cache space unit that has completed the exclusive initialization when the current exclusive cache space unit is exclusively or exclusively initialized by a process different from the process to which the instruction belongs.

It can be understood that, when a process runs, a corresponding memory address is allocated, and a memory address corresponding to an instruction in the process should be a part of a process memory address, so that it is necessary to ensure that an instruction memory address identifier is a part of a memory address identifier range of the process to which the instruction memory address identifier belongs, thereby preventing a memory address in the instruction memory address identifier from not belonging to the memory address range of the process to which the instruction memory address identifier belongs and causing a running error. To this end, an embodiment of the present invention further provides another exclusive initialization apparatus for a cache space, where a current exclusive cache space unit obtaining unit includes:

the allocated memory address identifier acquisition unit is suitable for acquiring the allocated memory address identifier of the process according to the process identifier;

a conditional current exclusive cache space unit obtaining unit, adapted to obtain a current exclusive cache space unit corresponding to the instruction memory address identifier according to the current address identifier segment of the instruction memory address identifier when the instruction memory address identifier belongs to the allocated memory address identifier

The embodiment of the present invention further provides a central processing unit, which is adapted to execute a program for implementing the aforementioned exclusive initialization method for a cache space.

The embodiment of the present invention further provides a storage medium, where the storage medium stores a program suitable for performing exclusive initialization of a cache space, so as to implement the aforementioned exclusive initialization method for the cache space.

Therefore, the state of the exclusive cache space unit is judged by acquiring the current exclusive cache space unit, when the current exclusive cache space unit can be monopolized by the instructed process, the current exclusive cache space unit is initialized and updated, preparation is made for the process to monopolize the current exclusive cache space unit, other processes can be prevented from sharing the current exclusive cache space unit through monopolizing the current exclusive cache space unit by the process, the risk that an attacker steals sensitive data or even controls program execution in the cache space by using a side channel attack technology can be reduced, and the security of the cache space is improved.

While various embodiments of the present invention have been described above, various alternatives described in the various embodiments can be combined and cross-referenced without conflict to extend the variety of possible embodiments that can be considered disclosed and disclosed in connection with the embodiments of the present invention.

Although the embodiments of the present invention have been disclosed, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A method for initializing exclusive ownership of a cache space, comprising:

when the current exclusive cache space unit is in a non-exclusive state, performing exclusive initialization on the current exclusive cache space unit so as to enable the current exclusive cache space unit to be exclusively occupied by the process of the instruction;

the exclusive initialization request also comprises a process identification of the process of the instruction;

the step of initializing the current exclusive cache space unit exclusively includes:

initializing and updating a process identification bit of a current exclusive cache space unit table entry of the current exclusive cache space unit into the process identification;

initializing and updating the exclusive state bit of the current exclusive cache space unit table entry into an exclusive initialization state;

and when the current exclusive cache space unit is exclusively initialized or exclusively initialized by a process different from the process of the instruction, clearing the exclusive initialization of the exclusive cache space unit which has completed the exclusive initialization.

2. The method for initializing exclusivity of a cache space as claimed in claim 1, further comprising:

after the previous exclusive cache space unit is initialized in an exclusive manner, if an address identification section of the exclusive cache space unit is not acquired in the instruction memory address identification, the address identification section of the exclusive cache space unit is acquired, the address identification section of the exclusive cache space unit is taken as a current address identification section, and the step of acquiring the current exclusive cache space unit corresponding to the current address identification section according to the instruction memory address identification is turned to be executed.

3. The method for initializing monopoly of cache space according to claim 1, wherein before the step of obtaining the current unit of the monopoly cache space corresponding to the current address identifier segment according to the instruction memory address identifier, the method further comprises:

acquiring the number of cache space units applied for monopolizing by the instruction according to the instruction memory address identifier, and acquiring the number of the monopolized cache space units of the process according to the process identifier;

and when the sum of the number of the process exclusive cache space units and the number of the application exclusive cache space units is smaller than or equal to the number of the allowed exclusive cache space units of the process, executing the step of acquiring the corresponding current exclusive cache space units according to the current address identification section of the instruction memory address identification.

4. The method for initializing exclusivity of a cache space as claimed in claim 3, further comprising:

and when the sum of the number of the process exclusive cache space units and the number of the application exclusive cache space units is greater than the number of the process allowed exclusive cache space units, returning an error code.

5. The method for initializing monopoly of cache space according to claim 3, wherein the step of obtaining the number of the monopolized cache space units of the process according to the process identifier comprises:

searching a simplified process identifier according to the process identifier;

searching the list items of the exclusive cache space unit table which is monopolized by the process according to the simplified process identification to obtain the number of the exclusive cache space units of the process;

the step of initializing and updating the process identification bit of the current exclusive cache space unit table entry to the process identification comprises:

and initializing and updating the process identification bit of the current exclusive cache space unit table entry into the simplified process identification.

6. The method for initializing exclusivity of cache space as claimed in claim 5, wherein said step of searching for a reduced process id based on said process id comprises:

and searching the simplified process identification from a process identification corresponding table according to the process identification, wherein the process identification corresponding table comprises a process identification bit for recording the process identification and a simplified process identification bit for recording the simplified process identification.

7. The method for initializing monopoly of cache space according to claim 6, wherein when the process identifier is not found in the process identifier corresponding table and a null entry exists in the process identifier corresponding table, a null entry is selected from the process identifier corresponding table to obtain a selected null entry, and the selected null entry is updated to establish a relationship between the process identifier and the simplified process identifier;

and recording the simplified process identification of the selected empty table entry.

8. The method for initializing exclusivity of a cache space as claimed in claim 7, further comprising:

and when the current exclusive cache space unit is initialized by exclusive or exclusive processes of the processes different from the process to which the instruction belongs, clearing the updated empty table entry of the process identification corresponding table.

9. The method for initializing exclusivity of a cache space according to any one of claims 1-8, further comprising:

and when the current exclusive cache space unit is in an exclusive initialization state by the process to which the current exclusive cache space unit belongs, if an address identification section which does not acquire the exclusive cache space unit exists in the instruction memory address identification, acquiring the address identification section which does not acquire the exclusive cache space unit, taking the address identification section which does not acquire the exclusive cache space unit as the current address identification section, and turning to the step of acquiring the current exclusive cache space unit corresponding to the current address identification section according to the instruction memory address identification.

10. The method according to any one of claims 1 to 8, wherein the step of obtaining the current exclusive cache space unit corresponding to the current address identifier segment according to the instruction memory address identifier comprises:

acquiring the allocated memory address identifier of the process according to the process identifier;

and when the instruction memory address identifier belongs to the allocated memory address identifier, acquiring a current exclusive cache space unit corresponding to the current address identifier section of the instruction memory address identifier according to the current address identifier section of the instruction memory address identifier.

11. An apparatus for initializing exclusivity of a cache space, comprising:

an exclusive initialization unit, adapted to perform exclusive initialization on the current exclusive cache space unit when the current exclusive cache space unit is in a non-exclusive state, so that the current exclusive cache space unit can be exclusively owned by the process to which the instruction belongs;

the exclusive initialization unit includes:

the table entry process identification bit initialization updating unit is suitable for initializing and updating the process identification bit of the current exclusive cache space unit table entry of the current exclusive cache space unit into the process identification;

the table entry exclusive state bit initialization updating unit is suitable for initializing and updating the exclusive state bit of the current exclusive cache space unit table entry into an exclusive initialization state;

and the second clearing unit is suitable for clearing the exclusive initialization of the exclusive cache space unit which finishes the exclusive initialization when the current exclusive cache space unit is exclusively initialized or exclusively initialized by a process which is different from the process of the instruction.

12. The apparatus for initializing exclusivity of the cache space as recited in claim 11, further comprising:

the current address identification section obtaining unit is suitable for obtaining the address identification section of the exclusive cache space unit which is not obtained when the address identification section of the exclusive cache space unit which is not obtained exists in the instruction memory address identification after the previous exclusive cache space unit is subjected to exclusive initialization, and sending the address identification section of the exclusive cache space unit which is not obtained as the current address identification section to the current exclusive cache space unit obtaining unit.

13. The apparatus for initializing exclusivity of the cache space as recited in claim 11, further comprising:

the unit for acquiring the number of the units applying for the exclusive cache space is suitable for acquiring the number of the units applying for the exclusive cache space of the instruction according to the instruction memory address identifier;

the process exclusive cache space unit quantity obtaining unit is suitable for obtaining the quantity of the exclusive cache space units of the process according to the process identification;

the current exclusive cache space unit obtaining unit is adapted to obtain the current exclusive cache space unit corresponding to the current address identification segment of the instruction memory address identification according to the current address identification segment of the instruction memory address identification when the sum of the number of the process exclusive cache space units and the number of the applied exclusive cache space units is less than or equal to the number of the allowed exclusive cache space units of the process.

14. The apparatus according to claim 13, wherein the unit for acquiring current exclusive cache space unit is adapted to end the exclusive initialization when a sum of the number of the process-owned cache space units and the number of the applied exclusive cache space units is greater than the number of the process-allowed exclusive cache space units.

15. The apparatus for initializing exclusively the cache space according to claim 14, wherein the unit for acquiring the number of units of the process-monopolized cache space comprises:

the simplified process identification obtaining unit is suitable for finding the simplified process identification according to the process identification;

the process monopolized quantity obtaining unit is suitable for searching the monopolized cache space unit table items monopolized by the process according to the simplified process identification to obtain the quantity of the process monopolized cache space units;

16. The apparatus for initializing exclusivity of the cache space as recited in claim 15, further comprising:

the simplified process identifier obtaining unit is adapted to obtain the simplified process identifier from a process identifier corresponding table according to the process identifier, where the process identifier corresponding table includes a process identifier bit for recording the process identifier and a simplified process identifier bit for recording the simplified process identifier.

17. The apparatus for initializing exclusivity of the cache space as recited in claim 15, further comprising:

and the selected empty table item updating unit is suitable for selecting an empty table item from the process identification corresponding table to obtain a selected empty table item and updating the selected empty table item so as to establish the relationship between the process identification and the simplified process identification and send the simplified process identification of the selected empty table item to the simplified process identification acquisition unit when the process identification is not found in the process identification corresponding table and the process identification corresponding table has an empty table item.

18. The apparatus for initializing exclusivity of the cache space as recited in claim 17, further comprising:

and the first clearing unit is suitable for clearing the empty table entry of the updated process identification corresponding table when the current exclusive cache space unit is initialized exclusively or exclusively by a process of a process different from the process of the instruction.

19. The apparatus for initializing exclusivity of a cache space of claim 12,

the current address identification segment obtaining unit is further adapted to, when the current exclusive cache space unit is in an exclusive initialization state by the process to which the current exclusive cache space unit belongs, obtain, if an address identification segment for which the exclusive cache space unit has not been obtained exists in the instruction memory address identification, the address identification segment for which the exclusive cache space unit has not been obtained, and send, as the current address identification segment, the address identification segment for which the exclusive cache space unit has not been obtained to the current exclusive cache space unit obtaining unit.

20. The apparatus for initializing exclusivity of cache space as claimed in any one of claims 11-18, wherein said unit for acquiring a current exclusive cache space unit comprises:

and the conditional current exclusive cache space unit obtaining unit is suitable for obtaining the current exclusive cache space unit corresponding to the instruction memory address identifier according to the current address identifier section of the instruction memory address identifier when the instruction memory address identifier belongs to the allocated memory address identifier.

21. A central processing unit adapted to execute a program for implementing the exclusive initialization method of a cache space according to any one of claims 1 to 10.

22. A storage medium storing a program adapted to perform exclusive initialization of a cache space, so as to implement the exclusive initialization method of the cache space according to any one of claims 1 to 10.