CN115114192A

CN115114192A - Memory interface, functional core, many-core system and memory data access method

Info

Publication number: CN115114192A
Application number: CN202110309611.4A
Authority: CN
Inventors: 吴臻志; 丁瑞强
Original assignee: Beijing Lynxi Technology Co Ltd
Current assignee: Beijing Lynxi Technology Co Ltd
Priority date: 2021-03-23
Filing date: 2021-03-23
Publication date: 2022-09-27
Anticipated expiration: 2041-03-23
Also published as: CN115114192B

Abstract

The application discloses a memory interface, a functional core, a many-core system and a storage data access method, and belongs to the technical field of computers. The storage data access method is applied to a storage interface, the storage interface is positioned in a first functional core in a many-core system, and the method comprises the following steps: receiving a first reading request, wherein the first reading request carries a target global address; responding to the first read request, when a target storage space indicated by the target global address is located in the first functional core, determining a first private address corresponding to the target global address according to a mapping relation between the global address and the private address, and transmitting first target data corresponding to the first private address in the target storage space. The method and the device can improve the operating efficiency of the many-core system.

Description

Memory interface, functional core, many-core system and memory data access method

Technical Field

The application belongs to the technical field of computers, and particularly relates to a memory interface, a functional core, a many-core system and a storage data access method.

Background

The many-core system has strong data processing capacity. The many-core system is provided with a plurality of functional cores. In the related art, when a plurality of functional cores need to access the same data, there is a problem of access delay, so that the operating efficiency of the many-core system is low.

Disclosure of Invention

An object of the embodiments of the present application is to provide a memory interface, a function core, a many-core system, and a storage data access method, which can solve the problem of low operating efficiency of the many-core system due to data delay in the storage data access method in the related art.

In order to solve the technical problem, the present application is implemented as follows:

in a first aspect, an embodiment of the present application provides a memory interface, where the memory interface is located in a first functional core in a many-core system, and the memory interface includes:

the target position resolver is used for determining a first private address corresponding to a target global address under the condition that a target storage space indicated by the target global address carried by a first reading request is located in a first functional core, so as to access first target data corresponding to the first private address in the target storage space based on the first private address;

the target location resolver stores a mapping relationship between the target global address and the first private address in advance, and the target storage space is located in the first functional core.

In a second aspect, an embodiment of the present application provides a functional core, where the functional core includes a memory and a memory interface connected to the memory, and the memory interface is the memory interface according to the first aspect.

In a third aspect, an embodiment of the present application provides a many-core system, where the many-core system includes a plurality of functional cores as described in the second aspect, and any two functional cores in the many-core system are communicatively connected.

In a fourth aspect, an embodiment of the present application provides a storage data access method, which is applied to the memory interface according to the first aspect, and the method includes:

receiving a first read request, wherein the first read request carries a target global address;

and responding to the first read request, when a target storage space indicated by the target global address is located in a first functional core, determining a first private address corresponding to the target global address according to a mapping relation between the global address and the private address, and transmitting first target data corresponding to the first private address in the target storage space.

In a fifth aspect, an embodiment of the present application provides a storage data access apparatus, which is applied to the memory interface according to the first aspect, and the apparatus includes:

a first receiving module, configured to receive a first read request, where the first read request carries a target global address;

and the first transmission module is used for responding to the first read request, determining a first private address corresponding to the target global address according to the mapping relation between the global address and the private address when the target storage space indicated by the target global address is located in the first functional core, and transmitting first target data corresponding to the first private address in the target storage space.

In a sixth aspect, the present application provides an electronic device, which includes a processor, a memory, and a program or instructions stored on the memory and executable on the processor, and when executed by the processor, the program or instructions implement the steps of the method according to the fourth aspect.

In a seventh aspect, the present application provides a readable storage medium, on which a program or instructions are stored, and when executed by a processor, the program or instructions implement the steps of the method according to the fourth aspect.

In an eighth aspect, embodiments of the present application provide a chip, where the chip includes a processor and a communication interface, where the communication interface is coupled to the processor, and the processor is configured to execute a program or instructions to implement the method according to the fourth aspect.

In the embodiment of the present application, a memory interface in a first functional core is configured to receive a first read request, where the first read request carries a target global address; and responding to the first reading request, when a target storage space indicated by the target global address is located in a first functional core, determining a first private address corresponding to the target global address according to a mapping relation between the global address and the private address, and transmitting first target data corresponding to the first private address in the target storage space. Therefore, the functional core in the many-core system can access the private storage space of another functional core according to the global address, and then different shared data can be stored in the private storage spaces of different functional cores in a scattered manner, so that the problems of long waiting time and uncertain waiting time when a plurality of functional cores access the global shared storage space respectively due to the fact that a large amount of shared data are stored in the global shared storage space are avoided, and the operating efficiency of the many-core system is improved.

Drawings

FIG. 1 is a flow chart of a method for accessing stored data according to an embodiment of the present disclosure;

fig. 2 is a schematic diagram of data interaction between a first functional core and a second functional core in a method for accessing stored data according to an embodiment of the present application;

fig. 3 is a schematic diagram of data interaction in a first functional core in a storage data access method according to an embodiment of the present application;

FIG. 4 is a schematic structural diagram of a memory interface provided in an embodiment of the present application;

FIG. 5 is a block diagram of a storage data access device according to an embodiment of the present application;

fig. 6 is a structural diagram of an electronic device according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The terms first, second and the like in the description and in the claims of the present application are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It will be appreciated that the data so used may be interchanged under appropriate circumstances such that embodiments of the application are capable of operation in sequences other than those illustrated or described herein, and that the terms "first," "second," etc. are generally used in a generic sense and do not limit the number of terms, e.g., a first term can be one or more than one. In addition, "and/or" in the specification and claims means at least one of connected objects, a character "/", and generally means that the former and latter related objects are in an "or" relationship.

The many-core system includes a plurality of functional cores, and if the plurality of functional cores in the many-core system need to access the same storage data, in the related art, the plurality of functional cores may acquire the same shared data by adopting the following two ways:

in the first mode, a global shared storage space is set, the global shared storage space is set outside a functional core and can be set outside a chip where the functional core is located, in an application, when the functional core needs to acquire target data from the global shared storage space, a read request is sent to the global shared storage space through a shared memory bus, and the target data is transmitted through the shared memory bus.

As can be seen from the above, in an application scenario where multiple computing units access the global shared memory space simultaneously, it is necessary to determine that one core obtains the usage right through contention arbitration, so that the one core that obtains the usage right obtains the storage data from the global shared memory space through the shared memory bus, and other cores that do not obtain the usage right need to continue waiting, which results in a long time required for the cores to access the global shared memory space. In addition, data in the global shared storage space needs to be transmitted to the functional core through the shared memory bus, and the data delay time is not fixed or even unpredictable, so that the shared memory bus is easily congested, and the operating efficiency of the many-core system is obviously reduced.

In the second mode, the shared data is respectively copied to the private storage space of each functional core that needs to use the shared data, and since the private storage space is only used by the functional core, the external functional core cannot access the private spaces of other functional cores, and in implementation, each functional core acquires the shared data through the private storage space of the functional core.

In this embodiment, when an algorithm (such as a large neural network) with shared data is run, the shared part needs to be copied into the private memory of each functional core, which wastes resources. In addition, the private memory cannot arrange large arrays or share data, and the application range of the many-core system is limited.

In order to solve the above technical problem, in the embodiments of the present application, the global address is converted into the corresponding private address, so that the external functional core can access the private memory space of another functional core through the global address. On one hand, shared data does not need to be copied into a private memory of each core, so that resource waste is reduced, and the application range of a many-core system is expanded; on the other hand, a global shared storage space is not additionally arranged outside the functional core, so that the operation efficiency of the many-core system is improved.

The stored data access method, the stored data access apparatus, the electronic device, and the readable storage medium provided in the embodiments of the present application are described in detail through specific embodiments and application scenarios thereof with reference to the accompanying drawings.

Referring to fig. 1, which is a flowchart illustrating a method for accessing stored data according to an embodiment of the present application, where the method for accessing stored data is applicable to a memory interface, and the memory interface is located in a first functional core in a many-core system, as shown in fig. 1, the method for accessing stored data may include the following steps:

step 101, receiving a first read request, wherein the first read request carries a target global address.

Step 102, in response to the first read request, when a target storage space indicated by the target global address is located in a first functional core, determining a first private address corresponding to the target global address according to a mapping relationship between the global address and the private address, and transmitting first target data corresponding to the first private address in the target storage space.

In implementation, the functional core may also be referred to as a "core" or "core", and the functional core is a minimum unit that can be independently scheduled and has complete computing power in the many-core system.

In some alternative embodiments, the private memory spaces in each functional core have the same private address, for example: the number of the private storage spaces of the first functional core is N, the number of the N storage space identifiers in the first functional core is 0-N-1, the number of the private storage spaces of the second functional core is N, and the number of the N storage space identifiers in the second functional core is 0-N-1.

The above global address is unique in the many-core system, and can point to a target private storage space in the many-core system, which is located in a target functional core, for example: the global address is a combination of a core identifier of the first functional core and a storage space identifier of a target storage space in the first functional core. In an implementation, the global address may be a starting storage address of the first target data, and the first read request may further include a first length of the first target data. At this time, the above-mentioned transmitting the first target data corresponding to the first private address in the target storage space may be understood as: and transmitting the data with the first length in the first functional core, which comprises the starting address and the following starting address, to a requester of the first read request by taking the first private address corresponding to the global address as the starting address.

As an optional implementation manner, the first read request includes at least one of the following:

a read request sent by a first data path of the first functional core;

a reading request sent by the second functional core;

wherein the second functional core is a functional core in the many-core system that is different from the first functional core.

The second functional core may be understood as any functional core in the many-core system except the first functional core, that is, a functional core outside the first functional core, and the number of the second functional cores may be one or more.

The above-mentioned read request sent by the first data path of the first functional core may be understood as: the first functional core accesses data stored within the first functional core using the global address.

It should be noted that, in an actual application, the first functional core may also directly use the private address to perform private access on the data stored in the first functional core, which is not limited herein.

The read request sent by the second functional core may be understood as: the external functional core performs global access to the data stored in the first functional core using the global address.

In an implementation, the same memory space within the first functional core may respond to only one of global access and private access at the same time, for example: the memory space may be switched by mode switching at a target in a first mode of operation (which may also be referred to as "global mode") and/or in a second mode of operation (which may also be referred to as "private mode"). In the first working mode (which may also be referred to as "global mode"), the global address in the received access request is converted into a private address through a memory interface in the first functional core, so as to access the data in the target storage space based on the private address (that is, in this working mode, only the global access to the target storage space is responded to, and the private access can be denied); in the second operating mode (which may also be referred to as "private mode"), data in the target memory space is accessed based on the private address in the received access request through the memory interface in the first functional core (i.e., in this operating mode, only private access to the target memory space is responded to, and a response may be denied for global access).

In addition, the private storage space (i.e., memory slice) of the first functional core may include one or more private storage spaces, where in the case that there are multiple private storage spaces (i.e., memory slices) of the first functional core, a part of the private storage space may operate in a private mode, and another part of the private storage space may operate in a global mode, where the private storage space in the private mode is only accessible to the first functional core, and the private storage space in the global mode is only accessible to the second functional core.

In this embodiment, both the first functional core and the second functional core in the many-core system may access data in the first functional core by using a global address.

As an alternative embodiment, the first read request and the first target data are transmitted via a network on chip or a bus on chip.

In an implementation, the first functional core and the second functional core are connected by the network on chip or a bus on chip.

For example: as shown in fig. 2, a request core 21 (i.e., a second functional core) and a destination core 22 (i.e., a first functional core) establish a communication connection through an on-chip/inter-chip network 23, where the request core 21 specifically includes: the first private memory 211, the first dual mode memory interface 212, the first route 213, and the data path 214, and the destination core 22 specifically includes: a second private memory 221, a second dual mode memory interface 222, and a second route 223. When the requesting core 21 needs to read the target data stored in the private memory 224 of the destination core 22, the data path 214 in the requesting core 21 sends a read request to the on-chip/inter-chip network 23 through the second dual-mode memory interface 222 and the first route 213, where the read request carries the core identifier of the requesting core 21 and the global address of the requested read data, the destination core 22 receives the read request from the on-chip/inter-chip network 23 through the second route 223, and when the second dual-mode memory interface 222 recognizes that the core identifier in the read request is not consistent with the core identifier of the destination core 22, the global address in the read request is converted into a private address, and the target data stored in the private address in the second private memory 221 is transmitted to the on-chip/inter-chip network 23 through the second route 223, so that the requesting core 21 obtains the target data from the on-chip/inter-chip network 23 through the first route 213, thereby realizing that the requesting core 21 acquires the target data from the private memory of the destination core 22.

It should be noted that, as shown in the embodiment shown in fig. 2, the arrow direction indicates the transmission direction of the signaling or the target data in the process that the requesting core 21 acquires the target data from the private memory 224 of the destination core 22.

In this embodiment, the request signaling and the data packet between the first functional cores are transmitted through the network on chip or the bus on chip, so that the waiting time can be reduced when a plurality of second functional cores access the private memory of the first functional core at the same time.

Of course, in a specific implementation, the first functional core and the second functional core may also be connected through other networks, for example: a short-range communication network, etc., and is not particularly limited herein.

In addition, in an optional implementation manner, in a case that the number of the second functional cores is multiple, that is, multiple external functional cores respectively access the private storage space of the first functional core, the first functional core may further respond to the read requests of the multiple second functional cores one by one.

As an optional implementation, the method further comprises:

and storing the mapping relation between the global address and the private address.

In an implementation, the mapping relationship between the global address and the private address may be: and in operation, inquiring the private address corresponding to the global address in the mapping table. Of course, it may also be a method of pre-storing the conversion relationship between the private address and the global address, so as to dynamically convert the global address into the corresponding private address in the running process.

Of course, the mapping relationship between the global address and the private address may further include: and determining a mapping relation according to the conversion relation between the global address and the private address.

As an optional implementation manner, the storing the mapping relationship between the global address and the private address includes:

under the condition that the many-core system comprises S chips, indicating a target function core where a corresponding private address is located and a target chip where the target function core is located based on each global address, and storing the mapping relation according to the global address corresponding to each private address;

alternatively, the first and second liquid crystal display panels may be,

and under the condition that the many-core system comprises 1 chip and the chips comprise a functional core array arranged in J rows and P columns, storing the mapping relation according to the global address corresponding to each private address based on the target functional core where each global address refers to the corresponding private address and the position of the target functional core in the whole column of the functional core.

In an optional implementation manner, the indicating, based on each global address, a target function core where a corresponding private address is located and a target chip where the target function core is located, to store the mapping relationship according to the global address corresponding to each private address may be understood as: the mapping relation comprises a conversion relation between the global address and the private address, and the conversion relation is realized by the target function core where the private address is located and the target chip where the target function core is located, wherein the target function core corresponds to the global address. In other words, it can also be understood as: the global address carries a corresponding private address, an identifier of a functional core where the private address is located, and an identifier of a chip where the functional core is located.

For example: under the condition that the many-core system comprises S chips, the mapping relation between the global address and the private address is determined by adopting the following formula:

p＝(qV+c)×N+k

wherein p represents a global address, k represents a private address, c represents an identifier of a functional core corresponding to k, q represents an identifier of a chip on which the functional core corresponding to c is located, N represents a total number of the private addresses in the functional core corresponding to k, and V represents a total number of the functional cores in each chip.

Of course, in specific implementation, besides the mapping relationship between the global address and the private address is expressed by the above formula, the mapping relationship between the global address and the private address may also be expressed by combining and arranging the private address, the chip identifier and the functional core identifier to form the global address.

In another optional implementation manner, the storing the mapping relationship according to the global address corresponding to each private address based on that each global address refers to the target functional core where the corresponding private address is located and the position of the target functional core in the whole column of the functional core may be understood as: the global address carries the identification of the corresponding private address and the functional core where the private address is located, and the arrangement position of the functional core in the functional core array.

For example: in the case where the many-core system includes 1 chip and the chips include a functional core array arranged in J rows and P columns, the mapping relationship between the global address and the private address is determined using the following formula:

p＝(Px+y)×N+k

wherein p represents a global address, k represents a private address, x represents a row identifier of the functional core corresponding to k in the functional core array, y represents a column identifier of the functional core corresponding to k in the functional core array, and N represents a total number of private addresses in the functional core corresponding to k.

Of course, in the specific implementation, in addition to expressing the mapping relationship between the global address and the private address through the above formula, the mapping relationship between the global address and the private address may also be expressed in a manner of jointly composing the global address by combining and arranging the private address and the chip location.

In this embodiment, the preset address and the global address are associated through the chip identifier, the function core position, and the like, so that the global address and the private address can be mutually converted in the application according to the chip identifier, the function core position, and the like, and the process of determining the first private address corresponding to the target global address is simplified.

As an optional implementation, the method further comprises:

receiving a second read request sent by a first data path, wherein the first data path is located in the first functional core, and the second read request carries a second private address;

transmitting second target data corresponding to the second private address within the target storage space to the first data path in response to the second read request.

Wherein the first data path represents a data path within a first functional core, for example: a data path between the processor and the memory within the first functional core.

The difference between the second read request and the first read request is as follows: the first read request carries a global address, and the second read request carries a private address, that is, the first read request is a global access request, and the second read request is a private access request.

This embodiment is applied to: the first functional core reads an application scenario of data from the local private memory, and at this time, the first functional core directly sends a private address to the local private memory without sending a global address of the private address, and the second read request carries the identifier of the first functional core, so that the target storage space can know that the second read request is a local access request, and the private address is identified instead of being mistaken for the global address.

For example: as shown in fig. 3, the computing module in the first functional core 31 may send a read request to the private memory 313 of the first functional core through the dual-mode memory interface 312 via the data path 311, where the read request carries a private address of target data, so that the private memory 313 feeds back the target data stored in the private address to the computing module through the dual-mode memory interface 312 and the data path 311.

It should be noted that, as shown in the embodiment shown in fig. 3, the arrow direction indicates the transmission direction of the signaling or the target data in the process that the first functional core 31 acquires the target data from the private memory 313 of the functional core.

It should be noted that, in this embodiment, the first data path in the first functional core sends the second read request carrying the private address to the target storage space of the first functional core, so that an implementation process of reading data from the target storage space is the same as a process of reading data from the local private memory by the functional core in the prior art, and is not described in detail herein.

It should be noted that, in practical applications, the first functional core may include a plurality of memory chips, so that there may be a case where a part of the memory chips in the first functional core is accessed by the functional core, and another part of the memory chips is accessed by the external functional core. However, the same memory slice can only respond to one of the local access request and the global access request (i.e., the first read request) at the same time.

In an alternative embodiment, the memory of the functional core may be controlled to operate in the global mode or the private mode according to a control signal of the control logic.

Situation one

In the case that the memory of the functional core operates in the global mode, the memory can only be globally accessed by the external functional core, and the access of the functional core will be denied. In the global mode, a received read request carries a global address, the global address is recorded by a global address mapping table and is responsible for translating the global address to a private address, and finally the private address is adopted to access the memory.

It should be noted that, in the global mode, the memories of all the functional cores form a large-capacity logical memory, and when performing global access, it is not necessary to indicate which core of which chip the accessed memory is located in, and only a global address is needed to access the memory.

Situation two

In the case where the memory of the functional core operates in the private mode, the memory can be accessed only locally by the functional core, and the global access of the external functional core will be denied. In the private mode, the memory can only be accessed by the functional core, and therefore, the access delay is fixed and predictable.

In another optional implementation manner, whether a received read request carries a private address or a global address may be determined to determine whether the access request is a local access request inside the local function core or a global access request of an external function core, so as to determine what response is performed to the read request according to the determination.

Further, the working modes of the target storage space comprise a first working mode and a second working mode;

in the first working mode, the memory interface converts a global address in a received access request into a private address so as to access data in the target storage space based on the private address; in the second working mode, the memory interface accesses the data in the target memory space based on the private address in the received access request;

the method further comprises at least one of:

determining a working mode of the target storage space according to a control instruction;

determining the operating mode to be the first operating mode in response to the first read request;

determining the operating mode to be the second operating mode in response to the second read request.

In the first operating mode, the memory interface converts the global address in the received access request into a private address, so as to access the data in the target storage space based on the private address, which may be understood as: the first mode of operation may be a global mode, in which case the memory interface responds only to global accesses.

In addition, in the second operating mode, the accessing, by the memory interface, the data in the target storage space based on the private address in the received access request may be understood as: the second mode of operation may be a private mode, in which case the memory interface responds only to private accesses.

In an optional embodiment, the determining the operation mode of the target storage space according to the control instruction may be implemented as follows: the working mode of the target storage space is determined according to the indication of the preset control instruction and is not influenced by the received access request.

In this embodiment, the working mode of the target storage space may be adjusted by a preset control instruction, so as to control whether data in the target storage space can be accessed only by the functional core or by other functional cores.

In another optional implementation, the determining, in response to the first read request, that the operating mode is the first operating mode; and in response to the second read request, determining that the operating mode is the second operating mode, which may be understood as: the memory interface determines whether to operate in the first mode of operation or the second mode of operation based on whether the received access request is a private request or a global request.

Specifically, the above memory interface refusing the second read request to the target memory space until the first read request completes the response may be understood as: in the first working mode, only the global access of the target storage space is responded, and after all the global access responses are completed, the second working mode can be switched to, so that in the second working mode, the private access of the target storage space is responded; or, after all the global access responses are completed, the private access of the target storage space can be responded directly without mode switching.

Accordingly, the above memory interface rejects the first read request to the target memory space until the second read request completes the response, which may also be understood as: in the second working mode, only the private access of the target storage space is responded, and after all the private access responses are completed, the first working mode can be switched to respond to the global access of the target storage space in the first working mode; or, after all the private access responses are completed, the global access of the target storage space can be responded directly without mode switching.

Further, in a specific implementation, when the memory interface receives the first read request and switches to the first operating mode, and then receives the second read request, the memory interface may respond to each first read request, and the second read request received in the period may be stored in the to-be-responded list, so that after the memory interface finishes responding to all the first read requests, the memory interface may switch to the second operating mode to respond to the second read request in the to-be-responded list.

Correspondingly, when the memory interface receives the second read requests and switches to the second operating mode, and then receives the first read requests, the memory interface may respond to each second read request, and the first read requests received during the period may be stored in the to-be-responded list, so that after the memory interface finishes responding to all the second read requests, the memory interface may switch to the first operating mode to respond to the first read requests in the to-be-responded list.

In this embodiment, the working mode of the target storage space may be determined according to the type of the received read request, so that the working mode of the target storage space is conveniently switched according to different read requests, so that the target storage space is matched with the received read request.

It should be noted that, if the target storage space receives both the local access request and the global access request at the same time, it is also possible to preferentially select one of the local access request core and the global access request to respond to through arbitration.

As an alternative embodiment, in the case that the difference between the receiving time of the first read request and the receiving time of the second read request is smaller than a preset time, the response to at least one of the first read request and the second read request is determined by arbitration or a preset priority.

The preset time may be any time length such as 0.1s (second) and 1 second, and is not particularly limited herein.

The determining to respond to at least one of the first read request and the second read request according to the preset time may be: under the condition that the priority of the first read request is set to be higher than that of the second read request in advance, the first read request is responded preferentially, the second read request can be rejected, or the second read request is responded after the first read request is responded; and under the condition that the priority of the second read request is set to be higher than that of the first read request in advance, the second read request is responded preferentially, the first read request can be rejected, or the first read request is responded after the second read request is responded.

As an optional implementation manner, the first read request is a read request sent by a first data path of the first functional core, and the method further includes:

when it is determined that the storage space indicated by the target global address is located in a second functional core, sending the first read request to the second functional core, wherein the second functional core is a functional core different from the first functional core in the many-core system;

and receiving third target data returned by the second functional core, and transmitting the third target data to the first data path.

In implementation, the present functional core may also access data stored in other functional cores, at this time, a data path in the present functional core sends a read request for requesting access to the data stored in the other functional cores, and the present functional core matches the functional core identifier carried in the read request with the identifier of the present functional core, and when the read request is not matched with the functional core identifier, it may be determined that the data requested by the read request is stored in the other functional cores, so as to determine that the address carried in the read request is a global address, and send the read request to a second functional core corresponding to the functional core identifier carried in the read request.

In addition, when the second functional core receives the first read request, the global address carried in the first read request is converted to obtain a private address, the storage space where the third target data is located is accessed based on the private address, and the third target data stored in the storage space is transmitted to the first functional core according to an access result.

In this embodiment, in addition to the data stored in the first functional core being accessible by the first functional core and the other functional cores, the first functional core may also obtain third target data stored in the second functional core based on the global address.

The following takes the example that the target storage space includes a storage interface (which may also be referred to as a "dual-mode memory interface") for switching the target storage space between a private mode and a global mode, and the response process of the local access request and the global access request is exemplified:

in this embodiment, the many-core system includes: a first functional core, a second functional core, and a network on chip 50 connecting the first functional core and the second functional core.

As shown in fig. 4, the first functional core includes: a data path 41, a memory 42, a routing module 43, and a dual-mode memory interface 44, where the routing module 43 is connected to the on-chip network 50; the dual mode memory interface 44 includes a destination location parser 441, a mode switch 442, an address mapping table storage module 443, a request signaling packetizer 444, a request signaling depacketizer 445, a data packetizer 446, and a data depacketizer 447.

Specifically, the destination location parser 441 is connected to the data path 41, the memory 42 mode switch 442, the address mapping table storage module 443, the request signaling packer 444, the request signaling unpacker 445, the data packer 446, and the data unpacker 447, respectively, and the mode switch 442, the address mapping table storage module 443, the request signaling packer 444, the request signaling unpacker 445, the data packer 446, and the data unpacker 447 are connected to the routing module 43, respectively.

It should be noted that the structure of the second functional core may be the same as that of the first functional core, and is not described herein again. In addition, the arrow direction in the embodiment shown in fig. 4 represents the transmission direction of the signaling or target data in the process that the memory 42 of the first functional core is accessed locally or globally.

In one case, if the dual-mode memory interface 44 is in the private mode, the destination location resolver 441 directly accesses the memory 42 according to the private address provided by the data generating unit in the data path 41, that is, the second read request carries the private address of the destination data, and the memory 42 directly outputs the returned data packet of the destination data to the data path 41.

In another case, if the dual-mode memory interface 44 is in the global mode, when the data path 41 sends a read request to the target location resolver 441, the target location resolver 441 is configured to determine, according to the address mapping table stored in the address mapping table storage module 443, whether a destination address in the read request sent by the data path 41 is located in the local function core or in another function core located outside, so as to determine whether the read request needs to be generated as a local access request or a global access request.

If the destination address in the read request is located in the local functional core, it is determined that the read request is a local access request, and the memory 42 is directly accessed according to the private address in the local access request.

In addition, if the destination address in the read request is located in another external functional core, then the read request is determined to be a global access request, at this time, the target location parser 441 sends the request location in the global access request to the request signaling packetizer 444, the request signaling packetizer 444 packetizes a global access request signaling packet and sends the global access request signaling packet to the routing module 43, and the routing module 43 sends the global access request signaling packet received from the request signaling packetizer 444 to the network-on-chip 50 to send the global access request signaling packet to a storage location of data to be read through the network-on-chip 50, so that when the target functional core where the storage location is located returns a data packet in response to the global access request signaling packet, the routing module 43 receives the return data packet from the network-on-chip 50 and unpacks the data packet by the data unpacker 447, to obtain target data (i.e. data that needs to be read by the functional core), the target location analyzer 441 further analyzes the target data, and sends the target data to the memory 42 or the data path 41 according to the analyzed information.

Meanwhile, the routing module 43 is also responsible for receiving a global access request signaling packet sent from the external functional core to the local functional core from the network on chip 50, and unpacking the global access request signaling packet by the request signaling unpacker 445 to obtain information such as a global address and a data length of the global access request signaling packet. And sends this information to the target location parser 441. Thus, the destination location parser 441 will translate the global address of the global access request into a private address to access the memory 42 through the private address, and return the access result (i.e. destination data) of the memory 42 to the data packer 446, so as to send the destination data to the network on chip 50 through the routing module 43 after the destination data is packed into a data packet by the data packer 446, at this time, the requester of the destination data will receive the data packet of the destination data from the network on chip 50, specifically, in the requester of the destination data, the data packet received by the routing module will be unpacked in the data unpacker, and the relevant data packet will be sent to the destination location parser, the destination location parser will parse the data packet information to send the data in the data packet to the memory or the data path according to the parsed information, the processing procedure of the requester of the destination data on the received destination data is the same as the processing procedure of the function core after receiving the data packet, and will not be described in detail herein.

In implementation, the format of the request signaling packet may be as shown in table 1 below:

TABLE 1

Wherein the signaling identifier is used to distinguish between different signaling; the target function core address is used for indicating the address of the function core where the memory storing the data to be accessed is located; the data starting global address represents a starting global address of the data to be accessed, and the starting global address plus the data length can represent an ending global address of the data to be accessed; when the storage space where the data to be accessed is located has multiple functional cores to access simultaneously, the target location analyzer may perform arbitration based on the priority to determine to respond to an access request signaling with the highest priority; additional information may be added through the additional information field described above.

It should be noted that the arrangement positions of the sub signals in the request signaling packet may be exchanged, and the arrangement positions may further include other sub information besides the signaling identifier, the target function core address, the data starting global address, the priority, and the additional information field, which is not exhaustive here.

In addition, in implementation, the format of the data packet may be as shown in table 2 below:

TABLE 2

Wherein, the data packet identifier is used for distinguishing different data packets; the data body represents specific data (namely data to be accessed) in the data packet; in addition, the specific meanings of the target function core address, the data start global address, the data length, and the additional information field may refer to the specific meanings of the target function core address, the data start global address, the data length, and the additional information field in the request signaling packet format shown in table 1, respectively, and are not described herein again.

In the related art, when a set of weights is used for a plurality of pictures, the plurality of pictures are respectively input to a plurality of functional cores to be respectively processed, and in application, because the set of weights needs to be used for the plurality of functional cores, and the private memory of each functional core can only be accessed by the functional core, all the functional cores needing to use the weights exist in the set of weights, so that the pictures can be processed layer by layer.

In the embodiment of the present application, the set of weights may be stored in only 1 or a few functional cores (for example, only each weight value in the set of weights is respectively stored in a functional core that needs to use the weight value, and the functional core does not need to store the whole set of weights), and when one functional core needs to use an unstored weight value, the functional core may obtain the weight value from other functional cores that store the weight value in a global access manner.

As can be seen from the above, by the stored data access method provided in the embodiment of the present application, when an algorithm (such as a large neural network) with shared data is executed, the shared data does not need to be copied to the private memory of each functional core, so that resource waste can be reduced, the application range of a many-core system with a large array and shared data is wider, and a high-speed mode and a sparse mode can be simultaneously supported. In addition, different from the prior art that shared data needs to be transmitted through a shared memory central line, in the embodiment of the application, signaling and data of global access are transmitted through an on-chip network, an on-chip bus or an inter-chip network, so that the waiting time of signaling and data transmission can be reduced, and the operating efficiency of a many-core system can be improved.

In the embodiment of the application, a first functional core receives a first read request sent by a second functional core, wherein the first read request carries an identifier and a target global address of the second functional core; responding to the first read request, determining a first private address corresponding to the target global address, and transmitting first target data corresponding to the first private address in the target storage space to the second functional core; the first functional core stores a mapping relationship between the target global address and the first private address in advance, and a target storage space corresponding to the first private address is located in the first functional core. Therefore, the private storage space in the first functional core can be used as a shared storage space to be accessed by the second functional core, and different shared data can be dispersedly stored in the private storage spaces of different functional cores, so that the problems of long waiting time and uncertain waiting time when a plurality of functional cores access the global shared storage space respectively due to the fact that a large amount of shared data are stored in the global shared storage space are avoided, and the operating efficiency of the many-core system is improved.

It should be noted that the storage data access method provided by the embodiment of the present application may be applied to a storage interface, which may be a storage interface located in a first functional core in a many-core system, (which may also be referred to as a "dual-mode memory interface"). As shown in fig. 4, the memory interface 44 may include:

the target location resolver 441 is configured to, when a target storage space indicated by a target global address carried in the first read request is located in the first functional core, determine a first private address corresponding to the target global address, so as to access first target data corresponding to the first private address in the target storage space based on the first private address;

In a specific implementation, the memory interface 44 may further include:

a data unpacker 446, wherein if the first read request is sent by a second functional core, the data unpacker 446 is configured to analyze the first read request received from the second functional core to obtain the target global address carried by the first read request;

the destination location resolver 441 is connected to the data unpacker 446, and the destination location resolver 441 obtains the destination global address from the data unpacker 446.

In this embodiment, the first read request has the same meaning as the first read request in the embodiment of the method shown in fig. 1, and the mapping relationship between the global address and the private address is the same as the mapping relationship between the global address and the private address in the embodiment of the method shown in fig. 1, which is not described herein again.

Optionally, the target location parser 441 is further configured to parse the received second read request to obtain a second private address carried in the second read request, and access, based on the second private address, second target data corresponding to the second private address in the target storage space, where the second read request is sent by the first functional core.

Optionally, as shown in fig. 4, the memory interface further includes:

a mode switch 442, wherein the mode switch 442 is connected to the target location resolver 441;

the mode switcher 442 is used for controlling the target storage space to be in a first working mode and/or a second working mode;

in the first working mode, the target location resolver 441 converts a global address in the received access request into a private address to access data in the target storage space based on the private address;

in the second operation mode, the target location resolver 441 accesses data in the target storage space based on the private address in the received access request.

Optionally, when the received read request for the target storage space carries a global address, the mode switch 442 controls the target storage space to be in the first working mode;

in a case that a private address is carried in the read request for the target storage space, the mode switch 442 controls the target storage space to be in the second operating mode.

Optionally, the target location analyzer 441 is further configured to analyze a third read request sent by the data path in the first functional core, so as to obtain a request address carried by the third read request;

the memory interface 44 further includes:

and a signaling group packer 444, configured to, when the storage space indicated by the request address is located in a second functional core, generate a fourth read request based on the request address by the signaling group packer 444, and send the fourth read request to the second functional core through the first functional core, where a target global address carried in the fourth read request is a global address corresponding to the request address, and the second functional core is a functional core different from the first functional core in the many-core system.

The signaling group packer 444 may also be referred to as a "request signaling group packer".

The request address carried by the third read request may be an address generated by the data address generation unit in the data path in the first functional core according to the location where the data to be accessed is stored.

In addition, when the second functional core receives the fourth read request from the first functional core, the second functional core performs the same processing on the fourth read request as the processing performed on the first read request by the first functional core, which is not described herein again.

Optionally, as shown in fig. 4, the memory interface 44 further includes:

a storage unit 443 for storing an address mapping table, wherein the storage unit 443 is used for storing a mapping relationship between a global address and a private address.

In implementation, when the storage address (which is a private address) of the target data carried in the global access request issued by the local functional core is located in another functional core, the global address corresponding to the storage address of the target data may be determined based on the mapping relationship between the global address and the private address stored in the storage unit 443.

In addition, when the functional core receives an access request carrying a global address, the private address corresponding to the global address can be determined based on the mapping relationship between the global address and the private address stored in the storage unit 443, so that the target storage space in the functional core is accessed based on the private address.

Accordingly, as shown in fig. 4, the memory interface 44 further includes:

the signaling depacketizer 445 is configured to parse the received access request to obtain access information carried in the access request, for example: a global address or a private address where target data to be accessed is stored, and the like.

As shown in fig. 4, the signaling depacketizer 445 may also be referred to as a "request signaling depacketizer".

Optionally, as shown in fig. 4, the memory interface 44 further includes:

the data packetizer 447 is configured to packetize the data accessed by the access request for transmission to the requester of the access request.

Accordingly, as shown in fig. 4, the memory interface 44 further includes:

the data de-packetizer 446 is configured to parse the received data, and has a function corresponding to that of the data packetizer 447, so that the parsed data is easy for a user to read.

The memory interface provided in the embodiment of the present application can perform each process in the method embodiment shown in fig. 1, and can obtain the same beneficial effects, and is not described herein again to avoid repetition.

The embodiment of the present application further provides a functional core, where the functional core includes a memory and a memory interface connected to the memory, and the memory interface is a memory interface provided in the previous memory interface embodiment.

Optionally, the number of target storage spaces included in the functional core is multiple, and the memory interface is connected to the multiple target storage spaces respectively;

the memory interface is used for respectively controlling the working mode of each target storage space, and the working modes of different target storage spaces in the functional core are not completely the same.

The target storage space in the functional core provided in the embodiment of the present application can be in different working modes to be privately accessed by the functional core, or globally accessed by an external functional core, and can also perform each process in the method embodiment shown in fig. 1, and can obtain the same beneficial effect, and details are not repeated here to avoid repetition.

An embodiment of the present application further provides a many-core system, where the many-core system includes a plurality of functional cores provided in the above embodiment, and any two functional cores in the many-core system are in communication connection.

Optionally, any two functional cores in the many-core system are connected through a network on chip or a bus on chip.

The many-core system provided in the embodiment of the present application does not need to store shared data in each functional core, and also does not need to set an independent shared storage space, and can also perform each process in the method embodiment shown in fig. 1, and can obtain the same beneficial effect, and in order to avoid repetition, details are not repeated here.

It should be noted that, in the stored data access method provided in the embodiment of the present application, the execution main body may be a stored data access device, or a control module in the stored data access device, which is used for executing the stored data access method. In the embodiment of the present application, a method for executing load and store data access by a store data access device is taken as an example, and the store data access device provided in the embodiment of the present application is described.

Referring to fig. 5, which is a structural diagram of a storage data access apparatus provided in an embodiment of the present application, where the storage data access apparatus 500 is applied to any one of the memory interfaces provided in the embodiment of the present application, as shown in fig. 5, the storage data access apparatus 500 includes:

a first receiving module 501, configured to receive a first read request, where the first read request carries a target global address;

a first transmission module 502, configured to, in response to the first read request, when a target storage space indicated by the target global address is located in a first functional core, determine, according to a mapping relationship between a global address and a private address, a first private address corresponding to the target global address, and transmit first target data corresponding to the first private address in the target storage space.

Optionally, the first read request includes at least one of:

a read request sent by a first data path of the first functional core;

a read request sent by the second functional core;

Optionally, the storage data access apparatus 500 further includes:

a second receiving module, configured to receive a second read request sent by a first data path, where the first data path is located in the first functional core, and the second read request carries a second private address;

a second transmission module, configured to transmit, to the first data path, second target data in the target storage space corresponding to the second private address in response to the second read request.

Optionally, the first read request is a read request sent by the first data path of the first functional core, and the apparatus 500 for accessing storage data further includes:

a sending module, configured to send the first read request to a second functional core when it is determined that a storage space indicated by the target global address is located in the second functional core, where the second functional core is a functional core different from the first functional core in the many-core system;

and the receiving module is used for receiving third target data returned by the second functional core and transmitting the third target data to the first data path.

Optionally, the storage data access apparatus 500 further includes:

and the storage module is used for storing the mapping relation between the global address and the private address.

Optionally, the storage module is specifically configured to:

alternatively, the first and second electrodes may be,

Optionally, the working modes of the target storage space include a first working mode and a second working mode;

in the first working mode, the memory interface converts a global address in the received access request into a private address so as to access data in the target storage space based on the private address; in the second working mode, the memory interface accesses the data in the target memory space based on the private address in the received access request;

storage data access device 500 further includes at least one of:

the first determining module is used for determining the working mode of the target storage space according to the control instruction;

a second determining module, configured to determine, in response to the first read request, that the operating mode is the first operating mode;

a third determining module, configured to determine, in response to the second read request, that the operating mode is the second operating mode.

Optionally, in a case that a difference between receiving times of the first read request and the second read request is smaller than a preset time, determining to respond to at least one of the first read request and the second read request by arbitration or a preset priority.

Optionally, the first read request and the first target data are transmitted through a network on chip or a bus on chip.

The storage data access device 500 provided in the embodiment of the present application can perform each process performed by the memory interface in the embodiment of the method shown in fig. 1, can improve the operating efficiency of the many-core system and save storage resources, has the same beneficial effects as the embodiment of the method shown in fig. 1, and is not described herein again to avoid repetition.

The storage data access device in the embodiment of the present application may be a device, and may also be a component, an integrated circuit, or a chip in a terminal. The device can be mobile electronic equipment or non-mobile electronic equipment. For example, the mobile electronic device may be a mobile phone, a tablet computer, a notebook computer, a palm top computer, a vehicle-mounted electronic device, a wearable device, an ultra-mobile personal computer (UMPC), a netbook or a Personal Digital Assistant (PDA), and the like, and the non-mobile electronic device may be a Personal Computer (PC), a teller machine, a self-service machine, and the like, and the embodiment of the present application is not particularly limited.

The stored data access device provided in the embodiment of the present application can implement each process implemented by the method embodiment shown in fig. 1, and is not described here again to avoid repetition.

Optionally, as shown in fig. 6, an electronic device 600 is further provided in the embodiment of the present application, and includes a processor 601, a memory 602, and a program or an instruction that is stored in the memory 602 and is executable on the processor 601, where the program or the instruction is executed by the processor 601 to implement each process of the foregoing stored data access method embodiment, and can achieve the same technical effect, and is not described again here to avoid repetition.

It should be noted that the electronic devices in the embodiments of the present application include the mobile electronic devices and the non-mobile electronic devices described above.

The embodiment of the present application further provides a readable storage medium, where a program or an instruction is stored on the readable storage medium, and when the program or the instruction is executed by a processor, the program or the instruction implements each process of the foregoing storage data access method embodiment, and can achieve the same technical effect, and in order to avoid repetition, details are not repeated here.

The processor is the processor in the electronic device described in the above embodiment. The readable storage medium includes a computer readable storage medium, such as a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and so on.

The embodiment of the present application further provides a chip, where the chip includes a processor and a communication interface, the communication interface is coupled to the processor, and the processor is configured to execute a program or an instruction to implement each process of the foregoing stored data access method embodiment, and can achieve the same technical effect, and in order to avoid repetition, the description is omitted here.

It should be understood that the chips mentioned in the embodiments of the present application may also be referred to as system-on-chip, system-on-chip or system-on-chip, etc.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. Further, it should be noted that the scope of the methods and apparatus of the embodiments of the present application is not limited to performing the functions in the order illustrated or discussed, but may include performing the functions in a substantially simultaneous manner or in a reverse order based on the functions involved, e.g., the methods described may be performed in an order different than that described, and various steps may be added, omitted, or combined. In addition, features described with reference to certain examples may be combined in other examples.

Through the description of the foregoing embodiments, it is clear to those skilled in the art that the method of the foregoing embodiments may be implemented by software plus a necessary general hardware platform, and certainly may also be implemented by hardware, but in many cases, the former is a better implementation. Based on such understanding, the technical solutions of the present application or portions thereof that contribute to the prior art may be embodied in the form of a software product, which is stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal (which may be a mobile phone, a computer, a server, an air conditioner, or a network device) to execute the method according to the embodiments of the present application.

While the present embodiments have been described with reference to the accompanying drawings, it is to be understood that the invention is not limited to the precise embodiments described above, which are meant to be illustrative and not restrictive, and that various changes may be made therein by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A memory interface for use in a many-core system, the memory interface located within a first functional core of the many-core system, the memory interface comprising:

the target position resolver stores a mapping relation between the target global address and the first private address in advance.

2. The memory interface of claim 1, wherein the target location parser is further configured to parse a received second read request to obtain a second private address carried in the second read request, and access second target data corresponding to the second private address in the target storage space based on the second private address, where the second read request is sent by the first functional core.

3. A functional core, characterized in that the functional core comprises a memory and a memory interface connected to the memory, the memory interface being a memory interface according to claim 1 or 2.

4. A many-core system, wherein the many-core system comprises a plurality of functional cores as recited in claim 3, and wherein any two functional cores in the many-core system are communicatively coupled.

5. A method of accessing stored data, applied to a memory interface according to claim 1 or 2, the method comprising:

6. The method of claim 5, wherein the first read request comprises at least one of:

a read request sent by a first data path of the first functional core;

a reading request sent by the second functional core;

7. The method of claim 5, further comprising:

8. A storage data access apparatus, applied to the memory interface according to claim 1 or 2, the apparatus comprising:

9. An electronic device comprising a processor, a memory and a program or instructions stored on the memory and executable on the processor, the program or instructions when executed by the processor implementing the steps of the method of stored data access according to any one of claims 5 to 7.

10. A readable storage medium, on which a program or instructions are stored, which program or instructions, when executed by a processor, carry out the steps of the storage data access method according to any one of claims 5-7.