CN105676727B - A kind of engine fuel supply system control sequential storage and read method - Google Patents
A kind of engine fuel supply system control sequential storage and read method Download PDFInfo
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- CN105676727B CN105676727B CN201610015871.XA CN201610015871A CN105676727B CN 105676727 B CN105676727 B CN 105676727B CN 201610015871 A CN201610015871 A CN 201610015871A CN 105676727 B CN105676727 B CN 105676727B
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Classifications
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
-
- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F02—COMBUSTION ENGINES; HOT-GAS OR COMBUSTION-PRODUCT ENGINE PLANTS
- F02D—CONTROLLING COMBUSTION ENGINES
- F02D41/00—Electrical control of supply of combustible mixture or its constituents
- F02D41/24—Electrical control of supply of combustible mixture or its constituents characterised by the use of digital means
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/23—Pc programming
- G05B2219/23245—Block, buffer the inputs when executing critical process, read them when finished, for a finite state machine
Abstract
The present invention relates to a kind of storage of engine fuel supply system control sequential and read method, stored using flash storage/reading speed is fast, the processing speed of the digital processing units such as FPGA, DSP is fast and the features such as executive capability is strong, three cooperates, in storage/reading process of sequential, use handshake mechanism and Hash checking algorithms, by control sequential storage to/read out flash storage, the inventive method is fast compared with conventional method storage/reading speed, while has higher data storage/reading reliability compared with commonsense method.The present invention can be different according to the actual operating mode of engine fuel oil system, and sequential is carried out into fragmented storage, multigroup sequential can be stored again in each section of sequential.When engine fuel supply system works, performed according to sequential corresponding to the selection of its actual state, it is possessed wide operating mode ability to work.
Description
Technical field
The invention belongs to field of data storage, for engine fuel supply system, more particularly to a kind of engine fuel
Supply system control sequential stores and read method.
Background technology
Engine fuel supply system is a multivariable, time-varying, nonlinear complication system, its control process seriously according to
The timing information that bad designer empirically sets.
The time series data of early stage is stored with mechanical type, but its preservation form is single, and storing process is complicated, and can only store
Simple sequential.With the appearance of magnetic storage technology and optical storage technology, the preservation form of sequential has obtained great extension, but
It is for the speed of processor, its access time is longer, and the mechanical part of memory inside is easier to break down, and easily
Influenceed by engine mechanical oscillation.Along with the development of microelectric technique, there is semiconductor technology storage.Semiconductor storage
Device is not readily susceptible to engine mechanical oscillation and its shifting almost without abrasion, movable part useless during reading
Dynamic influence.
As computer technology improves constantly, the continuous development of control theory, engine fuel supply system processing speed
Increasingly faster, this is required on the basis of the storage of sequential reliability is ensured, the time for shorten sequential storage as far as possible, reading.
At present, the sequential storage method used in engine fuel supply system is in space availability ratio, storage/reading speed
Upper Shortcomings, it is impossible to meet the high-speed cruising of system processor.And sequential storage method security is not high, in storage/reading
During easily by external interference, in fact it could happen that the phenomenon of storage/read error.
The content of the invention
Technical problems to be solved
In order to avoid the shortcomings of the prior art, the present invention proposes that a kind of engine fuel supply system control sequential is deposited
Storage and read method.
Technical scheme
The present invention is applied in the digital electronic controller (DEEC) being made up of digit chip for main devices.In DEEC
In embedding fpga chip, dual-circulation linked list is built with, user is just stored in this after the timing information write is sent into DEEC
In dual-circulation linked list.The timing information being stored in dual-circulation linked list is ephemeral data, for ensure system electrification after can be again
Timing information is performed, timing information need to be stored in flash storage.
A kind of engine fuel supply system control sequential storage method, it is characterised in that step is as follows：
Step 1：When DEEC needs to store sequential, FPGA sends the set signal of storage sequential to DSP, and DSP is received
After the signal, Flash is formatted, and correlated variables initialization；
Step 2：DSP is sent to FPGA stores ready set signal, and FPGA receives the signal, completes FPGA with DSP
Between store sequential first time shake hands；
Step 3：FPGA counts the number of sequential node in each sequential group, then by sequential version and the node of each sequential group
Number packages, and a Flash head node for representing sequential version and each sequential group number of network nodes is formed, then by head node
Stored successively in Flash with the node in each sequential group；
The FPGA and DSP cooperates a node storage is as follows to the process in Flash：
Step a：FPGA sends the request signal for needing data storage to DSP, will be corresponding after DSP receives request signal
The address that FPGA writes data is emptied, and sends the return signal for receiving data storage request after emptying to FPGA at once,
Shaking hands between completion FPGA and DSP；
Step b：After FPGA receives DSP return signal, this length for writing data is sent to.The present invention is to once
Write-in DSP data length is defined, and when needing the data length of storage node to be more than limit value, is divided into repeatedly to DSP
Write-in, the data of limit value length are once at most write to DSP, until by all data write-in DSP in the node；Work as storage
When the data length of node is less than setting value, once it is written into DSP；
Step c：FPGA writes the data for needing storage node in DSP, and when entering row write data, FPGA will need every time
The data of storage carry out ELF Hash summations, and ELF Hash summing values are connected on behind time series data and are together sent to DSP；
Step d：After data are sent, FPGA is sent completely to DSP and sends data manipulation set signal, and DSP is received
After the signal, the data length of this time write-in is read from setting address, and read FPGA transmissions from corresponding address according to length
Data, and ELF Hash summations are carried out to it, and compared with the ELF Hash summing values that FPGA is sended over；
If two hash values are the same, the marking signal for receiving correct data is sent to FPGA, and this is read
Data Cun Chudao Flash Page in, and whether the real-time judge Flash Page expires page, writes data if full page
Enter in next Page；Continue storage if less than page and arrive the Page, until its full page；After FPGA reads the signal, terminate
This time data storage, FPGA complete shaking hands with DSP.If the data in the node do not store completely, from step at the beginning after
Continue the process, until all data in the node are all stored and finished；If all storage finishes the node data, terminate this
The storage of node, the storage of next node is carried out, until all sequential nodes are all stored and finished；
If two hash values are different, DSP empties the data received, and resends to FPGA requests and this time store
Data, FPGA receive repeating transmission request after, restart from step a, resend this data.
Step 4：After PFGA stores all sequential nodes, the reset signal of storage sequential is sent to DSP, DSP connects
After receiving reset signal, by the invalid bit clear in Flash current Page, and to FPGA transmission timings complete storage mark
Signal, after FPGA receives the signal, complete to shake hands with DSP last time, terminate whole storing process.
It is a kind of with above-mentioned corresponding engine fuel supply system control sequential read method, it is characterised in that step is such as
Under：
Step 1：When DEEC needs to read sequential, FPGA sends the set signal for reading sequential to DSP, and DSP is received
After the set signal for reading sequential, prepare sequential read work；
Step 2：After ready, DSP sends to FPGA and reads ready set signal, and FPGA receives the signal, complete
Shaken hands into FPGA with DSP first time；
Step 3：Then according to the Flash head node length of definition, head node is read from Flash.Then head is parsed
Node, obtain the version of sequential and the number of sequential node in each sequential group；, will according to the number of sequential node in each sequential group
Each node in each sequential group is read from Flash successively；
The idiographic flow that the FPGA and DSP collaborative works read head node and sequential node from Flash is as follows：
Step a：FPGA writes the length for needing to read data to DSP first, and the present invention enters to the data length once read
Row limits, and when the node data length for needing to read is more than setting value, is divided into multiple reading, once from Flash at most only
The data of limit value length are read, until all data in the node are all read in FPGA；When the data for reading node
When length is less than or equal to setting value, once complete to read；
Step b：FPGA sends to DSP and reads data request signal, after DSP receives request signal, according to this needs
The data length of reading reads the data in Flash Page, and writes data on the address of agreement.Entering row write data
Meanwhile the data taken out from storage are carried out ELF Hash summations by DSP, and ELF Hash summing values are write on appropriate address
FPGA is sent to, when DSP reads data from Flash Page, judges whether current Page data read and finishes, read
Bi Ze reads the data in next Page；
Step c：Complete said process after, to FPGA send allow read return signal, complete FPGA and DSP between
Shake hands；
Step d：After FPGA receives DSP return signal, data are read from address, and the data of reading are carried out
ELF Hash sum, and compared with the ELF Hash summing values that DSP is sent；
If two hash values are the same, the timing information of this reading is added in corresponding sequential node.And to DSP
The marking signal for reading correct data is sent, after DSP receives the signal, the data in address are removed, to read next time
Prepare, and the marking signal of data dump completion is sent to FPGA；After FPGA receives the signal, terminate the reading of this data
Take, FPGA completes shaking hands with DSP.Finished if all data of the node are all read, complete this time to read, by the node
In sequential chained list corresponding to being added to；If data do not read and finished, continue the process at the beginning from step.Until the node institute
There are data all to read to finish, then carry out the reading of next node；
If two hash values are different, FPGA abandons the data this time read, and resends data to DSP requests,
After DSP receives the request, the data in address are removed, and the pointer for reading Flash is pulled back into laststate.And to FPGA
Transmission can re-read signal.After FPGA receives the signal, continue step 1 and later step, re-read this number
According to；
Step 4：After FPGA reads all sequential nodes, sent to DSP and read timing reset signal, DSP is received
To after reset signal, the pointer for reading Flash is referred into back original state, and the marking signal of sequential completion reading is write to FPGA,
After FPGA receives the signal, terminate whole reading process, complete to shake hands with DSP last time.By above procedure from
The sequential read in Flash, the temporal order configured with user are completely the same.
Beneficial effect
A kind of engine fuel supply system control sequential storage proposed by the present invention and read method, are deposited using Flash
The features such as reservoir storage/reading speed is fast, and the processing speed of the digital processing unit such as FPGA, DSP is fast and executive capability is strong, three association
With work, in storage/reading process of sequential, using handshake mechanism and Hash checking algorithms, by control sequential storage to/reading
Flash storage is taken out, the inventive method is fast compared with conventional method storage/reading speed, while compared with commonsense method with higher
Data storage/reading reliability.
The present invention can be different according to the actual operating mode of engine fuel oil system, and sequential carried out into fragmented storage, at each section
Multigroup sequential can be stored in sequence again.When engine fuel supply system works, held according to sequential corresponding to the selection of its actual state
OK, it is made to possess wide operating mode ability to work.
The present invention can reach following effect：
1st, using digital processing units such as FPGA, DSP, sequential storage/reading speed is improved；
2nd, used Handshake Protocol and hash algorithm to carry out sum check during storage/reading sequential, reduced
It is disturbed in storage/reading process and the probability of storage/read error occurs, improves reliability；
3rd, multigroup sequential can be stored/read simultaneously, engine fuel supply system is possessed wide operating mode ability to work.
Brief description of the drawings
Fig. 1：The flow chart of sequential storage
Fig. 2：The flow chart that sequential is read
Embodiment
In conjunction with embodiment, accompanying drawing, the invention will be further described：
DEEC needs to store two groups of sequential, and one group includes 37 nodes, and the length of each node is 35 byte lengths；One
Group sequential includes 14 nodes, and the length of each node is 35 byte lengths.Depositing for this timing can be completed by procedure below
Storage.
Synchronous set the signal 0xAA, DSP that FPGA sends storage sequential by address 0xD0 to DSP are connect by address 0xD0
After receiving 0xAA, the Flash Page of the sequential of storage are formatted, correlated variables initialization, prepare storage sequential；It is accurate
After ready, DSP sends storage ready set signal 0x1, FPGA to FPGA by address 0x150 and receives address
The 0x1 that 0x150 is sent, completes to shake hands with DSP first time.
The number that FPGA counts sequential node in two sequential groups is respectively 37 and 14, by sequential version 0x4048 (sequential
Version number) and the number of network nodes of sequential group package, form one and represent sequential version and each sequential group number of network nodes
Flash head nodes.This node is the length of 4 bytes, preserves sequential version information (0x4048) in the first two byte, the 3rd
The sequential nodes (0x25) of first group of sequential are preserved in byte, the sequential nodes of second group of sequential are preserved in the 4th byte
(0x0E).Then the node in head node and each sequential group is stored in Flash successively.
FPGA and DSP cooperates a node storage is as follows to the process in Flash：
First, FPGA is sent by address 0xD1 to DSP needs the request signal 0x1, DSP of data storage to be read from address 0xD1
After getting 0x1, the corresponding FPGA address 0xD5-0xE9 for writing data are emptied, address 0x152 is immediately passed through after emptying
To the return signal 0x1 of FPGA transmission reception data storage requests, shaking hands between completion FPGA and DSP；
2nd, after FPGA receives the 0x1 of address 0x152 transmissions, this length for writing data is sent to DSP by address 0xD2
Degree.The data length for limiting write-once DSP is no more than 20 bytes (corresponding address 0xD5-0xE9), and the length of head node is 4
Byte can write-once DSP；Sequential node is 35 byte longs, is divided into and writes DSP twice, 20 bytes before writing for the first time
Data, write DSP after its storage, then by the data of remaining 15 bytes；
3rd, FPGA writes the data for needing storage node in DSP, and when entering row write data, FPGA deposits each needs
The data of most 20 bytes of storage carry out ELF Hash summations, and ELF Hash summing values are sent to by address 0xEA
DSP；
4th, after data are sent, FPGA is sent completely to DSP by address 0xD1 and sends data manipulation set signal
0x2, DSP after address 0xD1 reads 0x2, from the 0xD2 of address read this time write-in data length, and according to length from
The data that FPGA is sent are read in the 0xD5-0xE9 of address, and ELF Hash summations are carried out to it, and are read from the 0xEA of address
The ELF Hash summing values that FPGA is sended over, are compared；
If the 5, two hash values are the same, the mark letter for receiving correct data is sent to FPGA by address 0x152
Number 0x1, and by the data Cun Chudao Flash of this reading Page, and whether the real-time judge Flash Page expires page,
Write data into if full page in next Page；Continue storage if less than page and arrive the Page, until its full page.FPGA is read
After the 0x1 for getting address 0x152 transmissions, terminate this data storage, FPGA completes shaking hands with DSP.If in the node
Data do not store completely, continue the process at the beginning from step, until all data in the node are all stored and finished；If should
All storage finishes node data, then terminates the storage of the node, carry out the storage of next node, until all sequential nodes are all
Storage finishes；
If the 6, two hash values are different, DSP empties the data received, and is sent by address 0x152 to FPGA
The signal 0x2, FPGA for resending data storage read 0x2 from address 0x152, restart from step 1, resend
This time data.
After PFGA stores all sequential nodes, the reset signal of storage sequential is sent to DSP by address 0xD0
After 0xBB, DSP read 0xBB from the 0xD0 of address, by the invalid bit clear in Flash current Page, and pass through address
The marking signal 0x0, FPGA that 0x150 completes storage to FPGA transmission timings read 0x0 from the 0x150 of address, complete with DSP
Last time shake hands, terminate whole storing process.Will be all in Flash heads node and two sequential groups by above step
Node is reliably stored in Flash.
When DEEC needs to read sequential, FPGA addresses 0xD0 sends set the signal 0xCC, DSP for reading sequential to DSP
After 0xD0 reads 0xCC from address, prepare sequential read work；After ready, DSP is sent by address 0x151 to FPGA
Read ready set signal 0x1, FPGA and 0x1 is read from the 0x151 of address, complete FPGA and shaken hands with DSP first time.
Head node during 4 byte length is read from Flash, parsing head node can obtain sequential version (0x4048) and two
Sequential number of network nodes is respectively 37 and 14 in individual sequential group.According to the number of sequential node in two sequential groups, when will be each
Each node in sequence group is read from Flash successively, and is added in corresponding sequential.
The idiographic flow that FPGA and DSP collaborative works read head node and sequential node from Flash is as follows：
First, FPGA writes the length for needing to read data, the number of the invention to once reading first by address 0xD4 to DSP
It is defined according to length, limits the data length once read and be no more than 20 bytes (corresponding address 0x155-0x169), head node
Length can once complete to read for 4 bytes；Sequential node is 35 byte longs, is divided into twi-read, reads for the first time
The data of preceding 20 bytes, after its reading, then read the data of remaining 15 bytes；
2nd, FPGA sends reading data request signal 0x1, DSP to DSP by address 0xD3 and reads address 0xD3 number
After 0x1 is changed into, the data length read according to this needs reads the data in Flash Page, and data are write successively
On the 0x155-0x169 of address.While row write data are entered, the data taken out from storage are carried out ELF Hash summations by DSP,
And ELF Hash summing values are write on the 0x16A of address and are sent to FPGA, when DSP reads data from Flash Page, judge
Whether current Page data, which read, finishes, and reading finishes, and reads the data in next Page；
3rd, after completing said process, DSP sends the return signal 0x1 for allowing to read by address 0x153 to FPGA, complete
Into when FPGA and DSP between shake hands；
4th, after FPGA reads 0x1 from the 0x153 of address, data are read from the 0x155-0x169 of address, and to reading
Data carry out ELF Hash summations, the ELF Hash summing values that DSP is calculated are read from the 0x16A of address, and are compared；
If the 5, two hash values are the same, the timing information of this reading is added in corresponding sequential node.Pass through
Address 0xD3 sends the marking signal 0x0 for reading correct data to DSP, and DSP is read after data are changed into 0x0 in 0xD3, clearly
Except the data in 0x155-0x169, prepared to read next time, and it is complete to FPGA transmission data dumps by address 0x153
Into marking signal 0x0.After FPGA receives the signal, terminate this digital independent, FPGA completes shaking hands again with DSP.
Finished if all data of the node are all read, complete this time to read, the node is added in corresponding sequential chained list；
If data do not read and finished, continue the process at the beginning from step.Until all data of the node all read and finished, then carry out
The reading of next node.
If the 6, two hash values are different, FPGA abandons the data this time read, and is sent out by address 0xD3 to DSP
Send and resend after data-signal 0x2, DSP read 0x2 from the 0xD3 of address, remove the data in the 0x155-0x169 of address, and
The pointer for reading Flash is pulled back into laststate.And signal 0x2 can be re-read to FPGA transmissions by 0x153.FPGA from
After reading 0x2 in the 0x153 of address, continue step 1 and later step, re-read this data.
After FPGA reads all sequential nodes, sent by address 0xD0 to DSP and read timing reset signal
After 0xDD, DSP receive the reset signal, the pointer for reading Flash is referred into back original state, and by address to FPGA write when
Sequence complete read marking signal 0x0, FPGA read 0x0 from the 0x151 of address after, terminate whole reading process, complete with
DSP last time is shaken hands.The sequential read by above procedure from Flash, the temporal order configured with user are complete
Unanimously.
Claims (2)
1. a kind of engine fuel supply system control sequential storage method, it is characterised in that step is as follows：
Step 1：When digital electronic controller needs to store sequential, FPGA sends the set signal of storage sequential, DSP to DSP
After receiving the signal, Flash is formatted, and correlated variables initialization；
Step 2：DSP is sent to FPGA stores ready set signal, and FPGA receives the signal, completes FPGA with being deposited between DSP
The first time of storage sequential shakes hands；
Step 3：FPGA counts the number of sequential node in each sequential group, then by sequential version and the number of network nodes of each sequential group
Package, form a Flash head node for representing sequential version and each sequential group number of network nodes, then by head node and respectively
Node in sequential group is stored in Flash successively；
The FPGA and DSP cooperates a node storage is as follows to the process in Flash：
Step a：FPGA sends the request signal for needing data storage to DSP, after DSP receives request signal, by corresponding FPGA
The address for writing data is emptied, and is sent the return signal for receiving data storage request after emptying to FPGA at once, is completed
Shaking hands between FPGA and DSP；
Step b：After FPGA receives DSP return signal, this length for writing data is sent to, to write-once DSP's
Data length is defined, and when needing the data length of storage node to be more than limit value, is divided into and repeatedly being write to DSP, once
The data of limit value length are at most write to DSP, until by all data write-in DSP in the node；When the number of storage node
When being less than setting value according to length, once it is written into DSP；
Step c：FPGA writes the data for needing storage node in DSP, and when entering row write data, FPGA will need to store every time
Data carry out ELF Hash summations, and ELF Hash summing values are connected on behind time series data and are together sent to DSP；
Step d：After data are sent, FPGA is sent completely to DSP and sends data manipulation set signal, and DSP receives the letter
After number, the data length of this time write-in is read from setting address, and reads the number of FPGA transmissions from corresponding address according to length
According to, and ELF Hash summations are carried out to it, and compared with the ELF Hash summing values that FPGA is sended over；
If two hash values are the same, the marking signal for receiving correct data, and the number that this is read are sent to FPGA
According to storage into Flash Page, and whether the real-time judge Flash Page expires page, is write data into down if full page
In one Page；Continue storage if less than page and arrive the Page, until its full page；After FPGA reads the signal, terminate this time
Data storage, FPGA complete shaking hands with DSP；If the data in the node do not store completely, continue this at the beginning from step
Process, until all data in the node are all stored and finished；If all storage finishes the node data, terminate the node
Storage, the storage of next node is carried out, until all sequential nodes are all stored and finished；
If two hash values are different, DSP empties the data received, and the number of this time storage is resend to FPGA requests
After receiving repeating transmission request according to, FPGA, restart from step a, resend this data；
Step 4：After PFGA stores all sequential nodes, the reset signal of storage sequential is sent to DSP, DSP is received
After reset signal, by the invalid bit clear in Flash current Page, and the mark for completing to store to FPGA transmission timings is believed
Number, after FPGA receives the signal, complete to shake hands with DSP last time, terminate whole storing process.
A kind of 2. reading side corresponding with engine fuel supply system control sequential storage method described in claim 1
Method, it is characterised in that step is as follows：
Step 1：When digital electronic controller needs to read sequential, FPGA sends the set signal for reading sequential, DSP to DSP
After receiving the set signal for reading sequential, prepare sequential read work；
Step 2：After ready, DSP sends to FPGA and reads ready set signal, and FPGA receives the signal, completes
FPGA shakes hands with DSP first time；
Step 3：Then according to the Flash head node length of definition, head node is read from Flash；Then head node is parsed,
Obtain the version of sequential and the number of sequential node in each sequential group；According to the number of sequential node in each sequential group, when will be each
Each node in sequence group is read from Flash successively；
The idiographic flow that the FPGA and DSP collaborative works read head node and sequential node from Flash is as follows：
Step a：FPGA writes the length for needing to read data to DSP first, and the data length once read is defined, when need
When the node data length to be read is more than setting value, it is divided into multiple reading, limit value length is once at most only read from Flash
The data of degree, until all data in the node are all read in FPGA；When the data length for reading node is less than or equal to
During setting value, once complete to read；
Step b：FPGA sends to DSP and reads data request signal, after DSP receives request signal, needs to read according to this
Data length read data in Flash Page, and write data on the address of agreement, entering the same of row write data
When, the data taken out from storage are carried out ELF Hash summations by DSP, and ELF Hash summing values are write on appropriate address and sent out
FPGA is given, when DSP reads data from Flash Page, judges whether current Page data read and finishes, reading finishes
Then read the data in next Page；
Step c：Complete said process after, to FPGA send allow read return signal, complete FPGA and DSP between hold
Hand；
Step d：After FPGA receives DSP return signal, data are read from address, and ELF is carried out to the data of reading
Hash sums, and compared with the ELF Hash summing values that DSP is sent；
If two hash values are the same, the timing information of this reading is added in corresponding sequential node, and is sent to DSP
The marking signal of correct data is read, after DSP receives the signal, removes the data in address, standard is done to read next time
It is standby, and to FPGA send data dump complete marking signal；After FPGA receives the signal, terminate this digital independent,
FPGA completes shaking hands with DSP；Finished if all data of the node are all read, complete this time to read, the node is added
In sequential chained list corresponding to being added to；If data do not read and finished, continue the process at the beginning from step；Until the node owns
Data all read and finished, then carry out the reading of next node；
If two hash values are different, FPGA abandons the data this time read, and resends data to DSP requests, and DSP connects
After receiving the request, the data in address are removed, and the pointer for reading Flash is pulled back into laststate, and are sent to FPGA
Signal can be re-read；After FPGA receives the signal, continue step 1 and later step, re-read this data；
Step 4：After FPGA reads all sequential nodes, sent to DSP and read timing reset signal, DSP receives multiple
After the signal of position, the pointer for reading Flash is referred into back original state, and the marking signal of sequential completion reading, FPGA are write to FPGA
After receiving the signal, terminate whole reading process, complete to shake hands with DSP last time, by above procedure from Flash
The sequential of reading, the temporal order configured with user are completely the same.
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| CN201610015871.XA CN105676727B (en) | 2016-01-11 | 2016-01-11 | A kind of engine fuel supply system control sequential storage and read method |
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4284052A (en) * | 1979-08-23 | 1981-08-18 | The Bendix Corporation | Sequential injector timing apparatus |
| JPS5713239A (en) * | 1980-06-27 | 1982-01-23 | Honda Motor Co Ltd | Fuel injection timing control method and system for efi engine |
| WO2003073259A1 (en) * | 2002-02-21 | 2003-09-04 | Qualcomm, Incorporated | Direct memory swapping between nand flash and sram with error correction coding |
| CN101586505A (en) * | 2008-05-21 | 2009-11-25 | Gm全球科技运作股份有限公司 | Method and system for controlling operating pressure in a common-rail fuel injection system |
| CN102072817A (en) * | 2010-11-25 | 2011-05-25 | 西北工业大学 | Device and method for controlling ignition by constant-current time sequence |
| CN103090724A (en) * | 2013-01-21 | 2013-05-08 | 北京航空航天大学 | Solid-liquid power sounding rocket land launching sequential control system |
| EP2883146A1 (en) * | 2012-08-07 | 2015-06-17 | Qualcomm Incorporated | Methods, systems and devices for hybrid memory management |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5894493B2 (en) * | 2011-08-09 | 2016-03-30 | ルネサスエレクトロニクス株式会社 | Timing control apparatus and control system including the same |
-
2016
- 2016-01-11 CN CN201610015871.XA patent/CN105676727B/en not_active Expired - Fee Related
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4284052A (en) * | 1979-08-23 | 1981-08-18 | The Bendix Corporation | Sequential injector timing apparatus |
| JPS5713239A (en) * | 1980-06-27 | 1982-01-23 | Honda Motor Co Ltd | Fuel injection timing control method and system for efi engine |
| WO2003073259A1 (en) * | 2002-02-21 | 2003-09-04 | Qualcomm, Incorporated | Direct memory swapping between nand flash and sram with error correction coding |
| CN101586505A (en) * | 2008-05-21 | 2009-11-25 | Gm全球科技运作股份有限公司 | Method and system for controlling operating pressure in a common-rail fuel injection system |
| CN102072817A (en) * | 2010-11-25 | 2011-05-25 | 西北工业大学 | Device and method for controlling ignition by constant-current time sequence |
| EP2883146A1 (en) * | 2012-08-07 | 2015-06-17 | Qualcomm Incorporated | Methods, systems and devices for hybrid memory management |
| CN103090724A (en) * | 2013-01-21 | 2013-05-08 | 北京航空航天大学 | Solid-liquid power sounding rocket land launching sequential control system |
Non-Patent Citations (2)
| Title |
|---|
| Implementing high speed communication buses for a FPGA-DSP architecture for digital control of power electronics;C GiroN,FJ Rodriguez,F Huerta,E Bueno;《IEEE International Symposium on Intelligent Signal Processing》;20071130;第1-6页 * |
| 脉冲风洞发动机试验多油位多时序;邓维鑫,乐嘉陵,杨顺华,张弯洲,周华波,许明恒;《实验流体力学》;20130630;第27卷(第3期);第70-76页 * |
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