CN107682311B - Hardware-implemented multi-link TCP data reconstruction system - Google Patents
Hardware-implemented multi-link TCP data reconstruction system Download PDFInfo
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Abstract
The invention discloses a hardware-implemented multilink TCP data reorganization system, which comprises a TCP header load separation module, a data packet processing module and a data processing module, wherein the TCP header load separation module is used for extracting relevant information in a data packet and finishing the separate storage of a data header and a load; the HASH linked list module is used for completing the operations of adding, searching and deleting the HASH linked list according to the related header information, generating a link number and carrying out multi-link management on the data packet; the TCP data recombination management module completes the recombination management of the out-of-order data packets through a channel cache technology and a channel shift technology according to the header information and the link number; and the large-capacity external memory control module is used for finishing sequential splicing storage of the load data. The invention adopts a hardware mode to realize TCP data recombination under a multi-link environment, and can obtain higher network transmission rate and bandwidth utilization rate than the prior software implementation mode.
Description
Technical Field
The invention belongs to the technical field of network communication, and particularly relates to a hardware-implemented multilink TCP data reconstruction system.
Background
With the continuous development of computer technology and the continuous improvement of network communication system performance, network technology has also been widely used, and at the same time, the utilization and demand of networks are higher and higher. The transmission control protocol (TCP protocol) is a reliable transmission protocol which is most widely used, and is a link-oriented point-to-point transport layer protocol, which can implement reliable delivery service and ensure that data transmitted by a TCP link is error-free, lost-free and repeated. Meanwhile, the TCP protocol allows application processes of two communication parties to send data and receive data at any time, and provides full-duplex communication services. With the deepening of the application of network technology, the amount of data transmitted by the network is larger and larger, and a single TCP data packet cannot carry a large amount of data, so that the fragmented transmission of data information becomes a mainstream mode. Due to the non-uniqueness of the transmitted physical path, the received TCP data packets may be out of order, and how to accurately and quickly realize the sequencing and recombination of the TCP data in a multi-link parallel processing system is an important link for ensuring the transmission correctness.
At present, the realization of TCP data recombination is mainly completed by a software mode. With the increasing demand of networks, the flow rate of network data becomes an important standard for measuring the quality of the network. In the era of fiber optic networks today, network bandwidth resources have no longer been the bottleneck limiting network data flow rates, but rather the speed of the processors. The software mode attached to the CPU and the operating system processes the TCP data reassembly, and the speed of the software mode is greatly limited by the processing speed of the CPU, which results in the waste of network bandwidth resources and the inability to improve the network data flow rate.
In order to improve the utilization rate of network bandwidth, realize high-speed transmission of network data, and reduce the resource overhead of a CPU in network transmission, the realization of TCP data reassembly in a hardware manner has become a main direction of research.
Disclosure of Invention
In order to solve the technical problems in the background art, the present invention aims to provide a hardware-implemented multilink TCP data reassembly system, which overcomes the defects of the existing software-based data reassembly method, reduces the resource overhead of the CPU in network transmission, and improves the utilization rate of the network bandwidth.
In order to achieve the technical purpose, the technical scheme of the invention is as follows:
a multilink TCP data reorganization system realized by hardware comprises a TCP header load separation module, a HASH linked list module, a TCP data reorganization management module and a large-capacity external memory control module;
the TCP header load separation module receives a data stream and a control signal from an Ethernet MAC controller, extracts and calculates the header length, the load length, a quadruple, a serial number and a HASH command signal of the data of the packet according to a TCP/IP protocol format, writes the header data into a header temporary storage FIFO, and writes the load data into the load temporary storage FIFO, wherein the quadruple comprises a source end IP address, a destination end IP address, a source end port number and a destination end port number;
the HASH linked list module receives the HASH command signal and the quadruple generated by the TCP header load separation module, obtains a corresponding HASH value according to the quadruple calculation, completes the addition, search and deletion of the HASH linked list according to the HASH command signal, generates link numbers corresponding to the quadruple one by one, and manages data according to links;
the TCP data recombination management module receives the serial number, the load length, the HASH command signal and the link number generated by the HASH chain table module, which are generated by the TCP header load separation module, compares the serial number and the load length with effective information in n data channels under corresponding links, if the data can be matched with the information in a certain data channel, the data is added into the channel, and if the data cannot be matched with the information of any channel, a new data channel is enabled to store the data, and the load length and the serial number of the recombined data are output.
The high-capacity external storage control module receives an output signal of the TCP data reorganization management module, reads load data into the module from the load temporary storage FIFO according to the output signal, splices the data, and sends the spliced data into the external high-capacity storage through a data writing channel for storage, so that reorganization of out-of-order data packets in the Ethernet is realized.
Further, the TCP header load separation module includes a counting control module, a CRC check module, a MAC frame header extraction module, an IP header extraction module, a TCP header extraction module, a load extraction module, a data discard enabling module, and a header information format generation module; the counting control module detects a control signal of the Ethernet MAC controller in real time, when valid data are input, the counting control module is started, MAC frame data are written into an input cache FIFO, meanwhile, a CRC check module is started to carry out CRC check on the input data, whether errors occur in transmission is judged, if the CRC check fails, an error transmission command is sent to a data discarding enabling module, and the data of the packet is discarded; the data after CRC check is sequentially input into an MAC frame header extraction module, an IP header extraction module and a TCP header extraction module, the header length, the load length, the quadruple, the serial number and the characteristic zone bit are sequentially extracted and calculated according to the header format of a TCP/IP protocol, a HASH command signal is generated according to the information of the characteristic zone bit, then the data is input into the load extraction module, and the load data is written into a load temporary storage FIFO under the control of a counting control module; when the data discarding enabling module receives the error transmission signal of the CRC, the data transmission is wrong, a data discarding signal is generated, and the data in the header temporary storage FIFO and the load temporary storage FIFO are read away to discard the data; when the data is transmitted correctly, the header information generation module packs the HASH command, the number of header zero padding, the sequence number, the load length, the data length and the link number into a header temporary storage FIFO according to a set format.
Furthermore, the HASH linked list module comprises a quick search module, a HASH function module, a central control module, a table head RAM, a table item RAM and a pointer RAM; defining m memory units in the quick search module, and recording quadruples and corresponding link numbers input by different quadruples m times before the operation; comparing the quadruple input into the fast search module with the quadruple values recorded in m memory units, and if the quadruple input into the module is matched with the quadruple recorded in 1 of the memory units, directly outputting the link number recorded in the memory unit; if the m memory units can not be successfully matched, the input quadruple is sent to the HASH function module, an HASH value with 12bit wide is obtained through calculation and sent to the central control module, and one of the enabling data adding module, the data searching module and the data deleting module is selected according to an HASH command signal; the enabled module firstly addresses the table head RAM according to the HASH value, then addresses the table item RAM according to the data in the table head RAM, and if the value in the table item RAM is matched with the input quadruple, the address of the table item RAM is output as a link number; if not, the pointer RAM is addressed according to the value in the table head RAM to obtain a new address, the table item RAM is addressed again, and the operation is repeated to obtain the link number.
Furthermore, the TCP data recombination management module comprises an information sampling module, a state control module, a retransmission judging module, a starting packet recombination module, a transmission packet recombination module, an ending packet recombination module and an output information module; the information sampling module samples input information such as serial numbers, load lengths, link numbers and the like; the state control module receives the signal collected by the information sampling module, starts time sequence control, enables the retransmission judging module and the output information module according to the time sequence, enables one of the initial packet recombination module, the transmission packet recombination module and the end packet recombination module according to the HASH command signal, accesses n data channels correspondingly linked, compares the input information with the information in the data channels, and completes TCP data recombination.
Further, the specific operation steps of the TCP data reassembly management module are as follows:
(1) if the signal acquisition module detects a matching success signal, sampling information such as an input serial number, a load length, a link number and the like, and sending a sampling result to the state control module;
(2) the state control module enables the retransmission judging module and inputs the load length, the serial number and the link number; the retransmission judging module accesses the information of n data channels under the current link number through an RAM bus; comparing the input load length and the serial number with effective information in a data channel, judging whether the data of the serial number and the load length belong to the effective information in the channel, if the matching is successful, starting a retransmission signal, and directly entering the step 7, otherwise, entering the step (3);
(3) according to the input HASH command signal, if the HASH command is established, entering the step (4); if the HASH command is a search command, entering the step (5); if the HASH command is deleted, entering the step (6);
(4) accessing a memory unit with a serial number RAM, a length RAM and an effective bit RAM address as a link number through an RAM bus; setting memory units of the serial number RAM and the length RAM to be zero; writing 00000001 into the effective bit RAM memory unit, and entering the step (7);
(5) judging whether the serial number of the current packet data and the previous packet data meet continuity, namely the serial number loading length of the previous packet is equal to the serial number of the current packet, and if the continuity is met, directly attaching the data information of the current packet to a channel where the previous packet data are located through an RAM bus; if the continuity is not met, the data information of the packet is compared with the information in the effective channel in the n channels for two times, whether the sum of the serial number and the load length of the information in the channel is equal to the serial number of the current packet or not is judged for the first time, whether the sum of the serial number and the load length of the previous packet is equal to the serial number of the information in the channel or not is judged for the second time, and if the first matching is successful, the channel information with the load length of the packet is used for replacing the original channel information; if the second matching is successful, replacing the original channel information by the sequence number of the packet and the channel information added with the load length of the packet; if the matching is successful, adding the lengths of the two channel information and the load length of the packet data to replace the channel information with a smaller channel number, and simultaneously, setting the position with a larger channel number in the effective bit RAM to be zero; if the matching is unsuccessful, determining the serial number of the data storage channel of the packet according to the size relation of the serial numbers, sequentially adding one to the serial numbers of the rest channels, sequentially shifting and storing, and entering the step (7);
(6) accessing a memory unit with a serial number RAM, a length RAM and an effective bit RAM address as a link number through an RAM bus; setting memory units of the serial number RAM, the length RAM and the effective bit RAM to be zero, and entering the step (7);
(7) and packaging the link number, the serial number and the load length of the packet data into a write data command format and sending the write data command format into a large-capacity external memory control module.
Furthermore, the high-capacity external memory control module comprises a data write-in command analysis module, a retransmission module, a data write-in splicing module, a data read-out command analysis module, a data read-out splicing module and an external memory interface module; when a data writing command is transmitted from the TCP data recombination management module, the data writing command analysis module analyzes the command, if the command belongs to retransmission data, the retransmission module is enabled to read the data from the load cache FIFO, and the data is discarded; if not heavyData is transmitted, the data write-in splicing module is enabled to read data from the load cache FIFO, the data are spliced and written into the write data FIFO according to the bit width requirement and the write command requirement of the external memory, and meanwhile, the external memory interface module reads the data from the write data FIFO and continuously writes the data into corresponding addresses according to the write command requirement; the data reading command analysis module analyzes externally input reading data commands and simultaneously enables the data reading splicing module and the external memory interface module, the external memory interface module writes data into the reading data FIFO through the reading channel according to requirements, the data reading splicing module reads the data from the reading data FIFO and splices the data into a complete 2iAnd outputting in a bit format, wherein i is more than or equal to 4.
Adopt the beneficial effect that above-mentioned technical scheme brought:
the invention adopts hardware description language to describe the required function index, processes the related information of the data packet through the channel cache technology and the channel shift technology, efficiently completes the reorganization and ordering of the disordered data packet in the network, and simultaneously manages different dialogue links by using the HASH linked list, thereby realizing the reorganization of the disordered network data packet under the condition of multiple links. The invention greatly improves the network transmission speed and the network bandwidth utilization rate under the condition of not increasing the resource overhead. Compared with a software implementation mode, the method has the advantages of higher efficiency, higher speed, larger storage scale, better flexibility and stronger usability.
Drawings
FIG. 1 is an overall block diagram of the present invention;
FIG. 2 is a block diagram of the TCP header payload separation module of the present invention;
FIG. 3 is a block diagram of a HASH chain table module according to the present invention;
FIG. 4 is a diagram of a TCP reassembly management module according to the present invention;
FIG. 5 is a flow chart of the operation of the TCP reassembly management module of the present invention;
FIG. 6 is a diagram of a mass storage external memory control module according to the present invention.
Detailed Description
The technical scheme of the invention is explained in detail in the following with the accompanying drawings.
The invention designs a hardware-implemented multilink TCP data reorganization system, the overall structure of which is shown in FIG. 1 and comprises a TCP header load separation module, a HASH linked list module, a TCP data reorganization management module and a large-capacity external memory control module.
The TCP header load separation module receives a data stream and a control signal from the Ethernet MAC controller, extracts and calculates the header length, the load length, the quadruplet, the serial number, the HASH command signal and the like of the data of the packet according to the TCP/IP protocol format, and simultaneously feeds back the link number, the matching success signal and the matching failure signal output by the HASH linked list module to the TCP header load separation module, so as to package header information conveniently, write header data into the header temporary storage FIFO and write the load data into the header temporary storage FIFO.
The HASH linked list module receives the HASH command signal and the data packet quadruple signal generated by the TCP header load separation module, obtains a corresponding HASH value according to the quadruple calculation, and completes the addition, search and deletion of the HASH linked list according to the HASH command signal to generate link numbers corresponding to the quadruple one by one.
The TCP data recombination management module receives the serial number, the load length, the HASH command signal and the like generated by the TCP header load separation module and the link number and the matching success signal generated by the HASH chain table module at the same time, utilizes the parallelism principle of hardware design, compares the serial number and the load length with the information in the effective channels in the n channels under the corresponding link number at the same time, adds the data of the packet into a certain channel if the data can be matched with the information in the channel, enables a new channel to store the data of the packet if the data cannot be matched with the data of any channel, and outputs a format command comprising the information of a retransmission signal, the current load length, the current load serial number and the link number.
The large-capacity external storage control module receives control commands such as retransmission mark signals, current load length, current serial number and the like generated by the TCP data reorganization management module, reads load data into the module from the load temporary storage FIFO according to the control signals, splices the data, sends the spliced data into the external storage through a data writing channel for storage, realizes reorganization of disordered data packets in the Ethernet, can receive format commands including a read link number, a read length and a read serial number input from the outside, can read corresponding information according to the input information, and sends the information to the application layer for processing.
Fig. 2 is a block diagram of a TCP header payload separation module designed in accordance with the present invention. The TCP header load separation module comprises a counting control module, a CRC check module, an MAC frame header extraction module, an IP header extraction module, a TCP header extraction module, a load extraction module, a data discarding enabling module and a header information generation module. The counting control module detects a control signal of the Ethernet MAC controller in real time, when valid data are input, the counting control module is started, MAC frame data are written into an input cache FIFO, meanwhile, a CRC check module is started to carry out CRC check on the input data to judge whether errors occur in transmission, if the CRC check fails, an error transmission command is sent to a data discarding enabling module, and the data of the packet is discarded; and after CRC (cyclic redundancy check) verification, the data are sequentially input into an MAC frame header extraction module, an IP (Internet protocol) header extraction module and a TCP header extraction module, information such as a header length, a load length, a quadruple, a serial number, a characteristic zone bit and the like is sequentially extracted and calculated according to a header format of a TCP/IP (transmission control protocol/Internet protocol), and a HASH command signal is generated according to the information of the characteristic zone bit. Then the data is input into a load extraction module, and the load data is written into a temporary load FIFO under the control of a counting control module. When the data discarding enabling module receives a CRC (cyclic redundancy check) checked error transmission signal or a matching failure signal input by the HASH linked list module, the data discarding enabling module indicates that data transmission is wrong, a data discarding signal is generated, and data in the header temporary storage FIFO and the load temporary storage FIFO are read away to discard the data. When the data is correctly transmitted, the header information generation module packs the HASH command, the header zero padding quantity, the sequence number, the load length, the data length and the link number into a header temporary storage FIFO according to a certain format so as to be directly used in the subsequent processing process.
Fig. 3 is a structural diagram of a HASH chain table module in a device for hardware implementation of multi-link TCP data reassembly according to the present invention. The HASH linked list module comprises a quick searching module, a HASH function module, a central control module, a table head RAM, a table item RAM and a pointer RAM. The fast searching module defines m structure body memory units and records the quadruple values and the corresponding link numbers input by different quadruples m times before the operation. m is an integer greater than 0, and the larger the value of m, the more resources are consumed, and is usually set to an integer between 4 and 8. The quadruple input into the module firstly enters a quick searching module, the characteristic of hardware parallel processing is utilized to compare with the quadruple values in m memory units, if one of the memory units can be matched, the recorded link number is directly output, if the m memory units can not be successfully matched, the quadruple is sent into an HASH function module, the HASH value with the bit width of 12 bits is obtained through calculation and sent into a central control module, and one of an enabling data adding module, a data searching module and a data deleting module is selected through an HASH command signal. The enabled module firstly addresses the table head RAM according to the HASH value through the RAM bus, then addresses the table item RAM according to the data in the table head RAM, and if the value in the table item RAM is matched with the input quadruple, the address of the table item RAM is output as a link number; if not, the pointer RAM is addressed according to the value in the table head RAM to obtain a new address, and the table item RAM is addressed again, and the above operations are repeated to obtain the link number.
Fig. 4 is a structural diagram of a TCP data reassembly management module designed in the present invention. The TCP data recombination management module comprises an information sampling module, a state control module, a retransmission judging module, an initial packet recombination module, a transmission packet recombination module, an end packet recombination module and an output information module. The information sampling module samples input information such as serial numbers, load lengths, link numbers and the like; the state control module receives the signals collected by the information sampling module, starts time sequence control, enables the retransmission judging module and the output information module according to the time sequence, enables one of the initial packet recombination module, the transmission packet recombination module and the end packet recombination module according to the HASH command signal, accesses n data channels correspondingly linked through the RAM bus, compares the input information with the information in the data channels, and completes TCP data recombination. n takes an integer greater than 0 and typically takes an integer value between 8 and 16.
Fig. 5 is a flowchart illustrating the operation of the TCP data reassembly management module, which includes the following specific steps:
step 1: if the signal acquisition module detects a matching success signal, sampling information such as an input serial number, a load length, a link number and the like, and sending a sampling result to the state control module;
step 2: the state control module enables the retransmission judging module and inputs the load length, the serial number and the link number; the retransmission judging module accesses the information of n data channels under the current link number through an RAM bus; comparing the input load length and the serial number with effective information in a data channel by using a hardware parallelism principle, judging whether the data of the serial number and the load length belong to the effective information in the channel, if the comparison is successful, starting a retransmission signal, and directly entering a step 7, otherwise, entering a step 3;
and step 3: according to the input HASH command signal, if the HASH command is established, entering a step 4; if the HASH command is a search command, entering a step 5; if the HASH command is delete, entering step 6;
and 4, step 4: accessing a memory unit with a serial number RAM, a length RAM and an effective bit RAM address as a link number through an RAM bus; setting memory units of the serial number RAM and the length RAM to be zero; writing 00000001 into the effective bit RAM memory unit, and entering step 7;
and 5: judging whether the serial number of the current packet data and the previous packet data meet continuity, namely the serial number loading length of the previous packet is equal to the serial number of the current packet, and if the continuity is met, directly attaching the data information of the current packet to a channel where the previous packet data are located through an RAM bus; if the continuity is not met, the data information of the packet is compared with the information in the effective channel in the n channels for two times, whether the sum of the serial number and the load length of the information in the channel is equal to the serial number of the current packet or not is judged for the first time, whether the sum of the serial number and the load length of the previous packet is equal to the serial number of the information in the channel or not is judged for the second time, and if the first matching is successful, the channel information with the load length of the packet is used for replacing the original channel information; if the second matching is successful, replacing the original channel information by the sequence number of the packet and the channel information added with the load length of the packet; if the matching is successful, adding the lengths of the two channel information and the load length of the packet data to replace the channel information with a smaller channel number, and simultaneously, setting the position with a larger channel number in the effective bit RAM to be zero; if the matching is unsuccessful, determining the serial number of the data storage channel of the packet according to the size relation of the serial numbers, sequentially adding one to the serial numbers of the rest channels, sequentially shifting and storing, and entering the step 7;
step 6: accessing a memory unit with a serial number RAM, a length RAM and an effective bit RAM address as a link number through an RAM bus; setting memory units of the serial number RAM, the length RAM and the effective bit RAM to be zero, and entering step 7;
and 7: and packaging the link number, the serial number and the load length of the packet data into a write data command format, and sending the write data command format into a large-capacity external memory control module for splicing and storing the load data.
Fig. 6 is a structural diagram of a large capacity external memory control module. The large-capacity external memory control module comprises a data writing command analysis module, a retransmission module, a data writing splicing module, a data reading command analysis module, a data reading splicing module and an external memory interface module. When a data writing command is transmitted from the TCP data recombination management module, the data writing command analysis module analyzes the command, if the command belongs to retransmission data, the retransmission module is enabled to read the data from the load cache FIFO, and the data is discarded; if the data is not the retransmission data, enabling the data write-in splicing module to read the data from the load cache FIFO according to the bit width requirement of the external memory and the requirement of the write-in command, splicing and writing the data into the write-in data FIFO, and simultaneously, enabling the external memory interface module to read the data from the FIFO and continuously write the data into the corresponding address according to the requirement of the write-in command. The data reading command analysis module can analyze externally input reading data commands and simultaneously enables the data reading splicing module and the external memory interface module, the external memory interface module writes data into the reading data FIFO through a reading channel as required, and the data reading splicing module reads the data from the FIFO and splices the data into a complete 2iAnd outputting the bit format. i is an integer greater than 4 and,the bit width is typically 32 bits or 64 bits depending on the network environment in which the application is implemented.
The embodiments are only for illustrating the technical idea of the present invention, and the technical idea of the present invention is not limited thereto, and any modifications made on the basis of the technical scheme according to the technical idea of the present invention fall within the scope of the present invention.
Claims (6)
1. A hardware-implemented multilink TCP data reorganization system is characterized in that: the system comprises a TCP header load separation module, a HASH linked list module, a TCP data recombination management module and a large-capacity external memory control module;
the TCP header load separation module receives a data stream and a control signal from an Ethernet MAC controller, extracts and calculates the header length, the load length, a quadruple, a serial number and a HASH command signal of the data of the packet according to a TCP/IP protocol format, writes the header data into a header temporary storage FIFO, and writes the load data into the load temporary storage FIFO, wherein the quadruple comprises a source end IP address, a destination end IP address, a source end port number and a destination end port number;
the HASH linked list module receives the HASH command signal and the quadruple generated by the TCP header load separation module, obtains a corresponding HASH value according to the quadruple calculation, completes the addition, search and deletion of the HASH linked list according to the HASH command signal, generates link numbers corresponding to the quadruple one by one, and manages data according to links;
the TCP data recombination management module receives the serial number, the load length, the HASH command signal and the link number generated by the HASH chain table module, which are generated by the TCP header load separation module, and compares the serial number and the load length with effective information in n data channels under corresponding links, if the data can be matched with the information in a certain data channel, the data is added into the channel, and if the data cannot be matched with the information of any channel, a new data channel is enabled to store the data, and the load length and the serial number of the recombined data are output;
the high-capacity external storage control module receives an output signal of the TCP data reorganization management module, reads load data into the module from the load temporary storage FIFO according to the output signal, splices the data, and sends the spliced data into the external high-capacity storage through a data writing channel for storage, so that reorganization of out-of-order data packets in the Ethernet is realized.
2. The hardware-implemented multilink TCP data reassembly system as recited in claim 1, wherein: the TCP header load separation module comprises a counting control module, a CRC (cyclic redundancy check) module, an MAC (media access control) frame header extraction module, an IP (Internet protocol) header extraction module, a TCP header extraction module, a load extraction module, a data discarding enabling module and a header information format generation module; the counting control module detects a control signal of the Ethernet MAC controller in real time, when valid data are input, the counting control module is started, MAC frame data are written into an input cache FIFO, meanwhile, a CRC check module is started to carry out CRC check on the input data, whether errors occur in transmission is judged, if the CRC check fails, an error transmission command is sent to a data discarding enabling module, and the data of the packet is discarded; the data after CRC check is sequentially input into an MAC frame header extraction module, an IP frame header extraction module and a TCP frame header extraction module, the length of a frame header, the length of a load, a quadruple, a serial number and a characteristic zone bit are sequentially extracted and calculated according to the frame header format of a TCP/IP protocol, a HASH command signal is generated according to the information of the characteristic zone bit, then the data is input into the load extraction module, and load data is written into a load temporary storage FIFO under the control of a counting control module; when the data discarding enabling module receives the error transmission signal of the CRC, the data transmission is wrong, a data discarding signal is generated, and after the data in the header temporary storage FIFO and the load temporary storage FIFO are read away, the data in the two FIFOs are discarded; when the data is transmitted correctly, the header information generation module packs the HASH command, the number of header zero padding, the sequence number, the load length, the data length and the link number into a header temporary storage FIFO according to a set format.
3. The hardware-implemented multilink TCP data reassembly system as recited in claim 1, wherein: the HASH linked list module comprises a quick search module, a HASH function module, a central control module, a table head RAM, a table item RAM and a pointer RAM; defining m memory units in the quick search module, and recording quadruples and corresponding link numbers input by different quadruples m times before the operation; comparing the quadruple input into the fast search module with the quadruple values recorded in m memory units, and if the quadruple input into the module is matched with the quadruple recorded in 1 of the memory units, directly outputting the link number recorded in the memory unit; if the m memory units can not be successfully matched, the input quadruple is sent to the HASH function module, an HASH value with 12bit wide is obtained through calculation and sent to the central control module, and one of the enabling data adding module, the data searching module and the data deleting module is selected according to an HASH command signal; the enabled module firstly addresses the table head RAM according to the HASH value, then addresses the table item RAM according to the data in the table head RAM, and if the value in the table item RAM is matched with the input quadruple, the address of the table item RAM is output as a link number; if not, the pointer RAM is addressed according to the value in the table head RAM to obtain a new address, the table item RAM is addressed again, and the operation is repeated to obtain the link number.
4. The hardware-implemented multilink TCP data reassembly system as recited in claim 1, wherein: the TCP data recombination management module comprises an information sampling module, a state control module, a retransmission judging module, an initial packet recombination module, a transmission packet recombination module, an end packet recombination module and an output information module; the information sampling module samples input information such as serial numbers, load lengths, link numbers and the like; the state control module receives the signal collected by the information sampling module, starts time sequence control, enables the retransmission judging module and the output information module according to the time sequence, enables one of the initial packet recombination module, the transmission packet recombination module and the end packet recombination module according to the HASH command signal, accesses n data channels correspondingly linked, compares the input information with the information in the data channels, and completes TCP data recombination.
5. The hardware-implemented multilink TCP data reassembly system as recited in claim 4, wherein: the TCP data recombination management module specifically comprises the following operation steps:
(1) if the signal acquisition module detects a matching success signal, sampling information such as an input serial number, a load length, a link number and the like, and sending a sampling result to the state control module;
(2) the state control module enables the retransmission judging module and inputs the load length, the serial number and the link number; the retransmission judging module accesses the information of n data channels under the current link number through an RAM bus; comparing the input load length and the serial number with effective information in a data channel, judging whether the data of the serial number and the load length belong to the effective information in the channel, if the matching is successful, starting a retransmission signal, and directly entering the step (7), otherwise, entering the step (3);
(3) according to the input HASH command signal, if the HASH command is established, entering the step (4); if the HASH command is a search command, entering the step (5); if the HASH command is deleted, entering the step (6);
(4) accessing a memory unit with a serial number RAM, a length RAM and an effective bit RAM address as a link number through an RAM bus; setting memory units of the serial number RAM and the length RAM to be zero; writing 00000001 into the effective bit RAM memory unit, and entering the step (7);
(5) judging whether the serial number of the current packet data and the previous packet data meet continuity, namely the serial number loading length of the previous packet is equal to the serial number of the current packet, and if the continuity is met, directly attaching the data information of the current packet to a channel where the previous packet data are located through an RAM bus; if the continuity is not met, the data information of the packet is compared with the information in the effective channel in the n channels for two times, whether the sum of the serial number and the load length of the information in the channel is equal to the serial number of the current packet or not is judged for the first time, whether the sum of the serial number and the load length of the previous packet is equal to the serial number of the information in the channel or not is judged for the second time, and if the first matching is successful, the channel information with the load length of the packet is used for replacing the original channel information; if the second matching is successful, replacing the original channel information by the sequence number of the packet and the channel information added with the load length of the packet; if the matching is successful, adding the lengths of the two channel information and the load length of the packet data to replace the channel information with a smaller channel number, and simultaneously, setting the position with a larger channel number in the effective bit RAM to be zero; if the matching is unsuccessful, determining the serial number of the data storage channel of the packet according to the size relation of the serial numbers, sequentially adding one to the serial numbers of the rest channels, sequentially shifting and storing, and entering the step (7);
(6) accessing a memory unit with a serial number RAM, a length RAM and an effective bit RAM address as a link number through an RAM bus; setting memory units of the serial number RAM, the length RAM and the effective bit RAM to be zero, and entering the step (7);
(7) and packaging the link number, the serial number and the load length of the packet data into a write data command format and sending the write data command format into a large-capacity external memory control module.
6. The hardware-implemented multilink TCP data reassembly system as recited in claim 1, wherein: the high-capacity external memory control module comprises a data write-in command analysis module, a retransmission module, a data write-in splicing module, a data read-out command analysis module, a data read-out splicing module and an external memory interface module; when a data writing command is transmitted from the TCP data recombination management module, the data writing command analysis module analyzes the command, if the command belongs to retransmission data, the retransmission module is enabled to read the data from the load cache FIFO, and the data is discarded; if the data is not the retransmission data, enabling the data write-in splicing module to read the data from the load cache FIFO, splicing the data and writing the data into the write data FIFO according to the bit width requirement of the external memory and the requirement of a write command, and simultaneously reading the data from the write data FIFO by the external memory interface module and continuously writing the data into a corresponding address according to the requirement of the write command; the data reading command analysis module analyzes externally input reading data commands and simultaneously enables the data reading splicing module and the external memory interface module, the external memory interface module writes data into the reading data FIFO through the reading channel according to requirements, the data reading splicing module reads the data from the reading data FIFO and splices the data into a complete 2iThe output of the bit format is carried out,wherein i is greater than or equal to 4.
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| CN111917780A (en) * | 2020-08-05 | 2020-11-10 | 电信科学技术第五研究所有限公司 | FPGA-based TOE data splicing system and method |
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