CN105675955A - A zero power consumption voltage detection circuit - Google Patents
A zero power consumption voltage detection circuit Download PDFInfo
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- CN105675955A CN105675955A CN201610039075.XA CN201610039075A CN105675955A CN 105675955 A CN105675955 A CN 105675955A CN 201610039075 A CN201610039075 A CN 201610039075A CN 105675955 A CN105675955 A CN 105675955A
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- mos pipe
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- circuit
- phase inverter
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- 238000001514 detection method Methods 0.000 title claims abstract description 14
- 230000007812 deficiency Effects 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/0084—Arrangements for measuring currents or voltages or for indicating presence or sign thereof measuring voltage only
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Measurement Of Current Or Voltage (AREA)
- Semiconductor Integrated Circuits (AREA)
- Manipulation Of Pulses (AREA)
- Electronic Switches (AREA)
Abstract
本发明公开了一种零功耗电压检测电路，该电路是采用多个MOS管和锁相环组成的检测电路来检测输入电源电压的变化，并能够在电源电压达到集成电路的工作电源后停止检测电路的工作，从而达到了零功耗的功能；输入端设置的延时电路进一步的满足了集成电路在电源达到工作电压时工作的要求。
The invention discloses a zero-power consumption voltage detection circuit, which uses a detection circuit composed of multiple MOS tubes and a phase-locked loop to detect the change of input power supply voltage, and can stop the detection circuit from working after the power supply voltage reaches the working power supply of an integrated circuit, thereby achieving the function of zero power consumption; the delay circuit arranged at the input end further meets the requirement that the integrated circuit works when the power supply reaches the working voltage.
Description
Technical field
The invention belongs to the voltage detection circuit technical field in unicircuit, especially relate to a kind of zero-power voltage detecting circuit.
Background technology
At present, unicircuit is in the moment of energising, due to the time delay reason of power supply boosting, when voltage of supply does not reach the operating voltage of unicircuit, unicircuit is it is possible to this situation of starting working not only can not ensure the normal operation of unicircuit but also unicircuit can be caused damage, need to arrange one for detecting the circuit of voltage of supply, in the middle of prior art relatively normal adopt as
Circuit structure shown in Fig. 1 carries out judging sampling, and owing to there is voltage on the Vref of circuit all the time, so have watt consumption with unicircuit work always, this causes the waste of resource, and increases and have impact on cost and the use of unicircuit.
Summary of the invention
For solving the deficiencies in the prior art problem, the present invention provides a kind of zero-power voltage detecting circuit, this circuit adopts multiple MOS to manage the detection circuit with phaselocked loop composition to detect the change of input supply voltage, and can stop detecting the work of circuit after voltage of supply reaches the working power of unicircuit, thus reach the function of zero-power; The unicircuit that meets that the time delay circuit of input terminus setting is further reaches, at power supply, the requirement that operating voltage is work.
A kind of zero-power voltage detecting circuit, comprises power input, output terminal, ground terminal and voltage time delay detection circuit, and described detection circuit comprises a MOS pipe, the 2nd MOS pipe, the 3rd MOS pipe, the 4th MOS pipe, the 5th MOS pipe and phase-locked circuit; The grid of the one MOS pipe and the grid junction circuit output terminal of the 4th MOS pipe, a MOS pipe source electrode connects power input, and the drain electrode of a MOS pipe connects the drain electrode pole of the 2nd MOS pipe; The source electrode of the 2nd MOS pipe connects ground terminal, and the grid of the 2nd MOS pipe connects the grid of the 3rd MOS pipe; The source electrode of the 3rd MOS pipe connects ground terminal, and its drain electrode connects the grid of the 5th MOS pipe; The source electrode of the 5th MOS pipe and drain electrode connect power input, and the source electrode of the 4th MOS pipe and drain electrode connect ground terminal; Phase-locked circuit comprises the first phase inverter and the 2nd phase inverter, the input terminus of the first phase inverter and the output terminal of the 2nd phase inverter connect between the grid of the 5th MOS pipe and the drain electrode of the 3rd MOS pipe respectively, between the grid that the output terminal of the first phase inverter and the input terminus of the 2nd phase inverter are connected to a described MOS pipe and the grid of the 4th MOS pipe.
Preferably, a described MOS pipe and described 5th MOS pipe are PMOS, described 2nd MOS pipe,
Described 3rd MOS pipe and described 4th MOS pipe are NMOS tube.
Preferably, being connected with the first standby circuit between the grid of a described MOS pipe and source electrode, first is attached
Add a circuit PMOS at least in parallel.
Preferably, being connected with the 2nd standby circuit between the grid of described 3rd MOS pipe and source electrode, the 2nd is attached
Add the few NMOS tube in parallel of circuit.
Preferably, described output terminal is connected with time delay circuit, and time delay circuit comprises the 3rd phase inverter, the 4th phase inverter and the 5th phase inverter mutually connected.
A kind of zero-power voltage detecting circuit of the present invention adopts multiple MOS to manage the detection circuit with phaselocked loop composition to detect the change of input supply voltage, and can stop detecting the work of circuit after voltage of supply reaches the working power of unicircuit, thus reach the function of zero-power; The unicircuit that meets that the time delay circuit of input terminus setting is further reaches, at power supply, the requirement that operating voltage is work.
Accompanying drawing explanation
Fig. 1 is the schematic circuit of voltage compare sample circuit in prior art.
Fig. 2 is the schematic circuit of the zero-power voltage detecting circuit of the present invention.
Embodiment
As follows by reference to the accompanying drawings, the application's scheme is further described:
As shown in Figure 2, a kind of zero-power voltage detecting circuit, comprising power input Vcc, output end vo ut, ground terminal Vgnd and voltage time delay detection circuit, this detection circuit comprises a MOS pipe N1, the 2nd MOS pipe N2, the 3rd MOS pipe N3, the 4th MOS pipe N4, the 5th MOS pipe N5 and phase-locked circuit.
The grid of the one MOS pipe N1 and the grid junction circuit output end vo ut of the 4th MOS pipe N4, a MOS pipe N1 source electrode connects the drain electrode pole of drain electrode connection the 2nd MOS pipe N2 of power input Vcc, a MOS pipe N1; The source electrode of the 2nd MOS pipe N2 connects the grid of grid connection the 3rd MOS pipe N3 of ground terminal Vgnd, the 2nd MOS pipe N2; The source electrode of the 3rd MOS pipe N3 connects ground terminal Vgnd, and its drain electrode connects the grid of the 5th MOS pipe N5; The source electrode of the 5th MOS pipe N5 and drain electrode connect power input Vcc, and the source electrode of the 4th MOS pipe N4 and drain electrode connect ground terminal Vgnd; A MOS pipe N1 and described 5th MOS pipe N5 in the present embodiment are PMOS, and the 2nd MOS pipe N2, the 3rd MOS pipe N3 and the 4th MOS pipe N4 are NMOS tube.
Phase-locked circuit comprises the first phase inverter D1 and the 2nd phase inverter D2, the input terminus 11 of the first phase inverter D1 and the output terminal 22 of the 2nd phase inverter D2 are connected between the grid of the 5th MOS pipe N5 and the drain electrode of the 3rd MOS pipe N3, between the grid that the output terminal 12 of the first phase inverter D1 and the input terminus 21 of the 2nd phase inverter D2 are connected to a described MOS pipe N1 and the grid of the 4th MOS pipe N4.
Further, in order to prevent the MOS pipe N1 from causing circuit can not work due to fault, the
Being connected with the first standby circuit between the grid of one MOS pipe N1 and source electrode, the first standby circuit PMOS at least in parallel, the first standby circuit in the present embodiment comprises the PMOS N11 and N12 of two series connection.
Further, in order to prevent the 3rd MOS pipe N3 from causing circuit can not work due to fault, institute
Stating and be connected with the 2nd standby circuit between the grid of the 3rd MOS pipe N3 and source electrode, the few NMOS tube in parallel of the 2nd standby circuit, the first standby circuit in the present embodiment comprises the NMOS tube N31 and N32 of two series connection.
Further, in order to meet the requirement that unicircuit works when power supply reaches operating voltage, described output end vo ut is connected with time delay circuit, and time delay circuit comprises the 3rd phase inverter D3, the 4th phase inverter D4 and the 5th phase inverter D5 of series connection mutually.
A kind of zero-power voltage detecting circuit of the present invention adopts multiple MOS to manage the detection circuit with phaselocked loop composition to detect the change of input supply voltage, and can stop detecting the work of circuit after voltage of supply reaches the working power of unicircuit, thus reach the function of zero-power; The unicircuit that meets that the time delay circuit of input terminus setting is further reaches, at power supply, the requirement that operating voltage is work.
Above-mentioned preferred implementation should be considered as the illustration of the application's scheme implementation mode, all identical with the application's scheme, approximate or make based on this technology deduction, replacement, improvement etc., the protection domain of this patent all should be considered as.
Claims (5)
1. a zero-power voltage detecting circuit, comprise power input, output terminal, ground terminal and voltage time delay detection circuit, it is characterised in that: described detection circuit comprises a MOS pipe, the 2nd MOS pipe, the 3rd MOS pipe, the 4th MOS pipe, the 5th MOS pipe and phase-locked circuit; The grid of the one MOS pipe and the grid junction circuit output terminal of the 4th MOS pipe, a MOS pipe source electrode connects power input, and the drain electrode of a MOS pipe connects the drain electrode pole of the 2nd MOS pipe; The source electrode of the 2nd MOS pipe connects ground terminal, and the grid of the 2nd MOS pipe connects the grid of the 3rd MOS pipe; The source electrode of the 3rd MOS pipe connects ground terminal, and its drain electrode connects the grid of the 5th MOS pipe; The source electrode of the 5th MOS pipe and drain electrode connect power input, and the source electrode of the 4th MOS pipe and drain electrode connect ground terminal; Phase-locked circuit comprises the first phase inverter and the 2nd phase inverter, the input terminus of the first phase inverter and the output terminal of the 2nd phase inverter connect between the grid of the 5th MOS pipe and the drain electrode of the 3rd MOS pipe respectively, between the grid that the output terminal of the first phase inverter and the input terminus of the 2nd phase inverter are connected to a described MOS pipe and the grid of the 4th MOS pipe.
2. a kind of zero-power voltage detecting circuit according to claim 1, it is characterised in that: described in
One MOS pipe and described 5th MOS pipe are PMOS, and described 2nd MOS pipe, described 3rd MOS pipe and described 4th MOS pipe are NMOS tube.
3. a kind of zero-power voltage detecting circuit according to claim 2, it is characterised in that: described in
It is connected with the first standby circuit, the first standby circuit PMOS at least in parallel between the grid of the one MOS pipe and source electrode.
4. a kind of zero-power voltage detecting circuit according to claim 2, it is characterised in that: described in
The 2nd standby circuit it is connected with, the few NMOS tube in parallel of the 2nd standby circuit between the grid of the 3rd MOS pipe and source electrode.
5. a kind of zero-power voltage detecting circuit according to claim 3 or 4, it is characterised in that: described output terminal is connected with time delay circuit, and time delay circuit comprises the 3rd phase inverter of series connection mutually, the 4th phase inverter and the 5th phase inverter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610039075.XA CN105675955B (en) | 2016-01-21 | 2016-01-21 | Zero-power-consumption voltage detection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610039075.XA CN105675955B (en) | 2016-01-21 | 2016-01-21 | Zero-power-consumption voltage detection circuit |
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| Publication Number | Publication Date |
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| CN105675955A true CN105675955A (en) | 2016-06-15 |
| CN105675955B CN105675955B (en) | 2018-08-10 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201610039075.XA Active CN105675955B (en) | 2016-01-21 | 2016-01-21 | Zero-power-consumption voltage detection circuit |
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| WO2007012993A2 (en) * | 2005-07-28 | 2007-02-01 | Koninklijke Philips Electronics N.V. | Transistor bulk control for compensating frequency and/or process variations |
| CN101414748A (en) * | 2007-10-19 | 2009-04-22 | 深圳迈瑞生物医疗电子股份有限公司 | Method for starting control circuit and protecting power supply control chip |
| CN101499644A (en) * | 2008-02-02 | 2009-08-05 | 华润矽威科技（上海）有限公司 | Under-voltage protection circuit with low starting current |
| CN201345613Y (en) * | 2008-12-18 | 2009-11-11 | 比亚迪股份有限公司 | Voltage adjusting device for load starting |
| CN202142841U (en) * | 2011-06-24 | 2012-02-08 | 广州市君盘实业有限公司 | Switch power supply output short circuit protective circuit |
| CN102710242A (en) * | 2012-06-17 | 2012-10-03 | 湖南华宽通电子科技有限公司 | On-chip power-on reset detection circuit applied to high-frequency phase locked loop (PLL) |
| CN103716023A (en) * | 2013-12-03 | 2014-04-09 | 北京中电华大电子设计有限责任公司 | Power-on reset circuit with ultra-low power consumption |
| CN104122971A (en) * | 2013-04-29 | 2014-10-29 | 鸿富锦精密电子(天津)有限公司 | Power circuit |
| CN104253529A (en) * | 2013-06-25 | 2014-12-31 | 无锡华润上华半导体有限公司 | Starting circuit of power supply management chip and power supply management chip |
| CN204190734U (en) * | 2014-11-05 | 2015-03-04 | 百利通科技（扬州）有限公司 | A kind of electrify restoration circuit |
-
2016
- 2016-01-21 CN CN201610039075.XA patent/CN105675955B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2007012993A2 (en) * | 2005-07-28 | 2007-02-01 | Koninklijke Philips Electronics N.V. | Transistor bulk control for compensating frequency and/or process variations |
| CN101414748A (en) * | 2007-10-19 | 2009-04-22 | 深圳迈瑞生物医疗电子股份有限公司 | Method for starting control circuit and protecting power supply control chip |
| CN101499644A (en) * | 2008-02-02 | 2009-08-05 | 华润矽威科技（上海）有限公司 | Under-voltage protection circuit with low starting current |
| CN201345613Y (en) * | 2008-12-18 | 2009-11-11 | 比亚迪股份有限公司 | Voltage adjusting device for load starting |
| CN202142841U (en) * | 2011-06-24 | 2012-02-08 | 广州市君盘实业有限公司 | Switch power supply output short circuit protective circuit |
| CN102710242A (en) * | 2012-06-17 | 2012-10-03 | 湖南华宽通电子科技有限公司 | On-chip power-on reset detection circuit applied to high-frequency phase locked loop (PLL) |
| CN104122971A (en) * | 2013-04-29 | 2014-10-29 | 鸿富锦精密电子(天津)有限公司 | Power circuit |
| CN104253529A (en) * | 2013-06-25 | 2014-12-31 | 无锡华润上华半导体有限公司 | Starting circuit of power supply management chip and power supply management chip |
| CN103716023A (en) * | 2013-12-03 | 2014-04-09 | 北京中电华大电子设计有限责任公司 | Power-on reset circuit with ultra-low power consumption |
| CN204190734U (en) * | 2014-11-05 | 2015-03-04 | 百利通科技（扬州）有限公司 | A kind of electrify restoration circuit |
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| CN105675955B (en) | 2018-08-10 |
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