CN105656592A - Ethercat communication system master station and communication method - Google Patents
Ethercat communication system master station and communication method Download PDFInfo
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- CN105656592A CN105656592A CN201511031363.2A CN201511031363A CN105656592A CN 105656592 A CN105656592 A CN 105656592A CN 201511031363 A CN201511031363 A CN 201511031363A CN 105656592 A CN105656592 A CN 105656592A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
- H04L12/40019—Details regarding a bus master
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
Abstract
The invention provides an EtherCAT communication system master station and a communication method. The master station comprises a main processing module, an FPGA and an Ethernet transceiver; the main processing module comprises a PDO interactive unit, and the FPGA comprises a PDO transceiver unit, a distribution clock unit and a physical layer control unit; wherein the clock distribution unit is used for realizing the clock synchronization of a movement controller and a servo slave station according to a clock signal of the FPGA; the data transceiver unit is used for packaging slave station data from the PDO interactive unit into an EtherCAT data frame, depackaging the EtherCAT data frame from the physical layer control unit and sending the same to the PDO interactive unit according to a communication period; and the physical layer control unit is used for realizing the full duplex transceiving of the EtherCAT data frame and sending a distribution clock message. According to the EtherCAT communication system master station provided by the invention, the clock synchronization of the movement controller and the servo slave station is realized by the hardware of the FPGA, periodic data transceiving is realized accordingly, and the synchronous communication of the master station and the slave station can be accurately realized.
Description
Technical field
The present invention relates to the EtherCAT communications field, more particularly, it relates to a kind of EtherCAT communication system main website and communication means.
Background technology
EtherCAT (Ethernet auto-control technology, it is called for short ECAT) it is the field bus system of an open architecture based on Ethernet, with " onthefly " communication mode that it is exclusive, make communications data frame through each website, when Frame does not stop, processing the data of respective site, thus significantly reducing data processing time, shortening communication cycle. Synchronization mechanism plus its distribution clock (DistributeClock, DC) so that EtherCAT is widely used at a high speed, high-precision motion control field.
EtherCAT slave station is carried out from station control (ESC) by EtherCAT. And main website does not have special ASIC (ApplicationSpecificIntegratedCircuits, special IC), EtherCAT main website is generally by the pure software operated in operating system (Windows, Linux, VxWorks etc.), and combined standard Ethernet card drives and realizes.
In actual applications, EtherCAT main website often operates in motion controller one end, motion controller can produce the data of period planning, and can these data be passed through EtherCAT main website and send in real time to each servo slave station, and this is the key factor of the control performance affecting this control system. Therefore the net synchronization capability of the real-time of EtherCAT main website and main website and slave station, at a high speed, high-precision motor control, it is critical that.
For realizing the real-time synchronization of EtherCAT main website and servo slave station, the cycle interruption clock of motion controller must be Tong Bu with the distribution clock (DC) of all servo slave stations, otherwise motion controller period planning multi-axial Simultaneous motion (such as moving interpolation) data at server-side it cannot be guaranteed that be executed synchronously. So, control accuracy is not just known where to begin.
Traditional EtherCAT main website is based on the pure software framework of operating system OS (OperatingSystem). It is extremely complex due to the scheduling of operating system multitask and is non real-time, so wanting the EtherCAT real-time task performing below 1ms on an operating system, it is necessary to stamp real-time patch with operating system supplier depth cooperation (such as Windows) or to operating system (such as Linux etc.). Such as provide master clock (ClockM) by the real-time patch RTPatch intervalometer (Timer) produced for EtherCAT communication, as shown in Figure 1, this master clock is directly set to reference clock slave station SL0 (Slave0) as its distribution clock by EtherCAT main website, and servo slave station thereafter synchronizes with the distribution clock of reference clock for reference again. Delay variation is there is due to after driver that the transmitting-receiving packet rows of EtherCAT main website is the Ethernet Adaptation Unit (EthernetAdapter) being operated by under system, this is introduced directly into a shake will necessarily to the distribution clock of whole EtherCAT network, thus the net synchronization capability destroyed between servo slave station, therefore traditional EtherCAT main website scheme cannot ensure that the cycle interruption clock of motion controller reaches Tong Bu with the distribution clock of servo slave station.
But, be no matter with operating system supplier depth cooperation or or beat real-time patch for operating system, all need to be modified the scheduling of operating system underlying task, thus improving the real-time of EtherCAT master tasks. But the stability of operating system will certainly be brought very big challenge and risk by this. And even by such Real-Time Improvement, it is desirable to obtaining the real-time performance of below 500us, be also that the CPU needing performance superpower could realize, the cost of system certainly will be impacted again by this.
Summary of the invention
The technical problem to be solved in the present invention is in that, the problem that in communicating for above-mentioned EtherCAT, real-time performance is poor, relatively costly, it is provided that a kind of EtherCAT communication system main website and communication means.
This invention address that the technical scheme of above-mentioned technical problem is to provide a kind of EtherCAT communication system main website, including main processing block, FPGA and ethernet transceiver, and by described ethernet transceiver connection reference clock slave station and servo slave station; Described main processing block includes PDO interactive unit, and described FPGA includes PDO Transmit-Receive Unit, distribution clock unit and physical layer control unit; Wherein: described distribution clock unit, generating distribution clock message for the clock signal period according to FPGA, the clock to realize motion controller clock and servo slave station synchronizes; Described data transceiving unit, for being encapsulated as EtherCAT Frame according to communication cycle and the EtherCAT Frame solution from physical layer control unit being honored as a queen and send PDO interactive unit to by the slave station interaction data from PDO interactive unit; Described physical layer control unit, realizes the full duplex transmitting-receiving of EtherCAT Frame and the transmission of distribution clock message for controlling ethernet transceiver.
In EtherCAT of the present invention communication system main website, described distribution clock unit includes time delay and arranges unit, clock transmitting element and start control unit, wherein: described time delay arranges unit, to the transmission delay of reference clock slave station and time offset and result of calculation is arranged reference clock slave station for calculating main website; Described clock transmitting element, for being regularly sent to each servo slave station by the clock of FPGA;Described startup control unit, for after main website is Tong Bu with the clock of servo slave station, the synchronizing signal calculating each servo slave station starts the IE time of time and main website, and the synchronizing signal startup time of described servo slave station alignd in phase place with the IE time of main website.
In EtherCAT of the present invention communication system main website, the main processing block of described main website includes document analysis unit, station scans unit, state machine administrative unit, dispensing unit and mailbox communication unit, described FPGA includes SDO Transmit-Receive Unit, and described SDO Transmit-Receive Unit for realizing the data interaction of document analysis unit, station scans unit, state machine administrative unit, dispensing unit and mailbox communication unit and each servo slave station by physical layer control unit.
In EtherCAT of the present invention communication system main website, described main website includes two ethernet transceivers, and one of them ethernet transceiver is for carrying out the transmitting-receiving of data message, another ethernet transceiver for realizing main website ring redundancy, described physical layer control unit includes Port Management unit, and this Port Management unit is used for realizing port connection state and ring redundancy process.
In EtherCAT of the present invention communication system main website, described physical layer control unit includes packet filtering unit, is used for filtering non-EtherCAT message.
The present invention also provides for a kind of EtherCAT communication system master station communication method, and described main website includes main processing block, FPGA and ethernet transceiver, and is connected reference clock slave station and servo slave station by described ethernet transceiver; Said method comprising the steps of:
A () described FPGA sends distribution clock message by ethernet transceiver to servo slave station according to the clock signal period of this FPGA, the clock to realize motion controller clock and servo slave station synchronizes;
B PDO from main processing block is encapsulated as EtherCAT Frame according to communication cycle and the EtherCAT Frame solution from physical layer control unit is honored as a queen and sends main processing block to by () described FPGA;
C () described FPGA controls ethernet transceiver and realizes the full duplex transmitting-receiving of EtherCAT Frame.
In EtherCAT communication system master station communication method of the present invention, described step (a) including:
(a1) described FPGA calculates main website and to the transmission delay of reference clock slave station and time offset and result of calculation arranges reference clock slave station;
(a2) clock of FPGA is sent to each servo slave station by described FPGA timing;
(a3) described FPGA is after main website is Tong Bu with the clock of servo slave station, the synchronizing signal calculating each servo slave station starts the IE time of time and main website, and the synchronizing signal startup time of described servo slave station alignd in phase place with the IE time of main website.
In EtherCAT communication system master station communication method of the present invention, described method also includes:
Described FPGA realizes the transmitting-receiving of SDO between main website and slave station by ethernet transceiver;
Described main processing block describes document analysis according to the FPGA slave station equipment received and goes out the slave station information relevant to configuration;
Described main processing block is scanned by the FPGA all clock reference slave stations to being connected in EtherCAT network and servo slave station, obtains the device descriptive information of online slave station number and each slave station;
Described main processing block completes the application layer state handover management of each slave station by FPGA;
Slave station is carried out relevant configuration by FPGA by described main processing block;
Described main processing block realizes mailbox communication by FPGA with servo slave station.
In EtherCAT communication system master station communication method of the present invention, described main website includes two ethernet transceivers, and one of them ethernet transceiver is for carrying out the transmitting-receiving of data message, another ethernet transceiver for realizing main website ring redundancy, described method includes: described FPGA carries out port connection state, ring redundancy processes.
In EtherCAT communication system master station communication method of the present invention, described method includes: described FPGA filters non-EtherCAT message.
EtherCAT communication system main website of the present invention and communication means, motion controller is realized Tong Bu with the clock of servo slave station by the hardware of FPGA, and the transmitting-receiving of property performance period data accordingly, module is increased without the kernel sky in operating system, also without increasing real-time patch, accurate master-salve station synchronous communication can be realized.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of EtherCAT communications system embodiment of the present invention.
Fig. 2 is the module diagram of EtherCAT communication system in Fig. 1.
Fig. 3 is the schematic diagram that in Fig. 1, EtherCAT communication system clock synchronizes.
Detailed description of the invention
In order to make the purpose of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated. Should be appreciated that specific embodiment described herein is only in order to explain the present invention, is not intended to limit the present invention.
As shown in Figure 1-2, being the schematic diagram of EtherCAT of the present invention communication system main website embodiment, it can replace the main website in existing EtherCAT communication system, to carry out servo slave station control. This EtherCAT communication system main website includes main processing block 10, FPGA (PLD) 20 and ethernet transceiver (EthernetPHY) 30, and connects reference clock slave station and servo slave station by ethernet transceiver 30. Above-mentioned main processing block 10 specifically can adopt ARM chip operation to have operating system (can include operating system user's space and operating system nucleus space), and this main processing block 10 is connected with FPGA20 by Peripheral Interface (PeripheralInterface).
In the present embodiment, main processing block 10 realizes application layer ECATAL (EtherCATApplicationLayer) function at operating system user's space, and FPGA20 completes data link layer ECATDLL (EtherCATDataLinkLayer) function of EtherCAT communication system main website and physical layer ECATPL (EtherCATPhysicalLayer) manages function. One road ethernet transceiver 30 connects EtherCAT slave station by RJ45 port, carries out the transmitting-receiving of data message, and an other road ethernet transceiver 30 uses as main website ring redundancy.
Main processing block 10 includes the PDO interactive unit 11 operating in application layer, FPGA20 includes operating in the PDO Transmit-Receive Unit 22 of data link layer, distribution clock unit 21 and operating in the physical layer control unit 24 of physical layer, and above-mentioned PDO interactive unit 11, PDO Transmit-Receive Unit 22, distribution clock unit 21 and physical layer control unit 24 realize in combinations with corresponding software.
Distribution clock unit 21 periodically generates distribution clock message for the hardware clock signal (but not clock signal of main processing block 10) according to FPGA20, and the clock to realize motion controller clock and servo slave station synchronizes.Specifically, distribution clock unit 21 include time delay arrange unit, clock transmitting element and start control unit. As it is shown on figure 3, time delay arranges unit in distribution clock unit 21 initialization procedure, measuring and calculating main website is to the transmission delay of reference clock slave station SL0 and time offset, and result of calculation arranges reference clock slave station SL0; Data link layer (DLL) the clock ClockM of FPGA20 is sent to each servo slave station SL1 by the timing of clock transmitting element, SL2, ..., SLN (N is integer), utilize EtherCAT distribution clock synchronization mechanism, it is ensured that on all servos slave station distribution clock (DC) and master clock stringent synchronization; Start control unit master clock and servo are Tong Bu from station clock after, the interruption (Interrupt) of the synchronizing signal startup time and main website that calculate each servo slave station starts the time, and ensures that all slave station synchronizing signals startup time alignd in phase place with the main website IE time.
By the distribution clock unit 21 of the hardware clock based on FPGA20, the period planning data that motion controller is made according to above-mentioned main website interrupt signal just can be synchronized to perform from standing in same period by all servos, it is achieved at a high speed, the control of high-precision high net synchronization capability.
PDO interactive unit 11, for generating PDO data according to application layer task call, including I/O data, controls data, status data etc., and processes the feedback data from servo slave station for application layer task call. PDO data from PDO (ProcessDataObject) interactive unit 11 are encapsulated as EtherCAT Frame based on the communication cycle (namely based on the hardware clock of FPGA20) of distribution clock unit 21 and the EtherCAT Frame solution from physical layer control unit 24 are honored as a queen and send PDO interactive unit 11 to by PDO Transmit-Receive Unit 22; Physical layer control unit 24 realizes the full duplex transmitting-receiving of EtherCAT Frame and the transmission of distribution clock message for controlling ethernet transceiver 30.
EtherCAT main website passes through above-mentioned demixing technology, is placed on by PDO transmission-receiving function the highest for requirement of real-time in EtherCA physical layer in FPGA20 and realizes, utilizes the hardware of FPGA20 itself to ensure the EtherCAT master station communication rigors to real-time in real time.
Additionally, also realize in FPGA20 due to physical layer management function (i.e. physical layer control unit 24), eliminate the operating system driving to ethernet transceiver 30 to dispatch, thus eliminating the delay variation problem of EtherCAT data message transmitting-receiving, eliminate EtherCAT data message and send the shake in cycle, make EtherCAT communication system obtain stable distribution clock net synchronization capability. Owing to real-time data link layer in FPGA20 is protected, and the application layer of EtherCAT main website can run directly in the user's space of operating system of main processing block 10, without increasing module or real-time patch at kernel spacing, when obtain superior strong time, the load of operating system can also be reduced to greatest extent, it is ensured that the reliable and stable operation of system.
The main processing block 10 of above-mentioned main website also includes document analysis unit 13, station scans unit 12, state machine administrative unit 15, dispensing unit 14 and mailbox communication unit 16, correspondingly, FPGA20 includes SDO (ServiceDataObject) Transmit-Receive Unit 23, this SDO Transmit-Receive Unit 23 is for realizing document analysis unit 13 by physical layer control unit 24, station scans unit 12, state machine administrative unit 15, the data interaction of dispensing unit 14 and mailbox communication unit 16 and each servo slave station, namely document analysis unit 13 is received, station scans unit 12, state machine administrative unit 15, the data message of dispensing unit 14 and mailbox communication unit 16, it is subsequently forwarded to physical layer control unit 24, receive the data message that physical layer control unit 24 returns simultaneously, the correlation unit of notice application layer reads.
Specifically, document analysis unit 13 parses from the device description file (XML file) of EtherCAT slave station and configures relevant slave station information, as: supplier ID (VendorID), product code (ProductCode) and process data PDO (ProcessDataObject) mapping etc. Station scans unit 12 is scanned for realizing the main website all slave stations to being connected in EtherCAT network, obtains the device descriptive information of online slave station number and each slave station. State machine (FiniteStateMachine, FSM) administrative unit 15 has been used for the application layer state handover management of each slave station, comprises the management of four kinds of states: initialize (INIT), pre-operation (PREOP), safety operation (SAFEOP), mode of operation (OP). Dispensing unit 14 is for, after entering PREOP state at slave station, carrying out relevant configuration according to the operator scheme that user wants to EtherCAT slave station, such as communication cycle, synchronous mode, DC cycle, PDO mapping etc. Mailbox communication unit 16 is used for realizing EtherCAT and services the read-write of data SDO (ServiceDataObject), depending on main website specification, can partly or entirely comprise following application layer protocol: CoE (CANopenoverEtherCAT), SoE (ServooverEtherCAT), FoE (FileoverEtherCAT), EoE (EthernetoverEtherCAT), AoE (ADSoverEtherCAT), VoE (VendoroverEtherCAT).
Especially, above-mentioned physical layer control unit 24 may also include packet filtering unit, is used for filtering non-EtherCAT message.
The present invention also provides for a kind of EtherCAT communication means, and wherein the main website in EtherCAT communication system includes main processing block, FPGA and ethernet transceiver, and is connected reference clock slave station and servo slave station by ethernet transceiver; The method comprises the following steps:
A () FPGA sends distribution clock message by ethernet transceiver to servo slave station according to the clock signal period of this FPGA, the clock to realize motion controller clock and servo slave station synchronizes.
This step specifically comprises the steps that FPGA calculates main website and to the transmission delay of reference clock slave station and time offset and result of calculation arranges reference clock slave station; The clock of FPGA is sent to each servo slave station by FPGA timing; FPGA is after main website is Tong Bu with the clock of servo slave station, and the synchronizing signal calculating each servo slave station starts the IE time of time and main website, and the synchronizing signal startup time of servo slave station alignd in phase place with the IE time of main website.
B PDO from main processing block is encapsulated as EtherCAT Frame according to communication cycle and the EtherCAT Frame solution from physical layer control unit is honored as a queen and sends main processing block to by () FPGA;
C () FPGA controls ethernet transceiver and realizes the full duplex transmitting-receiving of EtherCAT Frame.
In above-mentioned EtherCAT communication means, except PDO data transmit-receive, may also include that FPGA realizes the transmitting-receiving of SDO between main website and slave station by ethernet transceiver; Main processing block describes according to the FPGA slave station equipment received and parses in file and configure relevant slave station information; Main processing block is scanned by the FPGA all clock reference slave stations to being connected in EtherCAT network and servo slave station, obtains the device descriptive information of online slave station number and each slave station; Main processing block completes the application layer state handover management of each slave station by FPGA;Slave station is carried out relevant configuration by FPGA by main processing block; Main processing block realizes mailbox communication by FPGA with servo slave station.
The above; being only the present invention preferably detailed description of the invention, but protection scope of the present invention is not limited thereto, any those familiar with the art is in the technical scope that the invention discloses; the change that can readily occur in or replacement, all should be encompassed within protection scope of the present invention. Therefore, protection scope of the present invention should be as the criterion with scope of the claims.
Claims (10)
1. an EtherCAT communication system main website, it is characterised in that: include main processing block, FPGA and ethernet transceiver, and connected reference clock slave station and servo slave station by described ethernet transceiver; Described main processing block includes PDO interactive unit, and described FPGA includes PDO Transmit-Receive Unit, distribution clock unit and physical layer control unit; Wherein: described distribution clock unit, generating distribution clock message for the clock signal period according to FPGA, the clock to realize motion controller clock and servo slave station synchronizes; Described data transceiving unit, for being encapsulated as EtherCAT Frame according to communication cycle and the EtherCAT Frame solution from physical layer control unit being honored as a queen and send PDO interactive unit to by the slave station interaction data from PDO interactive unit; Described physical layer control unit, realizes the full duplex transmitting-receiving of EtherCAT Frame and the transmission of distribution clock message for controlling ethernet transceiver.
2. EtherCAT according to claim 1 communication system main website, it is characterized in that: described distribution clock unit includes time delay and arranges unit, clock transmitting element and start control unit, wherein: described time delay arranges unit, to the transmission delay of reference clock slave station and time offset and result of calculation is arranged reference clock slave station for calculating main website; Described clock transmitting element, for being regularly sent to each servo slave station by the clock of FPGA; Described startup control unit, for after main website is Tong Bu with the clock of servo slave station, the synchronizing signal calculating each servo slave station starts the IE time of time and main website, and the synchronizing signal startup time of described servo slave station alignd in phase place with the IE time of main website.
3. EtherCAT according to claim 1 communication system main website, it is characterized in that: the main processing block of described main website includes document analysis unit, station scans unit, state machine administrative unit, dispensing unit and mailbox communication unit, described FPGA includes SDO Transmit-Receive Unit, and described SDO Transmit-Receive Unit for realizing the data interaction of document analysis unit, station scans unit, state machine administrative unit, dispensing unit and mailbox communication unit and each servo slave station by physical layer control unit.
4. EtherCAT according to claim 1 communication system main website, it is characterized in that: described main website includes two ethernet transceivers, and one of them ethernet transceiver is for carrying out the transmitting-receiving of data message, another ethernet transceiver for realizing main website ring redundancy, described physical layer control unit includes Port Management unit, and this Port Management unit is used for realizing port connection state and ring redundancy process.
5. EtherCAT according to claim 1 communication system main website, it is characterised in that: described physical layer control unit includes packet filtering unit, is used for filtering non-EtherCAT message.
6. an EtherCAT communication system master station communication method, it is characterised in that: described main website includes main processing block, FPGA and ethernet transceiver, and is connected reference clock slave station and servo slave station by described ethernet transceiver; Said method comprising the steps of:
A () described FPGA sends distribution clock message by ethernet transceiver to servo slave station according to the clock signal period of this FPGA, the clock to realize motion controller clock and servo slave station synchronizes;
B PDO from main processing block is encapsulated as EtherCAT Frame according to communication cycle and the EtherCAT Frame solution from physical layer control unit is honored as a queen and sends main processing block to by () described FPGA;
C () described FPGA controls ethernet transceiver and realizes the full duplex transmitting-receiving of EtherCAT Frame.
7. EtherCAT communication system master station communication method according to claim 6, it is characterised in that: described step (a) including:
(a1) described FPGA calculates main website and to the transmission delay of reference clock slave station and time offset and result of calculation arranges reference clock slave station;
(a2) clock of FPGA is sent to each servo slave station by described FPGA timing;
(a3) described FPGA is after main website is Tong Bu with the clock of servo slave station, the synchronizing signal calculating each servo slave station starts the IE time of time and main website, and the synchronizing signal startup time of described servo slave station alignd in phase place with the IE time of main website.
8. EtherCAT communication system master station communication method according to claim 6, it is characterised in that: described method also includes:
Described FPGA realizes the transmitting-receiving of SDO between main website and slave station by ethernet transceiver;
Described main processing block describes document analysis according to the FPGA slave station equipment received and goes out the slave station information relevant to configuration;
Described main processing block is scanned by the FPGA all clock reference slave stations to being connected in EtherCAT network and servo slave station, obtains the device descriptive information of online slave station number and each slave station;
Described main processing block completes the application layer state handover management of each slave station by FPGA;
Slave station is carried out relevant configuration by FPGA by described main processing block;
Described main processing block realizes mailbox communication by FPGA with servo slave station.
9. EtherCAT communication system master station communication method according to claim 6, it is characterized in that: described main website includes two ethernet transceivers, and one of them ethernet transceiver is for carrying out the transmitting-receiving of data message, another ethernet transceiver for realizing main website ring redundancy, described method includes: described FPGA carries out port connection state, ring redundancy processes.
10. EtherCAT communication system master station communication method according to claim 6, it is characterised in that: described method includes: described FPGA filters non-EtherCAT message.
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