CN105656450A

CN105656450A - Digital lowpass filtering method and apparatus for integer arithmetic

Info

Publication number: CN105656450A
Application number: CN201511029759.3A
Authority: CN
Inventors: 郑晓江
Original assignee: BEIJING HICONICS DRIVE TECHNOLOGY CO LTD
Current assignee: Beijing Kang Kang Xin Polytron Technologies Inc
Priority date: 2015-12-31
Filing date: 2015-12-31
Publication date: 2016-06-08
Anticipated expiration: 2035-12-31
Also published as: CN105656450B

Abstract

The invention discloses a digital lowpass filtering apparatus for integer arithmetic. Data x (n), y (n - 1) and r (n - 1) are input to an accumulator A, the accumulator A calculates A = x (n) - y(n - 1) + r (n - 1); data A and h are input to a divider B, and the divider B calculates B = A/h; data B and y (n-1) are input to an accumulator C, and the accumulator calculates C = y (n-1) + B; and data C are used as the current filtering output y(n) and is stored for the next operation. The data x (n), y (n - 1) and r (n - 1) are input to the accumulator A, and the accumulator A calculates A = x (n) - y(n - 1) + r (n - 1); and the data A and h are input to the logic shifter B, the logic shifter B calculates B= A/h, and the current remainder of the B outputs r(n), and r(n) is stored for the next operation.

Description

The digital low-pass filtering method of integer arithmetic and device

Technical field

The present invention relates to the digital low-pass filtering method of integer arithmetic and device.

Background technology

In digital signal processing, and some physical quantity (as: voltage, electric current) before entering mathematical model, it is required for " stability " process, namely signal is filtered, to remove interference. For reducing the impact on signal, during filtering, to reduce time delay or displacement as far as possible. When the Interruption treatment mechanism using DSP or corresponding single-chip microcomputer processes, owing to the break period is adjustable, cut-off frequency is difficult to pre-determine. If accurately to process cut-off frequency, it is necessary to the break period is relevant to filter factor. Generally need not accurately process cut-off frequency, as long as meeting onsite application requirement; Also have some to be also required to " stability " before entering display for physical quantitys of showing to process, for instance, it is contemplated that the speed that the eyes of people can recognise that is at 25 stacks/below the second, and too fast for preventing from updating, this kind of signal is also required to filtering. This kind of process, generally adopts first-order low-pass ripple algorithm to be filtered, and its algorithm logic expression formula is as follows:

Y (n)={ x (n) y (n-1) }/h+y (n-1)

Wherein,

Y (n): this filters output; X (n): this filters input; Y (n-1): filtering output last time; H: filter factor (number more than 1).

From above formula, if the variable quantity of signal less (x (n) y (n-1)), the DSP of integer arithmetic or corresponding single-chip microcomputer are when computing, restriction because of figure place, variable quantity is given up by truncation, output is caused forever to rest on y (n-1), the problem that will not change.

As: h=4;

As can be seen from the above equation, when inputting (x (n)) relatively output (y (n-1)) and varying more than 4 (| x-y | > 4), output (y (n)) changes, if x (n) is y (n-1) for adding 4, then y (n)=y (n-1) adds 1; If x (n) is y (n-1) for subtracting 4, then y (n)=y (n-1) subtracts 1; It is to say, x (n) changes 4 units, y (n) changes 1 unit; It is slower that x (n) changes the change of very fast y (n); Thus serve the effect of filtering.

But when inputting (x (n)) change relative to output (y (n-1)) less than 4 (| x-y | < 4), the result being divided by with 4 (h) is given up by truncation, cause output y (n) to rest on y (n-1), do not have filter action.

In order to solve this problem, in prior art, all data are first amplified, then Filtering Processing, finally restore.

But amplify and reduction, it is necessary to carry out multiplication and division arithmetic, make the resource of DSP or single-chip microcomputer and time loss amplify and in reduction, affect the normal operation of DSP or single-chip microcomputer.

It is an object of the invention to provide one and can improve operational precision, digital low-pass filtering method and the device of the integer arithmetic of operand can be reduced again.

Summary of the invention

First technical scheme of the present invention is, the digital low-pass filtering method of integer arithmetic, and its algorithm logic expression formula is following formula (1),

Y (n)={ x (n) y (n-1) }/h+y (n-1) (1)

Wherein, y (n): this filters output; X (n): this filters input; Y (n-1): filtering output last time; H: filter factor,

It is a feature of the present invention that in formula (1), introduce variable r, by the algorithm logic expression formula of following formula (2), calculate filtering output y,

Y (n)={ x (n) y (n-1)+r (n-1) }/h+y (n-1) (2)

Wherein, the algorithm logic expression formula of r is following formula (3),

The remainder (3) of r (n)={ x (n) y (n-1)+r (n-1) }/h

R (n): this remainder; R (n-1): last time remainder,

Y, x, h, r are integer,

Including computing y (n) and computing r (n) step.

Second technical scheme is based on the first technical scheme, it is characterised in that the step of computing y (n), including,

Read x (n), y (n-1), r (n-1),

Call accumulator computing A=x (n) y (n-1)+r (n-1);

Read A, h,

Call divider computing B=A/h;

Read B, y (n-1),

Call accumulator computing y (n-1)+B, calculate y (n);

Y (n) exports as this filtering, and for computing next time,

The step of computing r (n), including,

Read x (n), y (n-1), r (n-1)

Call accumulator computing A=x (n) y (n-1)+r (n-1);

Read A, h,

Call the remainder of complementation internalarithmetic A/h, calculate r (n),

R (n) exports as this remainder, and for computing next time.

Second technical scheme is based on the first technical scheme, it is characterised in that described complementation arithmetical unit is logical shift device.

3rd technical scheme is based on the second technical scheme, it is characterised in that described complementation arithmetical unit is logical shift device.

4th technical scheme is based on first to technical scheme any one of the 3rd, it is characterised in that during initial computing, the initial value of y, r is set as 0.

5th technical scheme is the digital low-pass filtering device of integer arithmetic, it is characterized in that, including, calculate first accumulator of A=x (n) y (n-1)+r (n-1), calculate the divider of B=A/h, calculate second accumulator of y (n)=y (n-1)+B, calculate the 3rd accumulator of A=x (n) y (n-1)+r (n-1), calculate the complementation arithmetical unit of the remainder of A/h

Wherein, y (n): this filters output; X (n): this filters input; Y (n-1): filtering output last time; H: filter factor, r (n): this remainder; R (n-1): last time remainder.

6th technical scheme is based on the 5th technical scheme, it is characterised in that described complementation arithmetical unit is logical shift device.

7th technical scheme is based on the 5th or the 6th technical scheme, it is characterised in that the first accumulator, the second accumulator, the 3rd accumulator are when initial computing, and the initial value of y, r is set as 0.

Accompanying drawing explanation

Fig. 1 is the structured flowchart of embodiment of the present invention;

Fig. 2 is the operational flowchart of y in embodiment of the present invention;

Fig. 3 is the operational flowchart of r in embodiment of the present invention;

Fig. 4 is the operational flowchart of y in prior art;

Fig. 5 is the operational flowchart of yf in prior art.

Detailed description of the invention

Before embodiments of the present invention are described, first prior art is illustrated.

For solving the input (x (the n)) change hour relative to output (y (n-1)), the problem that output y (n) is not changed in, the algorithm of prior art is all data first to be amplified, then filter, finally restore, the following is its algorithm logic expression formula, in formula; Introduce new variable yf. Y (n)=[K*x (n)+(H-K) * y (n-1)+(H-K) * yf (n-1)/H]/H (4) yf (n)=[K*x (n-1)+(H-K) * y (n-1)+(H-K) * yf (n-1)/H] %H (5) is wherein

X: input

Y: output (integer)

Yf: output (decimal)

H: filter factor (number more than 1)

K: filtering ratio

H > K > 0

%: tape symbol complementation computing.

Such as H=1024, K=256

Obtained by formula (4)

Y=(x+y*3+yf*3/4)/4

=x/4+y*3/4+yf*3/4/4

Obtained by formula (5)

Yf=(x+y*3+yf*3/4) &3

When arithmetic expression (4), Section 1: x/4, i.e. input (x (n)) takes 1/4th; Section 2: y*3/4, i.e. output (y (n-1)) takes 3/4ths; Section 3: yf*3/4/4, i.e. output decimal (yf (n-1)) takes 3/4ths and carry. By such computing, integer and decimal are all outputed (including filtering), and, fractional part has reflected in the computing of y and the yf of next time, it is therefore prevented that the fractional part caused because of integer arithmetic is lost. In order to convenience of calculation division arithmetic can also use displacement substitution operation, now,

Y=(x+y*3+ (yf*3 > > 2)) > > 2

Ory=(x*256+y*768+ (yf*768 > > 10)) > > 10

Yf=(x+y*3+ (yf*3 > > 2)) &3

Ory=(x*256+y*768+ (yf*768 > > 10)) &1023

Fig. 4, Fig. 5 are the operational flowcharts of y and yf in prior art.

By the flow diagram of Fig. 4,5, existing algorithm needs when calculating y and yf to carry out six multiplication, three divisions or displacement (to the right) and some plus-minus logical operationss. During multiplying, for ensureing operational precision, data type to be put and to be twice; As: during 16 X16 positions, result must be only 32 safe; The speed that the figure place of data type more multicomputer processes is more slow; The memory space taken is more big; Wanting to improve operational efficiency must reasonable utilization multiplication and division.

Below by way of with prior art comparison embodiments of the present invention are illustrated.

Following formula (6) is the algorithm logic expression formula of the y of present embodiment, and following formula (7) is the algorithm logic expression formula of the r of present embodiment, all adopts integer arithmetic.

Y (n)={ x (n) y (n-1)+r (n-1) }/h+y (n-1) (6)

The remainder (7) of r (n)={ x (n) y (n-1)+r (n-1) }/h

R (n): this remainder; R (n-1): last time remainder;

Y (n), x (n), y (n-1), h, r are integer.

Compared with the basic representation of following formula (8), formula introduces variable r in (6), and the remainder that r (n) is { x (n) y (n-1)+r (n-1) }/h, therefore, during arithmetic expression (6), the complementing part being saved joins in computing next time, when solving computing, because of the problem that decimal produced by remainder is lost.

Y (n)={ x (n) y (n-1) }/h+y (n-1) (8)

Wherein, y (n): this filters output; X (n): this filters input; Y (n-1): filtering output last time; H: filter factor.

Hereinafter embodiments of the present invention are illustrated.

Fig. 1 is the structured flowchart of embodiment of the present invention.Data x (n), y (n-1), r (n-1) are input to accumulator A, accumulator A calculate A=x (n)-y (n-1)+r (n-1); Data A and h is input to divider B, divider B calculate B=A/H; Data B and y (n-1) is input to accumulator C, accumulator C calculate C=y (n-1)+B; Data C exports y (n) as this filtering, for computing next time after preservation. When calculating r,

Data x (n), y (n-1), r (n-1) are input to accumulator A, accumulator A calculate A=x (n)-y (n-1)+r (n-1); Data A and h is input to logical shift device B, logical shift device B calculate remainder output r (n) that B=A%H, B are this, for computing next time after preservation. Present embodiment rems, and what adopt is logical shift device, but can use any complementation arithmetical unit.

Fig. 2 is the operational flowchart of y.

Step 1, inputs data: X, Y, R

Step 2, call accumulator A calculate X-Y+R, result in A,

Step 3, obtains A=X-Y+R

Step 4, inputs data: A, H

Step 5, call divider B calculate A/H, result in B,

Step 6, obtains B=A/H

Step 7, inputs data: B, Y

Step 8, call accumulator C calculate Y+B, result in C,

Step 9, obtains C=Y+B; B=A/H; A=X-Y+R

Step 10, result is stored in depositor Y, for output and computing next time, wherein, Y=C=Y+B=Y+ (X-Y+R)/H

Fig. 3 is the operational flowchart of r.

Step 20, inputs data: X, Y, R

Step 21, calls accumulator A and calculates X-Y+R, and result is in A

Step 22, obtains A=X-Y+R

Step 23, inputs data: A, H

Step 24, calling logic shifter B calculates A%H, and result is in B

Step 25, obtains B=A%H

Step 26, result is stored in depositor R, wherein R=B; B=A%H; A=X-Y+R

From the foregoing, it will be observed that in the algorithm of the present invention, for once division arithmetic or logic shift right, a complementation computing, compared with prior art, efficiency is high. Owing to not having non-integer to occur, need not first amplifying, owing to not having multiplying, data type need not be amplified, and improves the processing speed of computer; And the memory space taken also can reduce, can be used in Interruption service routine and call.

Embodiment

In embodiment, input is output current of frequency converter amplitude signal.

Hardware: converter U phase is exported current amplitude circuit and is connected to the A/D conversion entrance of DSP, convert analog signals into the digital signal of integer; Voltage: 0-3V; Corresponding conversion result: 0-4095 (12). The following is process program.

A/D transformation result is set to Iad, as the input of wave filter; The integer part that Iabs exports as wave filter; Iabsf is remainder; It is int type.

Main.c

Initialize:

Iabs=Iabsf=Iad=0;

Interrupt_10ms.c

10 milliseconds of Interruption service routines:

Iabs+=(Iad Iabs+Iabsf) > > 2;

Iabsf=(Iad Iabs+Iabsf) %4.

Same signal formula (4), (5) prior art when processing, program is as follows:

A/D transformation result is set to Iad, as the input of wave filter; The integer part that Iabs exports as wave filter; The fractional part that Iabsf exports as wave filter; It is int type.

Main.c

Initialize:

Iabs=Iabsf=Iad=0;

Interrupt_10ms.c

10 milliseconds of Interruption service routines:

Iabs=(Iabs*768+ ((Iabsf*768) > > 10)+Iad*256) > > 10;

Iabsf=(Iabs*768+ ((Iabs*768) > > 10)+Iad*256) &1023;

Existing algorithm, needs six multiplication, three divisions or displacement (to the right) and some plus-minus logical operationss altogether. For ensureing the precision of multiplying, data type to be put and to be twice, and causes that the speed of computer disposal is more slow; The memory space taken is more big.

Compared with existing algorithm, due to the algorithm for once division of the present invention or move to right, a complementation computing, plus-minus logical operations some, program structure is simple, the speed of service very fast (for once division arithmetic or logic shift right, a complementation computing); Efficiency high (owing to not having multiplying, data type need not be amplified); It is particluarly suitable in Interruption service routine to call.

Below by way of concrete numerical value, the elimination of error is illustrated.

1.Iad=1, calculates:

A) Iabs+=(1 0+0) > > 2; Iabs=0

B) Iabsf=(1 0+0) %4; Iabsf=1

2.Iad=1, calculates:

A) Iabs+=(1 0+1) > > 2; Iabs=0

B) Iabsf=(1 0+1) %4; Iabsf=2

3.Iad=1, calculates:

A) Iabs+=(1 0+2) > > 2; Iabs=0

B) Iabsf=(1 0+2) %4; Iabsf=3

4.Iad=1, calculates:

A) Iabs+=(1 0+3) > > 2; Iabs=1

B) Iabsf=(1 0+3) %4; Iabsf=0

5.Iad=1, calculates:

A) Iabs+=(1 1+0) > > 2; Iabs=1

B) Iabsf=(1 1+0) %4; Iabsf=0

6.Iad=0, calculates:

A) Iabs+=(0 1+0) > > 2; Iabs=1

B) Iabsf=(0 1+0) %4; Iabsf=-1

7.Iad=0, calculates:

A) Iabs+=(0 1-1) > > 2; Iabs=1

B) Iabsf=(0 1-1) %4; Iabsf=-2

8.Iad=0, calculates:

A) Iabs+=(0 1-2) > > 2; Iabs=1

B) Iabsf=(0 1-2) %4; Iabsf=-3

9.Iad=0, calculates:

A) Iabs+=(0 1-3) > > 2; Iabs=0

B) Iabsf=(0 1-3) %4; Iabsf=0

10.Iad=0, calculate:

A) Iabs+=(0 1+0) > > 2; Iabs=0

B) Iabsf=(0 1+0) %4; Iabsf=-1

11.Iad=0, calculate:

A) Iabs+=(0 1+0) > > 2; Iabs=0

B) Iabsf=(0 1+0) %4; Iabsf=-1

12.Iad=0, calculate:

A) Iabs+=(0 1+0) > > 2; Iabs=0

B) Iabsf=(0 1+0) %4; Iabsf=-1

13.Iad=5, calculate:

A) Iabs+=(5 1-3) > > 2; Iabs=0

B) Iabsf=(5 1-3) %4; Iabsf=1

14.Iad=5, calculate:

A) Iabs+=(5 1+1) > > 2; Iabs=1

B) Iabsf=(5 1+1) %4; Iabsf=1

Calculate from above: when Iad is become 1 by 0, (1--4) Iabs=1 after four circulations, be equivalent to point four filtering; Calculating without complementation, after N number of circulation, labs is also equal to zero, and output is still equal to zero, so this is mainly remainder at integration, increases by 1/4th every time, and after four (n-1) individual circulation, output changes; When Iad keeps 1, (4--5) Iabs is constant, and input and output are equal, and output will not change; When Iad is become 0 by 1, (6--9) Iabs=0 after four circulations, correspond again to point four filtering, reduce 1/4th every time, after four circulations, output changes; When Iad keeps 0, (9--12) Iabs is constant, and input and output are equal, and output will not change; When Iad is become 5 by 0, (13--14) Iabs=1 after two circulations; This explanation input change is fast, and output is followed also fast.

It should be noted that above-described embodiment the present invention will be described rather than limits the invention, and those skilled in the art can design alternative embodiment without departing from the scope of the appended claims.

Claims

1. the digital low-pass filtering method of integer arithmetic, its algorithm logic expression formula is following formula (1),

Y (n)={ x (n) y (n-1) }/h+y (n-1) (1)

Y (n)={ x (n) y (n-1)+r (n-1) }/h+y (n-1) (2)

Wherein, the algorithm logic expression formula of r is following formula (3),

The remainder (3) of r (n)={ x (n) y (n-1)+r (n-1) }/h

R (n): this remainder; R (n-1): last time remainder,

Y, x, h, r are integer,

Including computing y (n) and computing r (n) step.

2. the digital low-pass filtering method of integer arithmetic according to claim 1, it is characterised in that

The step of computing y (n), including,

Read x (n), y (n-1), r (n-1),

Call accumulator computing A=x (n) y (n-1)+r (n-1);

Read A, h,

Call divider computing B=A/h;

Read B, y (n-1),

Call accumulator computing y (n-1)+B, calculate y (n);

Y (n) exports as this filtering, and for computing next time,

The step of computing r (n), including,

Read x (n), y (n-1), r (n-1)

Call accumulator computing A=x (n) y (n-1)+r (n-1);

Read A, h,

Call the remainder of complementation internalarithmetic A/h, calculate r (n),

R (n) exports as this remainder, and for computing next time.

3. the digital low-pass filtering method of integer arithmetic according to claim 2, it is characterised in that described complementation arithmetical unit is logical shift device.

4. the digital low-pass filtering method of the integer arithmetic recorded any one of claims 1 to 3, it is characterised in that during initial computing, the initial value of y, r is set as 0.

5. the digital low-pass filtering device of integer arithmetic, it is characterized in that, including, calculate first accumulator of A=x (n) y (n-1)+r (n-1), calculate the divider of B=A/h, calculate second accumulator of y (n)=y (n-1)+B, calculate the 3rd accumulator of A=x (n) y (n-1)+r (n-1), calculate the complementation arithmetical unit of the remainder of A/h

6. the digital low-pass filtering device of integer arithmetic according to claim 5, it is characterised in that described complementation arithmetical unit is logical shift device.

7. the digital low-pass filtering device of the integer arithmetic recorded according to claim 5 or 6, it is characterised in that the first accumulator, the second accumulator, the 3rd accumulator are when initial computing, and the initial value of y, r is set as 0.