CN105654992B - The measuring circuit and method of the IP address settling time of SRAM - Google Patents
The measuring circuit and method of the IP address settling time of SRAM Download PDFInfo
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- CN105654992B CN105654992B CN201610024754.XA CN201610024754A CN105654992B CN 105654992 B CN105654992 B CN 105654992B CN 201610024754 A CN201610024754 A CN 201610024754A CN 105654992 B CN105654992 B CN 105654992B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/12015—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising clock generation or timing circuitry
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31725—Timing aspects, e.g. clock distribution, skew, propagation delay
Abstract
The invention discloses the measuring circuit of the IP address settling time of SRAM a kind of, including identical first and two SRAM；Data and address input end all link address input signals of first SRAM, input end of clock connect the first clock signal, and data output end is connected to the address input end of the 2nd SRAM；The data input pin of 2nd SRAM connects data input signal, and input end of clock connects second clock signal, and data output end connects the ends D of d type flip flop；The input end of clock of d type flip flop connects third clock signal, the ends Q output data output signal.Using first and two clock signal measure the IP address settling time measured value being delayed including SRAM；SRAM is measured using second and third clock signal to be delayed；Finally subtract each other to obtain IP address settling time.The invention also discloses the measurement methods of the IP address settling time of SRAM a kind of.The present invention can improve the accuracy measured.
Description
Technical field
The present invention relates to semiconductor integrated circuit design field, more particularly to the IP address settling time of SRAM a kind of
Measuring circuit, the invention further relates to the measurement methods of the IP address settling time of SRAM a kind of.
Background technology
As shown in Figure 1, being the measuring circuit figure of the IP address settling time of existing SRAM；The IP address of existing SRAM is established
The measuring circuit of time includes：
Tested Static RAM (SRAM) 101, data input signal D passes through combinational logic circuit
(Combinational Logic) 102a is connected to the data input pin i.e. ends D of SRAM101, and address input signal A passes through combination
Logic circuit 102b is input to the ends D of d type flip flop (DFF) 103a, and the address that the ends Q of d type flip flop 103a are connected to SRAM101 is defeated
Enter the end i.e. ends A；The data output end of SRAM101, that is, ends Q are connected to the ends D of d type flip flop 103b, the ends the Q output of d type flip flop 103b
Data output signal DOUT.
Clock signal clk I is connected to the input end of clock of d type flip flop 103a, and clock signal clk M is connected to SRAM101's
Input end of clock, that is, the ends CLK, clock signal clk O are connected to the input end of clock of d type flip flop 103b.
When the test of progress IP address settling time with the following method：
First, IP address settling time measured value is obtained using the setting measurement of clock signal clk I and CLKM
Tas(testing)。
Secondly further include, delay path in the path at the ends A that address input signal A is input to SRAM101, the delay path
T is will produce for d type flip flop 103a, d type flip flop 103adelayDelay, therefore need measured value Tas(testing)Subtract the delay
It can obtain IP address settling time actual value Tas, formula is：
Tas=Tas(testing)–Tdelay。
In above-mentioned formula, TdelayIt can not accurately calculate, reason is：The DFF output loadings of each bit address are different；Digital flow
The T quoteddelayIt is inaccurate.In this way so that the T finally measuredasAlso inaccurate.
Invention content
Technical problem to be solved by the invention is to provide the measuring circuits of the IP address settling time of SRAM a kind of, can carry
The accuracy that the IP address settling time of high SRAM measures.For this purpose, the present invention also provides the IP address settling times of SRAM a kind of
Measurement method.
In order to solve the above technical problems, the measuring circuit of the IP address settling time of SRAM provided by the invention includes：The
One SRAM and the 2nd SRAM, the 2nd SRAM are tested SRAM, the structure and the 2nd SRAM phases of the first SRAM
Together.
The data input pin and address input end all link address input signals of first SRAM, the first SRAM's
Input end of clock connects the first clock signal, and the address that the data output end of the first SRAM is connected to the 2nd SRAM is defeated
Enter end.
The data input pin of 2nd SRAM connects data input signal, the input end of clock connection of the 2nd SRAM
Second clock signal, the ends D of the data output end connection d type flip flop of the 2nd SRAM.
The input end of clock of the d type flip flop connects third clock signal, the ends the Q output data output of the d type flip flop
Signal.
Go out described address input signal from described using first clock signal and the second clock signal measurement
First SRAM delay and IP address settling time of the address input end of one SRAM to the address input end of the 2nd SRAM
With.
The 2nd SRAM is measured using the second clock signal and the third clock signal to be delayed.
It is identical with the structure of the 2nd SRAM using the first SRAM and make the first SRAM delay and described the
Two SRAM be delayed identical feature by the first SRAM delay and the IP address settling time and subtract described second
SRAM is delayed to obtain the IP address settling time.
A further improvement is that the first SRAM and the 2nd SRAM is close to placement on domain.
It is delayed with the IP address settling time and is walked including following a further improvement is that measuring the first SRAM
Suddenly：
Described address input signal and the data input signal are all effective, first clock signal, it is described second when
Clock signal and the third clock signal all remain low level.
First clock signal is added, the described address input letter at first rising edge of first clock signal
Number it is input in the first SRAM and is input to after the first SRAM delays address input end of the 2nd SRAM.
The second clock signal is added, is arranged using the method for Step wise approximation on first of the second clock signal
Rising makes along position first leading edge position of the second clock signal can guarantee that the data for making the 2nd SRAM export
Make first rising edge and described first of the second clock signal under conditions of the value of the end output data input signal
Time difference between first rising edge of clock signal is minimum, and the time difference of the minimum is taken to be delayed for the first SRAM and institute
State the sum of IP address settling time.
Include the following steps a further improvement is that measuring the 2nd SRAM delays：
Described address input signal and the data input signal are all effective, first clock signal, it is described second when
Clock signal and the third clock signal all remain low level.
First clock signal is added, the described address input letter at first rising edge of first clock signal
Number it is input in the first SRAM and is input to after the first SRAM delays address input end of the 2nd SRAM.
The second clock signal is added, first leading edge position of the second clock signal, which can guarantee, makes described
The data output end of two SRAM exports the value of the data input signal.
The third clock signal is added, is arranged using the method for Step wise approximation on first of the third clock signal
Rising makes along position first leading edge position of the third clock signal so that the data output signal is switched to can guarantee
Make first rising edge and second clock letter of the third clock signal under conditions of the value of the data input signal
Number first rising edge between time difference it is minimum, take the time difference of minimum for the 2nd SRAM delays.
In order to solve the above technical problems, the measurement method of the IP address settling time of SRAM provided by the invention includes as follows
Step：
Step 1: setting measuring circuit, the measuring circuit include the first SRAM and the 2nd SRAM, the 2nd SRAM is
Tested SRAM, the structure of the first SRAM are identical with the 2nd SRAM.
The data input pin and address input end all link address input signals of first SRAM, the first SRAM's
Input end of clock connects the first clock signal, and the address that the data output end of the first SRAM is connected to the 2nd SRAM is defeated
Enter end.
The data input pin of 2nd SRAM connects data input signal, the input end of clock connection of the 2nd SRAM
Second clock signal, the ends D of the data output end connection d type flip flop of the 2nd SRAM.
The input end of clock of the d type flip flop connects third clock signal, the ends the Q output data output of the d type flip flop
Signal.
Step 2: using first clock signal and the second clock signal measurement go out described address input signal from
The first SRAM delays of address input end of the address input end of first SRAM to the 2nd SRAM and IP address are established
The sum of time.
It is delayed Step 3: measuring the 2nd SRAM using the second clock signal and the third clock signal.
Step 4: it is identical with the structure of the 2nd SRAM using the first SRAM and make the first SRAM delay and
2nd SRAM be delayed identical feature by the first SRAM delays and the IP address settling time and subtract described
2nd SRAM is delayed to obtain the IP address settling time.
The present invention uses i.e. the first SRAM of SRAM identical with tested SRAM i.e. the 2nd SRAM structures as tested SRAM's
The extension path of address input end, due to including extension path delay and IP address settling time and can by connection
It accurately measures to the setting of the clock signal of the input end of clock of two SRAM, and the delay of extension path is then by right
It is tested the setting of the clock signal of the input end of clock of the d type flip flop of SRAM and output end and indirectly accurately measures, two
A accurate measurements can obtain the exact value of IP address settling time after subtracting each other, compared with the existing technology in d type flip flop prolong
When measure inaccurate situation, the present invention can improve the measurement accuracy of IP address settling time.
Description of the drawings
The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments：
Fig. 1 is the measuring circuit figure of the IP address settling time of existing SRAM；
Fig. 2 is the measuring circuit of the IP address settling time of SRAM of the embodiment of the present invention；
Fig. 3 is Fig. 2 domains；
Fig. 4 is each signal curve figure in present invention method.
Specific implementation mode
As shown in Fig. 2, being the measuring circuit of the IP address settling time of SRAM of the embodiment of the present invention；The embodiment of the present invention
The measuring circuit of the IP address settling time of SRAM includes：First SRAM1 and the 2nd SRAM2, the 2nd SRAM2 is tested
The structure of SRAM, the first SRAM1 are identical with the 2nd SRAM2.
Data input pin, that is, ends D1 of first SRAM1 and address input end, that is, ends Addr in all link addresses input
The input end of clock of signal A, the first SRAM1 connect the first clock signal CKLI, the data output end of the first SRAM1
I.e. the ends Q1 are connected to the address input end i.e. ends A2 of the 2nd SRAM2.
The data input pin of 2nd SRAM2, that is, ends D2 connect data input signal D, the clock of the 2nd SRAM2
Input terminal connects the ends D of the data output end, that is, ends Q2 connection d type flip flop 4 of second clock signal CLKM, the 2nd SRAM2.
The input end of clock of the d type flip flop 4 connects third clock signal clk O, and the ends Q of the d type flip flop 4 export number
According to output signal DOUT.
Described address input signal A is measured using the first clock signal CKLI and the second clock signal CLKM
The first SRAM1 delays of address input end from the address input end of the first SRAM1 to the 2nd SRAM2 and IP address
The sum of settling time.
The 2nd SRAM2 is measured using the second clock signal CLKM and the third clock signal clk O to be delayed.
It is identical with the structure of the 2nd SRAM2 using the first SRAM1 and make the first SRAM1 delay and described
2nd SRAM2 be delayed identical feature by the first SRAM1 delays and the IP address settling time and subtract described the
Two SRAM2 are delayed to obtain the IP address settling time.
It is preferably selected as, the data input signal D is connected to the number of the 2nd SRAM2 by combinational logic circuit 3a
According to input terminal.
Described address input signal A by combinational logic circuit 3b be connected to the first SRAM1 data input pin and
Address input end.
As shown in figure 3, being Fig. 2 domains；The first SRAM1 and the 2nd SRAM2 is close on domain places, and two
The input/output port of person, that is, ports io are adjacent, and the ports io include that above-mentioned data input pin, address input end and clock input
End.Logic circuit 201 includes combinations of the above logic circuit 3a and 3b and d type flip flop 4.
As shown in figure 4, being each signal curve figure in present invention method, wherein Addr In correspond to the ends Addr In
Signal curve, CKLI correspond to the curve of the first clock signal CKLI, and Q1 (A2) corresponds to the signal curve at the ends Q1 or the ends A2,
CKLM corresponds to the curve of second clock signal CKLM, and Q2 corresponds to the signal curve at the ends Q2, and CKLO believes corresponding to second clock
The curve of number CKLO.
The sum for measuring the first the SRAM1 delay and the IP address settling time, includes the following steps：
Described address input signal A and the data input signal D are effective, the first clock signal CKLI, described
Second clock signal CLKM and the third clock signal clk O remain low level.
The first clock signal CKLI is added, at first rising edge of the first clock signal CKLI describedly
Location input signal A is input in the first SRAM1 and is input to the 2nd SRAM2 after the first SRAM1 delays
Address input end.
The second clock signal CLKM is added, is arranged the second clock signal CLKM's using the method for Step wise approximation
First leading edge position makes first leading edge position of the second clock signal CLKM make described second can guarantee
The data output end of SRAM2 makes the of the second clock signal CLKM under conditions of exporting the value of the data input signal D
Time difference between one rising edge and first rising edge of the first clock signal CKLI is minimum, takes the time of the minimum
Difference is the sum of the first SRAM1 delay and the IP address settling time.Namely when the of the second clock signal CLKM
When one leading edge position can make the data output end of the 2nd SRAM2 export the value of the data input signal D, then illustrate
The enough IP address settling times having had before first rising edge of the second clock signal CLKM；And it gradually forces
Closely make the second clock signal CLKM first rising edge and the first clock signal CKLI first rising edge it
Between time difference minimum when can then obtain IP address settling time of not allowance.
As shown in Figure 4, Tas(testing)It is established for the first SRAM1 delays finally measured and the IP address
Time and be also the IP address settling time measured value for including delay, which obtains after multiple Approach by inchmeal
Between first rising edge of the second clock signal CLKM and first rising edge of the first clock signal CKLI
Time difference.
The 2nd SRAM2 delays are measured to include the following steps：
Described address input signal A and the data input signal D are effective, the first clock signal CKLI, described
Second clock signal CLKM and the third clock signal clk O remain low level.
The first clock signal CKLI is added, at first rising edge of the first clock signal CKLI describedly
Location input signal A is input in the first SRAM1 and is input to the 2nd SRAM2 after the first SRAM1 delays
Address input end.
The second clock signal CLKM is added, first leading edge position of the second clock signal CLKM can guarantee
The data output end of the 2nd SRAM2 is set to export the value of the data input signal D.
The third clock signal clk O is added, is arranged the third clock signal clk O's using the method for Step wise approximation
First leading edge position makes first leading edge position of the third clock signal clk O keep the data defeated can guarantee
Going out under conditions of signal DOUT is switched to the value of the data input signal D makes on first of the third clock signal clk O
The time difference risen between edge and first rising edge of the second clock signal CLKM is minimum, takes the time difference of the minimum for institute
State the 2nd SRAM2 delays.Namely make the data when first leading edge position of the third clock signal clk O can guarantee
When output signal DOUT is switched to the value of the data input signal D, on illustrate the third clock signal clk O first
It is to prolong more than or equal to the 2nd SRAM2 to rise the time difference between edge and first rising edge of the second clock signal CLKM
When；And Approach by inchmeal make the third clock signal clk O first rising edge and the second clock signal CLKM
The 2nd SRAM2 delays of not allowance can be then obtained when time difference minimum between one rising edge.
As shown in Figure 4, TaccFor the 2nd SRAM2 delays finally measured, which is by repeatedly gradually forcing
On first rising edge of the third clock signal clk O and first of the second clock signal CLKM obtained after close
Rise the time difference between.And since the first SRAM1 is identical with the structure of the 2nd SRAM2, therefore the first SRAM1
Delay is also Tacc.Finally by Tas(testing)Subtract TaccObtain the i.e. T of IP address settling time actual value afterwardsas。
The measurement method of the IP address settling time of SRAM of the embodiment of the present invention includes the following steps：
Step 1: as shown in Fig. 2, setting measuring circuit, the measuring circuit include the first SRAM1 and the 2nd SRAM2, institute
It is tested SRAM to state the 2nd SRAM2, and the structure of the first SRAM1 is identical with the 2nd SRAM2.
The data input pin of first SRAM1 and address input end all link address input signal A, described first
The input end of clock of SRAM1 connects the first clock signal CKLI, and the data output end of the first SRAM1 is connected to described second
The address input end of SRAM2.
The data input pin of 2nd SRAM2 connects data input signal D, the input end of clock of the 2nd SRAM2
Connect the ends D of the data output end connection d type flip flop 4 of second clock signal CLKM, the 2nd SRAM2.
The input end of clock of the d type flip flop 4 connects third clock signal clk O, and the ends Q of the d type flip flop 4 export number
According to output signal DOUT.
It is preferably selected as, the data input signal D is connected to the number of the 2nd SRAM2 by combinational logic circuit 3a
According to input terminal.
Described address input signal A by combinational logic circuit 3b be connected to the first SRAM1 data input pin and
Address input end.
As shown in figure 3, being Fig. 2 domains；The first SRAM1 and the 2nd SRAM2 is close on domain places, and two
The input/output port of person, that is, ports io are adjacent, and the ports io include that above-mentioned data input pin, address input end and clock input
End.Logic circuit 201 includes combinations of the above logic circuit 3a and 3b and d type flip flop 4.
Step 2: it is defeated to measure described address using the first clock signal CKLI and the second clock signal CLKM
Enter the first SRAM1 delays of address input ends of the signal A from the address input end of the first SRAM1 to the 2nd SRAM2
With the sum of IP address settling time；
Step 3: measuring the 2nd SRAM2 using the second clock signal CLKM and the third clock signal clk O
Delay；
Step 4: identical with the structure of the 2nd SRAM2 using the first SRAM1 and the first SRAM1 is made to prolong
When and the 2nd SRAM2 be delayed identical feature by the first SRAM1 delay and the IP address settling time and subtract
The 2nd SRAM2 is gone to be delayed to obtain the IP address settling time.
Step 2 include it is following step by step：
Step 21, described address input signal A and the data input signal D are effective, first clock signal
CKLI, the second clock signal CLKM and the third clock signal clk O remain low level.
The first clock signal CKLI is added in step 22, in first rising edge of the first clock signal CKLI
Locate the address input signal A to be input in the first SRAM1 and be input to described the after the first SRAM1 delays
The address input end of two SRAM2.
The second clock signal CLKM is added in step 23, and the second clock, which is arranged, using the method for Step wise approximation believes
First leading edge position of number CLKM makes first leading edge position of the second clock signal CLKM make institute can guarantee
State the 2nd SRAM2 data output end export the value of the data input signal D under conditions of make the second clock signal
Time difference between first rising edge of CLKM and first rising edge of the first clock signal CKLI is minimum, takes this most
The small time difference is the sum of the first SRAM1 delay and the IP address settling time.Namely work as the second clock signal
First leading edge position of CLKM can make the data output end of the 2nd SRAM2 export the value of the data input signal D
When, then when illustrating that the enough IP address having had before first rising edge of the second clock signal CLKM are established
Between；And Approach by inchmeal make the second clock signal CLKM first rising edge and the first clock signal CKLI first
The IP address settling time of not allowance can be then obtained when time difference minimum between a rising edge.
As shown in Figure 4, Tas(testing)It is established for the first SRAM1 delays finally measured and the IP address
The sum of time, the value are first rising edge of the second clock signal CLKM obtained after multiple Approach by inchmeal and institute
State the time difference between first rising edge of the first clock signal CKLI.
Step 3 include it is following step by step：
Step 31, described address input signal A and the data input signal D are effective, first clock signal
CKLI, the second clock signal CLKM and the third clock signal clk O remain low level.
The first clock signal CKLI is added in step 32, in first rising edge of the first clock signal CKLI
Locate the address input signal A to be input in the first SRAM1 and be input to described the after the first SRAM1 delays
The address input end of two SRAM2.
The second clock signal CLKM, first rising edge position of the second clock signal CLKM is added in step 33
Set the value that can guarantee and the data output end of the 2nd SRAM2 is made to export the data input signal D.
The third clock signal clk O is added in step 34, and the third clock, which is arranged, using the method for Step wise approximation believes
First leading edge position of number CLKO makes first leading edge position of the third clock signal clk O make institute can guarantee
Stating under conditions of data output signal DOUT is switched to the value of the data input signal D makes the third clock signal clk O's
Time difference between first rising edge and first rising edge of the second clock signal CLKM is minimum, take the minimum when
Between difference be the 2nd SRAM2 be delayed.Namely make when first leading edge position of the third clock signal clk O can guarantee
When the data output signal DOUT is switched to the value of the data input signal D, illustrate the third clock signal clk O's
Time difference between first rising edge and first rising edge of the second clock signal CLKM is more than or equal to described the
Two SRAM2 are delayed；And Approach by inchmeal makes first rising edge and second clock letter of the third clock signal clk O
The 2nd SRAM2 delays of not allowance can be then obtained when time difference minimum between first rising edge of number CLKM.
As shown in Figure 4, TaccFor the 2nd SRAM2 delays finally measured, which is by repeatedly gradually forcing
On first rising edge of the third clock signal clk O and first of the second clock signal CLKM obtained after close
Rise the time difference between.And since the first SRAM1 is identical with the structure of the 2nd SRAM2, therefore the first SRAM1
Delay is also Tacc.Finally by Tas(testing)Subtract TaccObtain the i.e. T of IP address settling time actual value afterwardsas。
The present invention has been described in detail through specific embodiments, but these not constitute the limit to the present invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these are also answered
It is considered as protection scope of the present invention.
Claims (8)
1. the measuring circuit of the IP address settling time of SRAM a kind of, which is characterized in that including：First SRAM and the 2nd SRAM,
2nd SRAM is tested SRAM, and the structure of the first SRAM is identical with the 2nd SRAM；
The data input pin and address input end all link address input signals of first SRAM, the clock of the first SRAM
Input terminal connects the first clock signal, and the data output end of the first SRAM is connected to the address input of the 2nd SRAM
End；
The data input pin of 2nd SRAM connects data input signal, the input end of clock connection second of the 2nd SRAM
Clock signal, the ends D of the data output end connection d type flip flop of the 2nd SRAM；
The input end of clock of the d type flip flop connects third clock signal, the ends the Q output data output signal of the d type flip flop；
Go out described address input signal from described first using first clock signal and the second clock signal measurement
Sum of the address input end of SRAM to the first the SRAM delay and IP address settling time of the address input end of the 2nd SRAM；
The 2nd SRAM is measured using the second clock signal and the third clock signal to be delayed；
It is identical with the structure of the 2nd SRAM using the first SRAM and make the first SRAM delay and described second
SRAM be delayed identical feature by the first SRAM delay and the IP address settling time and subtract the 2nd SRAM
Delay obtains the IP address settling time；
It measures the first SRAM delays and the IP address settling time and includes the following steps：
Described address input signal and the data input signal are all effective, first clock signal, second clock letter
Number and the third clock signal all remain low level；
First clock signal is added, the address input signal is defeated at first rising edge of first clock signal
Enter into the first SRAM and be input to after the first SRAM delays address input end of the 2nd SRAM；
The second clock signal is added, first rising edge of the second clock signal is set using the method for Step wise approximation
Position makes first leading edge position of the second clock signal keep the data output end of the 2nd SRAM defeated can guarantee
Going out under conditions of the value of the data input signal makes first rising edge of the second clock signal and first clock
Time difference between first rising edge of signal is minimum, and it is that the first SRAM is delayed with the IP to take the minimum time difference
The sum of location settling time；
The 2nd SRAM delays are measured to include the following steps：
Described address input signal and the data input signal are all effective, first clock signal, second clock letter
Number and the third clock signal all remain low level；
First clock signal is added, the address input signal is defeated at first rising edge of first clock signal
Enter into the first SRAM and be input to after the first SRAM delays address input end of the 2nd SRAM；
The second clock signal is added, first leading edge position of the second clock signal, which can guarantee, makes described second
The data output end of SRAM exports the value of the data input signal；
The third clock signal is added, first rising edge of the third clock signal is set using the method for Step wise approximation
Position makes first leading edge position of the third clock signal can guarantee that so that the data output signal is switched to described
Make first rising edge of the third clock signal and the second clock signal under conditions of the value of data input signal
Time difference between first rising edge is minimum, and the minimum time difference is taken to be delayed for the 2nd SRAM.
2. the measuring circuit of the IP address settling time of SRAM as described in claim 1, it is characterised in that：The data input
Signal is connected to the data input pin of the 2nd SRAM by combinational logic circuit.
3. the measuring circuit of the IP address settling time of SRAM as described in claim 1, it is characterised in that：Described address inputs
Signal is connected to the data input pin and address input end of the first SRAM by combinational logic circuit.
4. the measuring circuit of the IP address settling time of SRAM as described in claim 1, it is characterised in that：It is described on domain
First SRAM and the 2nd SRAM is close to placement.
5. the measurement method of the IP address settling time of SRAM a kind of, which is characterized in that include the following steps：
Step 1: setting measuring circuit, the measuring circuit include the first SRAM and the 2nd SRAM, the 2nd SRAM is tested
SRAM is tried, the structure of the first SRAM is identical with the 2nd SRAM；
The data input pin and address input end all link address input signals of first SRAM, the clock of the first SRAM
Input terminal connects the first clock signal, and the data output end of the first SRAM is connected to the address input of the 2nd SRAM
End；
The data input pin of 2nd SRAM connects data input signal, the input end of clock connection second of the 2nd SRAM
Clock signal, the ends D of the data output end connection d type flip flop of the 2nd SRAM；
The input end of clock of the d type flip flop connects third clock signal, the ends the Q output data output signal of the d type flip flop；
Step 2: going out described address input signal from described using first clock signal and the second clock signal measurement
First SRAM delay and IP address settling time of the address input end of first SRAM to the address input end of the 2nd SRAM
Sum；
Step 2 include it is following step by step：
Step 21, described address input signal and the data input signal are all effective, first clock signal, described second
Clock signal and the third clock signal all remain low level；
First clock signal is added in step 22, and described address is defeated at first rising edge of first clock signal
Enter signal be input in the first SRAM and be input to after the first SRAM delays the 2nd SRAM address it is defeated
Enter end；
The second clock signal is added in step 23, is arranged the first of the second clock signal using the method for Step wise approximation
A leading edge position makes first leading edge position of the second clock signal can guarantee the data for making the 2nd SRAM
Output end exports first rising edge for making the second clock signal under conditions of the value of the data input signal and described
Time difference between first rising edge of the first clock signal is minimum, take the minimum time difference be the first SRAM delays and
The sum of the IP address settling time；
It is delayed Step 3: measuring the 2nd SRAM using the second clock signal and the third clock signal；
Step 3 include it is following step by step：
Step 31, described address input signal and the data input signal are all effective, first clock signal, described second
Clock signal and the third clock signal all remain low level；
First clock signal is added in step 32, and described address is defeated at first rising edge of first clock signal
Enter signal be input in the first SRAM and be input to after the first SRAM delays the 2nd SRAM address it is defeated
Enter end；
The second clock signal is added in step 33, and first leading edge position of the second clock signal, which can guarantee, makes institute
The data output end for stating the 2nd SRAM exports the value of the data input signal；
The third clock signal is added in step 34, is arranged the first of the third clock signal using the method for Step wise approximation
A leading edge position makes first leading edge position of the third clock signal so that the data output signal is cut can guarantee
Be changed to first rising edge for making the third clock signal under conditions of the value of the data input signal and it is described second when
Time difference between first rising edge of clock signal is minimum, and the minimum time difference is taken to be delayed for the 2nd SRAM；
Step 4: identical with the structure of the 2nd SRAM using the first SRAM and make the first SRAM delay and described
2nd SRAM be delayed identical feature by the first SRAM delay and the IP address settling time and subtract described second
SRAM is delayed to obtain the IP address settling time.
6. the measurement method of the IP address settling time of SRAM as claimed in claim 5, it is characterised in that：The data input
Signal is connected to the data input pin of the 2nd SRAM by combinational logic circuit.
7. the measurement method of the IP address settling time of SRAM as claimed in claim 5, it is characterised in that：Described address inputs
Signal is connected to the data input pin and address input end of the first SRAM by combinational logic circuit.
8. the measurement method of the IP address settling time of SRAM as claimed in claim 5, it is characterised in that：It is described on domain
First SRAM and the 2nd SRAM is close to placement.
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| CN102253643A (en) * | 2011-06-23 | 2011-11-23 | 山东力创科技有限公司 | High-precision time measuring circuit and method |
| CN103886913A (en) * | 2014-03-31 | 2014-06-25 | 西安华芯半导体有限公司 | SRAM (Static Random Access Memory) reading time self-testing circuit and method |
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| CN102253643A (en) * | 2011-06-23 | 2011-11-23 | 山东力创科技有限公司 | High-precision time measuring circuit and method |
| CN103886913A (en) * | 2014-03-31 | 2014-06-25 | 西安华芯半导体有限公司 | SRAM (Static Random Access Memory) reading time self-testing circuit and method |
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