CN105653488A - Circuit and method for lowering data coupling effect in long bus - Google Patents
Circuit and method for lowering data coupling effect in long bus Download PDFInfo
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- CN105653488A CN105653488A CN201511023963.4A CN201511023963A CN105653488A CN 105653488 A CN105653488 A CN 105653488A CN 201511023963 A CN201511023963 A CN 201511023963A CN 105653488 A CN105653488 A CN 105653488A
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- driving
- signal line
- reverser
- buffer
- line
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
Abstract
The present invention provides a circuit for lowering a data coupling effect in a long bus. The circuit includes a data bus. The data bus includes n signal lines. The n signal lines include even number signal lines and odd number signal lines. Each of the even number signal lines includes a drive inverter and a drive cache that appear alternatively. The drive inverter and the drive cache that appear alternatively are coupled in sequence. Each of the odd number signal lines include a drive cache and a drive inverter that appear alternatively. The drive cache and the drive inverter that appear alternatively are coupled in sequence. If the drive inverter among the even number signal lines appears first, the drive cache among the odd number signal lines appears first. If the drive cache among the even number signal lines appears first, the drive inverter among the odd number signal lines appears first.
Description
Technical field
The present invention relates to driving IC technical field, particularly relate in long bus-structured driving IC, for the circuit design reducing long bus coupling influence.
Background technology
Fig. 1 be one existing drive in IC frequently with latch (latch) storage architecture, it comprises data/address bus 130, first order latch 110, second level latch 111, la1 time-sequence control mode 112, la2 time-sequence control mode 113, digital-to-analogue conversion (DAC) module 120. Described first order latch 110 is used for storing data data after algorithm and Gamma correction, controls under the control of tfi module 112 at la1, and first order latch captures the data on data/address bus 130 successively according to sequential. La2 time-sequence control mode 113 is used for the timing control signal producing to control second level latch, by the time after first order latch all receives data, la2 time-sequence control mode produces control signal, in disposable for the view data in first order latch importing second level latch 111. Data in 120 second level latch of DAC module convert simulation GTG to and deliver to the upper parameter of output pin (pad) and show. Second level latch is directly connected with DAC module 120, thus can ensure that within the time of a HS, and the gray scale level that data-driven line (source) exports is stable. By real-time refreshing, complete the display of frame data.
Fig. 2 is the existing topological simplicity figure driving IC. For the resolution of HD800P, the length from left to right occupied due to 2400 data-driven wire pins is about 20000um, so domain engineer is when wiring, it is necessary to data/address bus 130 from Zola to the right side. For so long cabling, not only to consider its driving force, it is also contemplated that the coupling between data.
Fig. 3 is the sequential chart that latch captures data. When being left out coupling influence, data set up the time (setuptime) and the retention time (holdtime) respectively accounts for T/2, when considering coupling, the time of setting up of data or retention time can be reduced because data delay is uneven.In order to increase driving force, it is possible to data/address bus 130 is divided into 8 grades, every grade increases a driving buffer to strengthen driving force, but the coupling electric capacity of every grade can reach 200ff, because coupling causes that time delay is uneven and causes that time of invalid data can arrive about 7ns. Under the resolution of HD800P, the speed of MIPI interface needs to reach 550Mbps, the clock cycle that data are processed at about 14ns because coupling causes that time of invalid data has just accounted for the half in total cycle. Therefore, only drive, by increasing, the impact that data coupling can not be solved on data/address bus.
Summary of the invention
In order to reduce the bad image of the data coupling in long data bus, the invention provides and a kind of reduce the circuit of data coupling effect in long bus.
Described circuit includes:
Data/address bus, described data/address bus includes n signal line, and described n signal line is divided into even signal line and odd signals line;
Each signal line in described even signal line includes the driving reverser that is alternately present and drives buffer, described in the driving reverser that is alternately present and drive buffer to couple successively;
Each signal line in described odd signals line includes the driving buffer that is alternately present and drives reverser, described in the driving buffer that is alternately present and drive reverser to couple successively;
Wherein, if first occurs that driving reverser in described even signal line, then in described odd signals line first occur that driving buffer, if in described even signal line first occur that driving buffer, then in described odd signals line first occur that driving reverser.
In one embodiment, described n is 60.
In one embodiment, the driving reverser in each signal line in described even signal line is identical with the total sum of the driving reverser in each signal line in described odd signals line and driving buffer with the total sum driving buffer.
In one embodiment, the number of the driving reverser in each signal line in described even signal line is identical with the number driving buffer; The number of the driving reverser in each signal line in described odd signals line is identical with the number driving buffer.
In one embodiment, the number driving reverser in each signal line in described even signal line is 4, and the number of described driving buffer is 4; The number driving buffer in each signal line in described odd signals line is 4, and the number driving reverser is 4.
The invention provides and a kind of reduce the method for data coupling effect in long bus. The method comprises the following steps:
N data bus is divided into even signal line and odd signals line;
Each signal line in described even signal line provides the driving reverser that is alternately present and drives buffer, described in the driving reverser that is alternately present and drive buffer to couple successively;
Each signal line in described odd signals line provides the driving buffer that is alternately present and drives reverser, described in the driving buffer that is alternately present and drive reverser to couple successively;
Wherein, if first occurs that driving reverser in described even signal line, then in described odd signals line first occur that driving buffer, if in described even signal line first occur that driving buffer, then in described odd signals line first occur that driving reverser.
In one embodiment, described n is 60.
In one embodiment, the driving reverser in each signal line in described even signal line is identical with the total sum of the driving reverser in each signal line in described odd signals line and driving buffer with the total sum driving buffer.
In one embodiment, the number of the driving reverser in each signal line in described even signal line is identical with the number driving buffer; The number of the driving reverser in each signal line in described odd signals line is identical with the number driving buffer.
In one embodiment, the number driving reverser in each signal line in described even signal line is 4, and the number of described driving buffer is 4; The number driving buffer in each signal line in described odd signals line is 4, and the number driving reverser is 4.
Foregoing circuit provided by the present invention and method reduce coupling electric capacity effectively on impact produced by the longer data/address bus of cabling, improve the utilization rate of sequential.
Accompanying drawing explanation
The above summary of the invention of the present invention and detailed description below can be better understood when reading in conjunction with the accompanying. It should be noted that accompanying drawing is only used as the example of claimed invention. In the accompanying drawings, identical accompanying drawing labelling represents same or similar element.
Fig. 1 be one existing drive in IC frequently with latch (latch) storage architecture.
Fig. 2 is the existing topological simplicity figure driving IC.
Fig. 3 is the sequential chart that latch captures data.
Fig. 4 illustrates that a kind of according to an embodiment of the invention reduction drives the circuit diagram of long bus coupling in IC.
Fig. 5 is that interval is inserted driving buffer and drives inverter and the single emulation Data Comparison inserting driving buffer.
Fig. 6 is signal polarity correcting circuit figure.
Detailed description of the invention
Hereinafter detailed features and the advantage of the present invention are described in a specific embodiment in detail, its content is enough to make the technology contents of any present invention of skilled in the art realises that and implement according to this, and description disclosed by this specification, claim and accompanying drawing, skilled person readily understands that purpose and advantage that the present invention is correlated with.
Fig. 4 illustrates that a kind of according to an embodiment of the invention reduction drives the circuit diagram of long bus coupling in IC. Fig. 4 is driven to example explanation to insert 8 grades, it is to be noted that the present invention is not limited to insert 8 grades of drivings, the present invention can insert arbitrary number of level as required and drive.
In one embodiment, data/address bus 130 is n position. Each corresponding holding wire. For long holding wire din [0], insert and drive reverser (inverter) 210, obtain output da [0]; Da [0] connects driving buffer (buffer) 211 below, obtains output signal db [0]; Db [0] is connected to the input driving reverser 210, obtains signal dc [0].
In order, alternately long holding wire din [0] is inserted 4 grades of driving reversers 210 and 4 grades of driving buffers 211.
To the long holding wire din [1] adjacent with din [0], first insert and drive buffer211, be then inserted into driving inverter210, drive buffer contrary with long holding wire din [0] with the order driving inverter.
The same din of process [0] to long holding wire din [2], the same din of the process [1] to long holding wire din [3].
According to this rule, the long holding wire of dual numbers is sequentially inserted into driving inverter210 and drives buffer211, the long holding wire of odd number is sequentially inserted into driving buffer211 and drives inverter210.
Explain with long holding wire din [1], when din [1] is become 1 by 0, when changing for rising edge, putative signal line din [0] and holding wire din [2] change for trailing edge, and the rising of din [1] can be had a negative impact by din [0] and din [2] by coupling electric capacity; When din [1] drives buffer211 by the first order, din [0] and din [2] drives inverter because have passed through one-level, become rising edge change from trailing edge, can pass through to couple capacitive effect and din [1] is produced favorable influence. When by odd number driving stage, din [1] can be produced favourable coupling influence according to this rule, din [0] and din [2]; When by even number driving stage, din [1] is produced disadvantageous coupling influence. After 8 grades of driving stages, it is weakened that coupling influence relatively inserts single driving buffer (or driving inverter).
Still explain with long holding wire din [1], when din [1] is become 1 by 0, when changing for rising edge, it is assumed that holding wire din [0] and holding wire din [2] also changes for rising edge; Din [1] when by odd number driving stage, can be produced disadvantageous coupling influence by rule according to the above analysis, din [0] and din [2]; When by even number driving stage, din [1] is produced favourable coupling influence. After 8 grades of driving stages, coupling influence relatively inserts single driving buffer (or driving inverter) and is reinforced.
So, no matter the impact of din [1] is advantageous for or disadvantageous by adjacent holding wire din [0] and din [2] at input, and after 8 grades of driving stages, the time delay of signal can tend to meansigma methods. If with single driving buffer (or drive inverter), the time delay of signal under favourable coupling influence less than meansigma methods, more than meansigma methods under unfavorable coupling influence. When coupling electric capacity and being very big, the difference of the two must be taken seriously.
The present invention time delay by equalization signal, reaches to weaken the effect of coupling influence.
Fig. 5 is that interval is inserted driving buffer and drives inverter and the single emulation Data Comparison inserting driving buffer. Based on VIS0.162um processing procedure, under the simulation size of 5 times, from the comparative result of three PVT it can be seen that adopt and be interleaved alternately with the scheme driving buffer and driving inverter, it is possible to effectively reduce the coupling electric capacity impact on data/address bus.
Fig. 6 is signal polarity correcting circuit figure. Because signal is when inserting driving buffer211 and driving inverter210, the polarity of part signal is negated, it is necessary to correct according to rule.
For holding wire din [0] and din [1] analysis, its rule is: through the first driving stage, din [0] is negated, and din [1] polarity is constant; Through the second driving stage, din [0] is negated, and din [1] is also negated; Through the 3rd driving stage, din [0] polarity is constant, and din [1] polarity negates; After the 4th driving stage, the polarity of the two all becomes original state again. So, level Four driving stage is a cycle period.
According to above-mentioned rule, the polarity of signal is corrected according to Fig. 6. Correction rule is divided into 4 type:type1, type2, type3 and type4. The Q of QB output and even number latch that Type1 takes odd number latch exports; Type2 takes the QB output of all latch; The QB of Q output and even number latch that Type3 takes odd number latch exports; Type4 takes the Q output of all latch.
The impact of coupling electric capacity, when not increasing pipe number, has been weakened by the present invention, so that the time delay of signal tends to meansigma methods, the crank-up time of signal bus is shortened, and is effectively increased the utilization rate of timing.
Here the term adopted and form of presentation are only intended to describe, and the present invention should not be limited to these terms and statement. These terms and statement is used to be not meant to get rid of any signal and describe the equivalent features of (or wherein part), it should be recognized that various amendments that may be present also should be included in right. Other amendments, variations and alternatives also likely to be present. Accordingly, claim should be regarded as covering all these equivalents.
Equally, it is to be noted, although the present invention describes with reference to current specific embodiment, but those of ordinary skill in the art will be appreciated that, above embodiments is intended merely to the explanation present invention, change or the replacement of various equivalence is it may also be made that, therefore, as long as to the change of above-described embodiment, modification all by the scope dropping on following claims in the spirit of the present invention when without departing from spirit of the present invention.
Claims (10)
1. one kind reduces the circuit of data coupling effect in long bus, it is characterised in that described circuit includes:
Data/address bus, described data/address bus includes n signal line, and described n signal line is divided into even signal line and odd signals line;
Each signal line in described even signal line includes the driving reverser that is alternately present and drives buffer, described in the driving reverser that is alternately present and drive buffer to couple successively;
Each signal line in described odd signals line includes the driving buffer that is alternately present and drives reverser, described in the driving buffer that is alternately present and drive reverser to couple successively;
Wherein, if first occurs that driving reverser in described even signal line, then in described odd signals line first occur that driving buffer, if in described even signal line first occur that driving buffer, then in described odd signals line first occur that driving reverser.
2. circuit as claimed in claim 1, it is characterised in that described n is 60.
3. circuit as claimed in claim 1, it is characterized in that, the driving reverser in each signal line in described even signal line is identical with the total sum of the driving reverser in each signal line in described odd signals line and driving buffer with the total sum driving buffer.
4. circuit as claimed in claim 1, it is characterised in that the number of the driving reverser in each signal line in described even signal line is identical with the number driving buffer; The number of the driving reverser in each signal line in described odd signals line is identical with the number driving buffer.
5. circuit as claimed in claim 1, it is characterised in that the number driving reverser in each signal line in described even signal line is 4, and the number of described driving buffer is 4; The number driving buffer in each signal line in described odd signals line is 4, and the number driving reverser is 4.
6. one kind reduces the method for data coupling effect in long bus, it is characterised in that
N data bus is divided into even signal line and odd signals line;
Each signal line in described even signal line provides the driving reverser that is alternately present and drives buffer, described in the driving reverser that is alternately present and drive buffer to couple successively;
Each signal line in described odd signals line provides the driving buffer that is alternately present and drives reverser, described in the driving buffer that is alternately present and drive reverser to couple successively;
Wherein, if first occurs that driving reverser in described even signal line, then in described odd signals line first occur that driving buffer, if in described even signal line first occur that driving buffer, then in described odd signals line first occur that driving reverser.
7. method as claimed in claim 6, it is characterised in that described n is 60.
8. method as claimed in claim 6, it is characterized in that, the driving reverser in each signal line in described even signal line is identical with the total sum of the driving reverser in each signal line in described odd signals line and driving buffer with the total sum driving buffer.
9. method as claimed in claim 6, it is characterised in that the number of the driving reverser in each signal line in described even signal line is identical with the number driving buffer; The number of the driving reverser in each signal line in described odd signals line is identical with the number driving buffer.
10. method as claimed in claim 6, it is characterised in that the number driving reverser in each signal line in described even signal line is 4, and the number of described driving buffer is 4; The number driving buffer in each signal line in described odd signals line is 4, and the number driving reverser is 4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201511023963.4A CN105653488A (en) | 2015-12-30 | 2015-12-30 | Circuit and method for lowering data coupling effect in long bus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201511023963.4A CN105653488A (en) | 2015-12-30 | 2015-12-30 | Circuit and method for lowering data coupling effect in long bus |
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| Publication Number | Publication Date |
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| CN105653488A true CN105653488A (en) | 2016-06-08 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201511023963.4A Pending CN105653488A (en) | 2015-12-30 | 2015-12-30 | Circuit and method for lowering data coupling effect in long bus |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102650977A (en) * | 2011-02-28 | 2012-08-29 | 海力士半导体有限公司 | Integrated circuit |
| US20130275646A1 (en) * | 2012-04-16 | 2013-10-17 | Fujitsu Semiconductor Limited | Bus circuit and semiconductor device |
-
2015
- 2015-12-30 CN CN201511023963.4A patent/CN105653488A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102650977A (en) * | 2011-02-28 | 2012-08-29 | 海力士半导体有限公司 | Integrated circuit |
| US20130275646A1 (en) * | 2012-04-16 | 2013-10-17 | Fujitsu Semiconductor Limited | Bus circuit and semiconductor device |
Non-Patent Citations (1)
| Title |
|---|
| 张钰磊: ""OLED驱动电路的研究与设计"", 《兰州交通大学》 * |
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Effective date of registration: 20161206 Address after: 200335 Shanghai city Changning District Admiralty road 767 Lane 3 Building No. 1 Applicant after: CHIP WEALTH TECHNOLOGY LTD. Address before: 710065 Shaanxi hi tech Zone, Xi'an Jin Road, No. 70 satellite building 2F Applicant before: XI'AN ZHONGYING ELECTRONIC Co.,Ltd. |
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| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20160608 |
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