CN105652948A - LDO external expansion circuit and method for manufacturing LDO external expansion structure thereof - Google Patents
LDO external expansion circuit and method for manufacturing LDO external expansion structure thereof Download PDFInfo
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- CN105652948A CN105652948A CN201410652727.8A CN201410652727A CN105652948A CN 105652948 A CN105652948 A CN 105652948A CN 201410652727 A CN201410652727 A CN 201410652727A CN 105652948 A CN105652948 A CN 105652948A
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Abstract
The invention provides an LDO external expansion circuit. The LDO external expansion circuit includes: an LDO chip which is provided with an input end and an output end; a PNP transistor which is provided with a collecting electrode, an emitting electrode and a base electrode, wherein the emitting electrode is connected to an input end of the LDO external expansion circuit and the collecting electrode is connected to an output end of the LDO external expansion circuit; and a pull-up resistor, wherein one end of the pull-up resistor is connected to the emitting electrode of the PNP transistor, and the other end of the pull-up resistor is connected to the base electrode of the PNP transistor, and the pull-up resistor is used for achieving electric potential pull-up of the base electrode; The input end of the LDO chip is connected to the base electrode and is connected to the input end of the LDO external expansion circuit via the pull-up resistor at the same time, and the output end of the LDO chip is connected to the output end of the LDO external expansion circuit, wherein the PNP transistor is used for driving a power output transistor of the LDO chip.
Description
Technical field
What the present invention relates to the LDO of a kind of novel big electric current low quiescent current realizes method, particularly relates to despreading circuit and LDO thereof outside a kind of LDO and extends out the manufacture method of structure.
Background technology
LDO (lowdropoutregulator, low pressure difference linear voltage regulator) it is a kind of linear voltage regulator, it is used in transistor or the FET of operation in its range of linearity, from the input voltage of application, deducts the voltage exceeded the quata, produce the output voltage through overregulating. The circuit design of LDO is relatively easy, and it is the low pressure difference linear voltage regulator of a kind of Micro Energy Lose, is generally of extremely low own noise and higher PSRR PSRR (PowerSupplyRejectionRatio). The structure of LDO low pressure difference linear voltage regulator mainly includes start-up circuit, constant-current source bias unit, enables circuit, adjusts element, a reference source, error amplifier, feedback resistive network and protection circuit etc.
The basic functional principle of LDO is such that system and powers up, if enable foot is in high level, circuit starts to start, constant-current source circuit provides biasing to whole circuit, a reference source voltage is quickly set up, export along with input constantly rises, when namely output be up to setting, the output feedack voltage obtained by feedback network is also close to reference voltage value, now the error small-signal between output feedack voltage and reference voltage is amplified by error amplifier, it is amplified to output then through adjusting pipe, thus forming negative feedback, ensure that output voltage stabilization is on setting, if in like manner input voltage change or output curent change, this closed loop will make output voltage remain unchanged, that is: Vout=(R1+R2)/R2 �� Vref.
The load driving force of LDO depends on the adjustment element of chip internal, being all generally built-in power tube, the area of this pipe is very big, and the driving force needed such as fruit chip is more big, area occupied by this pipe is also more big, and this means that the cost of this chip can be more high. PNP power tube is adopted to extend out driving as general LDO chip, on such LDO chip, most will be conserved for the area of power drive pipe, remaining internal drive pipe has only to retain the driving force of about 100mA and enough drives and extend out PNP power tube, the substitute is technical process simpler, the special PNP power tube chip that unit are current drive capability is higher, according to product, the actual demand of driving force is selected the PNP power tube chip of different area size, collocation so flexibly, cost can be realized be greatly reduced and being substantially improved of driving force simultaneously, to reach the optimal allocation of cost performance.
Summary of the invention
For the demand of industry, the present inventor proposes the method that realizes of the LDO of a kind of novel big electric current low quiescent current, adopts PNP power tube to drive pipe as extending out of general LDO chip, and two kinds of integrated chips encapsulation are realized novel LDO product. LDO chip used by assembled inside can be any type, have only to the driving force of about 100mA, just can putting the ability of large-drive-current by connecting the method for PNP power tube, the driving force of PNP power tube is more strong, adopts this to extend out the driving force of the LDO product after scheme also more strong. If the quick low-power consumption LDO chip adopting CMOS technology does PNP power tube and extends out the connection of scheme, it is possible to realize effective combination of ultra low quiescent current and super large driving force, obtain the LDO product that cost performance is superior simultaneously.
According to an aspect of the invention, it is provided the outer despreading circuit of a kind of LDO, including:
LDO chip, has input and outfan;
PNP pipe, has colelctor electrode, emitter stage and base stage, and wherein this emitter stage is connected to the input of the outer despreading circuit of this LDO and this colelctor electrode is connected to the outfan of the outer despreading circuit of this LDO; And
Pull-up resistor, one end of this pull-up resistor is connected to the emitter stage of this PNP pipe and the other end is connected to the base stage of this PNP pipe, and the current potential in order to realize this base stage pulls up;
Wherein, the input of this LDO chip is connected to this base stage and is connected to the input of the outer despreading circuit of this LDO simultaneously via this pull-up resistor, and the outfan of this LDO chip is connected to the outfan of the outer despreading circuit of this LDO,
Wherein, this PNP pipe is used as to drive the power output tube of this LDO chip.
It is preferred that in the outer despreading circuit of above-mentioned LDO, this PNP pipe is longitudinal P NP pipe.
It is preferred that in the outer despreading circuit of above-mentioned LDO, the pressure 20V that reaches of forward of this longitudinal P NP pipe, maximum drive current is up to 2A.
Preferably, in the outer despreading circuit of above-mentioned LDO, the electric current of the base stage of this PNP pipe is controlled by this LDO chip, and the outfan of this LDO chip samples the voltage of colelctor electrode of this PNP pipe, modulate the base current of this PNP pipe, so that the voltage of the outfan of the outer despreading circuit of this LDO remains stable for when various load current.
It is preferred that in the outer despreading circuit of above-mentioned LDO, the current potential of this base stage is pulled up by this pull-up resistor, it is ensured that when LDO chip turns off, this PNP pipe is also switched off.
According to a further aspect in the invention, it is provided that a kind of LDO extends out the manufacture method of structure, this LDO extends out structure and is made up of PNP pipe and resistance, and this manufacture method includes:
A. providing substrate, this substrate is used as the colelctor electrode of this PNP pipe, and this substrate comprises PNP district and resistance area;
The both sides of the both sides and this resistance area of b. distinguishing Gai PNP district form isolation under p-type;
C. deposition n-extension, this n-extension is cut off by isolation under this p-type to form n-epi island;
D., isolation is formed isolation in p-type under this p-type;
E. forming multiple n+ district on this n-epi island, at least two n+ district that Zhong n+ district of this PNP district is used as in base stage and this resistance area is used separately as two contact jaws of this resistance;
F. forming multiple p+ district on the n-epi island in Gai PNP district, Zhong p+ district of this PNP district is used as emitter stage to form this PNP pipe.
It is preferred that in above-mentioned manufacture method, this substrate is p+/p-type epitaxial substrate.
It is preferred that in above-mentioned manufacture method, in above-mentioned steps c, the concentration of this n-extension and thickness be adjusted so that the beta value of this PNP pipe when 1A drives electric current more than 100, and the forward of this PNP pipe is pressure more than 20V.
It is preferred that in above-mentioned manufacture method, in above-mentioned steps e, carry out the extraction of the base stage of this PNP pipe and the extraction of two contact jaws of this pull-up resistor while this n-epi island forms multiple n+ district.
It is preferred that in above-mentioned manufacture method, in above-mentioned steps f, carry out the extraction of the emitter stage of this PNP pipe while the n-epi island in Gai PNP district forms multiple p+ district.
To sum up, a kind of novel LDO that proposes of the present invention extends out scheme, and wherein LDO extends out structure is longitudinal power P NP pipe that one is integrated with high pressure resistant, high-amplification-factor, the big electric current of pull-up resistor (such as 2Kohm).
Should be appreciated that more than the present invention general describes and the following detailed description is all exemplary and explanat, and it is intended that the present invention being somebody's turn to do such as claim provides further explanation.
Accompanying drawing explanation
Being that they are included and constitute the part of the application in order to provide further understanding of the invention including accompanying drawing, accompanying drawing illustrates embodiments of the invention, and plays the effect explaining the principle of the invention together with this specification. In accompanying drawing:
Fig. 1 is the circuit diagram of an embodiment of the outer despreading circuit of the LDO according to the present invention.
Fig. 2 is the electrical block diagram of an embodiment of the LDO chip used in the present invention.
Fig. 3 is the LDO of the present invention cross-sectional view extending out structure.
Fig. 4 is the LDO of the present invention process chart extending out the manufacture method of structure.
Fig. 5 is the dual chip integration packaging routing schematic diagram of the present invention.
Detailed description of the invention
With detailed reference to accompanying drawing, embodiments of the invention are described now. Now with detailed reference to the preferred embodiments of the present invention, its example is shown in the drawings. In the case of any possible, identical labelling will be used to represent same or analogous part in all of the figs. In addition, although the term used in the present invention is to select from public term, but some terms mentioned in description of the present invention are probably what applicant selected by his or her judgement, its detailed meanings explanation in the relevant portion of description herein. Additionally, require not only by the actual terms used, and it is also to the meaning by each term contains and understands the present invention.
The LDO of the present invention extends out scheme and preferably employs longitudinal power P NP audion, and use LDO chip to carry out the implementation control of the base current to PNP triode, the collector voltage of PNP pipe of simultaneously sampling with the outfan of LDO, collector voltage is made to remain the output voltage values of LDO, whole closed loop constitutes stable negative feedback, and power P NP pipe is equivalent to the external Current amplifier adjustment pipe of LDO. This PNP power tube requires to reach the Application Design target of high pressure, high-gain, big electric current. It is attempted by PNP pipe E pole and resistance that B extremely goes up, when built-in LDO chip is in the situation of closedown, guaranteed output PNP pipe is also at the off state determined, when built-in LDO chip is started working, when pressure drop reaches VBE threshold value after the overcurrent of resistance upper reaches, now PNP pipe is opened and is entered the duty that electric current drives.
Circuit diagram with reference first to the embodiment that Fig. 1, Fig. 1 are the outer despreading circuit of the LDO according to the present invention. As it can be seen, the outer despreading circuit 100 of this LDO mainly includes LDO chip 101, PNP pipe 102 and pull-up resistor 103. This PNP pipe 102 is used as to drive the power output tube of this LDO chip 101.
LDO chip 101 has input and outfan. It is connected to the input Vin of the outer despreading circuit 100 of this LDO via this pull-up resistor 103 while that the input Ido_vdd of this LDO chip 101 being connected to the base stage C of PNP pipe 102. Additionally, the outfan Ido_out of this LDO chip 101 is connected to the output end vo ut of the outer despreading circuit 100 of this LDO.
PNP pipe 102 has colelctor electrode C, emitter E and base stage B. This emitter E is connected to the input Vin and this colelctor electrode C of the outer despreading circuit 100 of this LDO and is connected to the output end vo ut of the outer despreading circuit 100 of this LDO. Wherein, this PNP pipe 102 is that pressure 20V and the maximum drive current longitudinal P NP up to 2A that reaches of forward manages. LDO chip 101 is as the control unit of the base current of PNP pipe 102, by the feedback to Vout terminal voltage, the base current of modulation PNP pipe 102, it is ensured that loop Vout end voltage stabilization when various load current.
Such as, Fig. 2 illustrates an embodiment of the LDO chip (the LDO chip 102 in such as Fig. 1) used in the present invention. Wherein, sampling voltage is added in the in-phase input end of amplifier A, and compared with the reference voltage V ref being added in inverting input, both amplified device A of difference control series connection and adjust the pressure drop of pipe after amplifying, thus regulated output voltage. When output voltage Vout reduces, the difference of reference voltage and sampling voltage increases, and the driving electric current of comparison amplifier output increases, and series connection adjusts tube voltage drop and reduces, so that output voltage raises. On the contrary, if output voltage Vout exceedes required setting value, the front wheel driving electric current of comparison amplifier output reduces, so that output voltage reduces. In power supply process, output voltage correction continuously performs, and the adjustment time is only limited by comparison amplifier and the restriction of output transistor loop response speed. Certainly, the invention is not limited in the LDO chip shown in Fig. 2, the LDO chip made for any technique can use the solution of the present invention, if adopting the LDO chip of CMOS technology, cost performance can be higher, it is possible to easily realizes ultra low quiescent current and the combination of big driving force. This novel LDO product, quiescent current and LDO chip used by assembled inside are basically identical, and speed can be slightly faster than LDO chip used by assembled inside, and noise isolation effect is constant.
One end of pull-up resistor 103 is connected to the emitter stage C of this PNP pipe 102 and the other end is connected to the base stage B of this PNP pipe 102, and the current potential in order to realize this base stage B pulls up. Such as, the current potential of this base stage B is pulled up by this pull-up resistor 103, it is ensured that when LDO chip 101 turns off, this PNP pipe 102 is also switched off.
In the outer despreading circuit 100 of above-mentioned LDO, the electric current of the base stage B of this PNP pipe 102 is controlled by this LDO chip 101, and the outfan of LDO chip 101 samples the voltage of colelctor electrode C of this PNP pipe 102, modulate the base current of this PNP pipe 102, so that the voltage of the output end vo ut of the outer despreading circuit 100 of this LDO remains stable for when various load current.
Additionally, for the LDO chip having en end, for instance the LDO chip 101 shown in the embodiment of Fig. 1, the scheme that extends out of the present invention can be applied equally to this kind of LDO chip, having only to when integration packaging, EN end is individually drawn, it is still effective that chip is enabled control by such EN end.
Hereinafter, discuss the LDO according to the present invention in detail in conjunction with Fig. 3 and Fig. 4 and extend out the manufacture method of structure. Wherein, this LDO extends out structure and is made up of PNP pipe (PNP pipe 102 as shown in Figure 1) and resistance (pull-up resistor 103 as shown in Figure 1).
As it is shown on figure 3, be the cross-sectional view of longitudinal power P NP integrated pull-up resistor of pipe of the present invention. Wherein, PNP pipe is adopted longitudinal positive-negative-positive structure and is realized, and colelctor electrode is drawn by substrate, adopts the P+/P-type extension base material of customization, takes into account consideration PNP pipe collector series resistance and B, C knot is pressure. By controlling resistivity and the thickness of N-epitaxial layer in technique, and P+ type launch site inject and annealing conditions, accurately control emitter stage junction depth, reach longitudinal P NP pipe beta and the best compromise of forward pressure (BVCE0), typical case's beta value is when 1A drives electric current more than 100, and corresponding chip area is 0.4mm2, BVCE0 is more than 20V simultaneously. Resistance adopts the separation N-epi island that the isolation of P type is irised out to realize, resistance 2Kohm.
As shown in Figure 4, the LDO of the present invention extends out the manufacture method 400 of structure and mainly includes following step:
Step 401: substrate (P+SUB in Fig. 3) is provided, this substrate is preferably p+/p-type epitaxial substrate, and this substrate is used as the colelctor electrode of this PNP pipe, this substrate comprises PNP district (with reference to Fig. 3) and resistance area (with reference to Fig. 3), wherein, preferably, the p+ part of substrate is used as the colelctor electrode of PNP pipe and draws, should be as far as possible dense, so can reduce collector series resistance, improve the driveability of power P NP pipe, the p-part of substrate be consider process heat process cause p+ on climb over and cross, simultaneously as the colelctor electrode of power P NP pipe;
Step 402: the both sides in Gai PNP district and the both sides of this resistance area form isolation (BP in Fig. 3) under (such as selecting to be injected into ad-hoc location) p-type by photoetching respectively, play the isolation n-effect being extended to, wherein the concentration of N-extension and thickness are very crucial, directly affect the beta of power P NP pipe and pressure, by adjusting, can reaching typical case's beta value when 1A drives electric current more than 100, corresponding chip area is 0.4mm2, BVCE0 is more than 20V simultaneously;
Step 403: deposition n-extension (N-epi in Fig. 3), this n-extension is cut off by isolation under this p-type to form n-epi island, wherein the concentration of this n-extension and thickness be adjusted so that the beta value of this PNP pipe when 1A drives electric current more than 100, and the forward of this PNP pipe is pressure more than 20V;
Step 404: form isolation (DP in Fig. 3) in p-type under this p-type in isolation, this p-type is isolated DP and lower isolation BP to, after leading to, irising out different N-epi island, be used separately as PNP power tube and pull-up resistor;
Step 405: form (such as being injected by photoetching) multiple n+ district (Fig. 3 Zhong n+ district) on this n-epi island, the at least two n+ district that Zhong n+ district of this PNP district is used as in base stage and this resistance area is used separately as two contact jaws of this resistance, wherein preferably in the extraction of two contact jaws of the extraction of base stage and this pull-up resistor that carry out this PNP pipe while forming multiple n+ district on this n-epi island;
Step 406: form multiple p+ district (Fig. 3 Zhong p+ district) on the n-epi island in Gai PNP district, Zhong p+ district of this PNP district is used as emitter stage to form this PNP pipe, wherein preferably in the extraction of the emitter stage carrying out this PNP pipe while forming multiple p+ district on the n-epi island in this PNP district, in addition, in this step, by finely tuning the annealing thermal process after injecting, it is accurately controlled emitter stage junction depth, take into account the high power longitudinal gain to PNP pipe and pressure, make up to optimum balance.
Finally, completing passivation pressure point technique and thinning back of the body gold, the colelctor electrode of power P NP pipe is directly drawn from the substrate of chip.
As shown in Figure 5, dual chip integration packaging routing schematic diagram example for the present invention, it is the packing forms of TO-252, it is illustrated that chips A is integrated with E extremely longitudinal P NP power tube chip to B pole pull-up resistor, during driving force that chip B is general is more weak, forces down power consumption high speed LDO chip. Chip A adopts conducting resinl attachment, the substrate colelctor electrode of power tube is attached directly on the chassis of package carrier, corresponding foot position PIN2, it is taken as extending out the output Vout end of scheme LDO, the emitter stage routing of power tube PNP pipe is connected on the PIN3 of foot position, is taken as extending out the output Vin end of scheme LDO. Chip B adopts insulating cement attachment, the input routing of built-in LDO chip is connected to the base stage of chip A, its output feedack end routing is connected to the chassis of package carrier, connect with A chipset electrode, the GND end routing of built-in LDO chip is connected on the PIN1 of foot position, is taken as extending out the output GND end of scheme LDO.
Those skilled in the art can be obvious, the above-mentioned exemplary embodiment of the present invention can be carried out various modifications and variations without departing from the spirit and scope of the present invention. Accordingly, it is intended to make the present invention cover the amendment to the present invention and modification dropping within the scope of appended claims and equivalent arrangements thereof.
Claims (10)
1. the outer despreading circuit of LDO, it is characterised in that including:
LDO chip, has input and outfan;
PNP pipe, has colelctor electrode, emitter stage and base stage, and wherein said emitter stage is connected to the input of the outer despreading circuit of described LDO and described colelctor electrode is connected to the outfan of the outer despreading circuit of described LDO; And
Pull-up resistor, one end of described pull-up resistor is connected to the emitter stage of described PNP pipe and the other end is connected to the base stage of described PNP pipe, and the current potential in order to realize described base stage pulls up;
Wherein, the input of described LDO chip is connected to described base stage and is connected to the input of the outer despreading circuit of described LDO simultaneously via described pull-up resistor, and the outfan of described LDO chip is connected to the outfan of the outer despreading circuit of described LDO,
Wherein, described PNP pipe is used as to drive the power output tube of described LDO chip.
2. the outer despreading circuit of LDO as claimed in claim 1, it is characterised in that described PNP pipe is longitudinal P NP pipe.
3. the outer despreading circuit of LDO as claimed in claim 2, it is characterised in that the forward of described longitudinal P NP pipe is pressure for 20V, and maximum drive current is 2A.
4. the outer despreading circuit of LDO as claimed in claim 1, it is characterized in that, the electric current of the base stage of described PNP pipe is controlled by described LDO chip, and the outfan of described LDO chip samples the voltage of colelctor electrode of described PNP pipe, modulate the base current of described PNP pipe, so that the voltage of the outfan of the outer despreading circuit of described LDO remains stable for when various load current.
5. the outer despreading circuit of LDO as claimed in claim 1, it is characterised in that the current potential of described base stage is pulled up by described pull-up resistor, it is ensured that described PNP pipe is also switched off when LDO chip turns off.
6. LDO extends out a manufacture method for structure, and described LDO extends out structure and is made up of PNP pipe and resistance, it is characterised in that this manufacture method includes:
A. providing substrate, described substrate is used as the colelctor electrode of described PNP pipe, and described substrate comprises PNP district and resistance area;
B. isolation under p-type is formed respectively in the both sides of the both sides in described PNP district and described resistance area;
C. deposition n-extension, described n-extension is cut off by isolation under described p-type to form n-epi island;
D., isolation is formed isolation in p-type under described p-type;
E. forming multiple n+ district on described n-epi island, at least two n+ district that Zhong n+ district of described PNP district is used as in base stage and described resistance area is used separately as two contact jaws of described resistance;
F. forming multiple p+ district on the n-epi island in described PNP district, Zhong p+ district of described PNP district is used as emitter stage to form described PNP pipe.
7. manufacture method as claimed in claim 6, it is characterised in that described substrate is p+/p-type epitaxial substrate.
8. manufacture method as claimed in claim 6, it is characterised in that in above-mentioned steps c, the concentration of described n-extension and thickness be adjusted so that the beta value of described PNP pipe when 1A driving electric current more than 100, and the forward of described PNP pipe is pressure more than 20V.
9. manufacture method as claimed in claim 6, it is characterised in that in above-mentioned steps e, carry out the extraction of the base stage of described PNP pipe and the extraction of two contact jaws of described pull-up resistor while forming multiple n+ district on described n-epi island.
10. manufacture method as claimed in claim 6, it is characterised in that in above-mentioned steps f, carry out the extraction of the emitter stage of described PNP pipe while the n-epi island in described PNP district forms multiple p+ district.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410652727.8A CN105652948A (en) | 2014-11-17 | 2014-11-17 | LDO external expansion circuit and method for manufacturing LDO external expansion structure thereof |
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| CN201410652727.8A CN105652948A (en) | 2014-11-17 | 2014-11-17 | LDO external expansion circuit and method for manufacturing LDO external expansion structure thereof |
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| CN106292823A (en) * | 2016-08-31 | 2017-01-04 | 苏州纳芯微电子股份有限公司 | A kind of high-low pressure converts integrated circuit |
| CN108122908A (en) * | 2016-11-30 | 2018-06-05 | 上海岭芯微电子有限公司 | A kind of high voltage positive-negative-positive counnter attack fills analog line driver and its manufacturing method |
| CN111063723A (en) * | 2019-11-25 | 2020-04-24 | 深圳深爱半导体股份有限公司 | Switch integrated controller and triode chip |
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Application publication date: 20160608 |