CN105632431B

CN105632431B - Controller and display device with improved performance and associated methods

Info

Publication number: CN105632431B
Application number: CN201510639883.5A
Authority: CN
Inventors: M·M·E·厄尔赛亚德; K·W·弗纳尔德
Original assignee: Silicon Laboratories Inc
Current assignee: Silicon Laboratories Inc
Priority date: 2014-11-26
Filing date: 2015-09-30
Publication date: 2020-07-10
Anticipated expiration: 2035-09-30
Also published as: CN105632431A

Abstract

A device includes a multiplexed liquid crystal display (L CD) controller. L CD controller operates in at least first and second phases of operation. L CD controller drives a plurality of first signal lines to a first set of voltages during the first phase of operation and to a second set of voltages during the second phase of operation. L CD controller selectively couples at least some of the plurality of signal lines to a node between the first and second phases of operation based on data provided to the L CD controller.

Description

Controller and display device with improved performance and associated methods

Cross Reference to Related Applications

This application is a continuation-in-part application of pending U.S. patent application No.13/720,037 entitled "Controller and Display Apparatus with Improved Performance and associated Methods" filed on 19/12/2012, attorney docket No. SI L a 345.

Technical Field

The disclosed concepts relate generally to display devices and related methods. More particularly, the present disclosure relates to devices with improved performance of displays and drivers through segment resetting and associated methods.

Background

Various types of electronic devices and systems use displays. The display provides the ability to present information to a user of the device or system. In some examples, the display also provides functionality to accept information (e.g., input) from a user.

L CD is ubiquitous in a variety of electronic devices and displays L CD consumes less power than other types of displays, such as fluorescent or light emitting diode (L ED) displays, which contributes in part to its relative popularity.

In some L CDs, the order of the L CD phases has been rearranged to reduce the power consumption of the L CD those of ordinary skill in the art understand the details of this technique L CDs that are not rearranged may have phases arranged by [0, 1, 2, 3, 4, 5, 6, 7] to reduce the number of voltage level transitions of the L CD common line, the order of the L CD phases may be rearranged by [0, 2, 4, 6, 1, 3, 5, 7] this technique may provide approximately 17% power savings compared to the L CD that is not rearranged.

Disclosure of Invention

According to the present disclosure, various embodiments are contemplated.A device according to one exemplary embodiment includes a multiplexed liquid crystal display (L CD) controller. L CD controller operates in at least first and second phases of operation. L CD controller drives a plurality of first signal lines to a first set of voltages during the first phase of operation and to a second set of voltages during the second phase of operation. L CD controller selectively couples at least some of the plurality of signal lines to a node between the first and second phases of operation based on data provided to the L CD controller.

In accordance with data provided to the L CD controller, the controller selectively performs a segment reset between the first and second operating phases of the L CD.

According to yet another exemplary embodiment, a method of operating L CDs includes operating a L CD in a first operating phase and selectively performing a segment reset based on data provided to a L CD controller after operating a L CD in the first operating phase the method further includes operating a L CD in a second operating phase after performing the selective segment reset.

Drawings

The drawings illustrate only exemplary embodiments and are therefore not to be considered limiting of its scope. Those of ordinary skill in the art will recognize that the disclosed concepts lend themselves to other equally effective embodiments. In the drawings, the same numerical designators used in more than one drawing denote the same, similar, or equivalent functionality, components, or blocks.

Fig. 1 illustrates a circuit arrangement according to an exemplary embodiment.

Fig. 2 shows a multiplex L CD used in an exemplary embodiment.

Fig. 3 illustrates a segmented capacitance in an exemplary embodiment.

Fig. 4 depicts an L CD control signal, according to an example embodiment.

Fig. 5 illustrates a conventional L CD segment switch.

FIG. 6 depicts a segment reset between phases in accordance with an exemplary embodiment.

Fig. 7 shows a block diagram of a circuit arrangement for a segmented reset using multiple reset schemes according to an example embodiment.

Fig. 8 depicts a set of waveforms for determining a primary voltage(s) used in segment resetting in accordance with an exemplary embodiment.

Fig. 9 shows a block diagram of the controller 15 according to an exemplary embodiment.

Fig. 10 illustrates L CD waveform transitions in an exemplary embodiment.

Fig. 11 illustrates a segment switch based on L CD data values, according to an example embodiment.

Fig. 12 depicts a segment reset based on L CD data values in accordance with an exemplary embodiment.

Fig. 13 illustrates a flowchart of a data dependent L CD segment switching method in accordance with an exemplary embodiment.

FIG. 14 shows L CDs in a common line scan ordering according to an example embodiment.

Fig. 15 depicts a conventional common line scan.

FIG. 16 illustrates a common line scan order in accordance with an exemplary embodiment.

Fig. 17 shows a flowchart of a data-dependent common line scanning method according to an exemplary embodiment.

Detailed Description

More specifically, the disclosed concepts provide a method for a device with an L CD and/or controller or drive having improved performance, e.g., lower or relatively lower power consumption as compared to conventional L CD/drives.

Segment resets can be applied to both the common and segment lines to short or couple the segment capacitors to a known or desired voltage, as described in detail below.

FIG. 1 illustrates a circuit arrangement 10 according to an exemplary embodiment, the circuit arrangement 10 includes a controller or drive 15 and an L CD or L CD panel 20. the controller 15 controls the operation of the L CD20 using a coupling mechanism 25. the coupling mechanism 25 allows control signals to be transmitted from the controller 15 to the L CD 20. furthermore, the coupling mechanism 25 can provide for the transmission of other signals, e.g., status signals, between the controller 15 and the L CD20 as needed.

The coupling mechanism 25 may take a variety of forms as desired, generally, the coupling mechanism 25 includes conductive elements that provide an electrical connection or coupling between the controller 15 and the L CD 20. for example, in certain embodiments, the coupling mechanism 25 may include Printed Circuit Board (PCB) traces.

As noted, in the exemplary embodiment, L CD20 is multiplex L CD FIG. 2 shows multiplex L CD20 used in the exemplary embodiment L CD20 includes a plurality of seven segment displays or digits, a configuration well known to those of ordinary skill in the art, for example, the left digit has seven segments labeled 20A-20G L CD controller 15 (not shown) drives these segments 20A-20G to display numeric (and some letter) information on the display similar driving techniques apply to the other portions of L CD 20.

However, L CD20 uses multiplexing to reduce the number of signal lines, and thus the number of conductors or linkages, in the example shown, controller 15 (not shown) controls or drives L CD20 using two sets of signals, a common signal or line (labeled COM0 through COM3) and a segmented signal or line (labeled SEG0 through SEG 6).

Note that the number and configuration of common and segment lines or signals in FIG. 2 provide only an example other configurations using other numbers of signals may be used in other embodiments as desired.

L CD20 has a capacitance 30 associated with its segment, as shown in FIG. 3, specifically FIG. 3 presents a L CD segment as capacitance 30 between the common and segment lines, in other words, the segments of L CD20 produce respective capacitances 30 arranged at the intersections of the common and segment lines, for example, the segment coupled between common line COM0 and segment line SEG0 (in the upper left corner of FIG. 3) is represented by capacitor 30, etc. by using multiplexing, this arrangement reduces the number of signal lines that the controller uses to drive L CD20, however, doing so makes the driving waveform more complex as the controller changes the waveform as a function of time (even for unchanged display results) to perform multiplexing, controller 15 controls or drives L CD20 by resetting the segments of L CD20, as described in detail below.

Note that fig. 3 shows capacitors 30 of an exemplary L CD the illustrated example takes four common lines COM0-COM3 and seven segment lines SEG0-SEG6 however, as will be appreciated by those of ordinary skill in the art, other L CD configurations (e.g., different number of segments), different numbers of common and/or segment lines, etc. may be used and may result in different configurations and/or numbers of capacitors 30 and may also result in different waveforms for driving the common and/or segment lines.

In an exemplary embodiment, the drive 15 controls L the CD20 using time division multiplexing the number of time divisions (or phases) in a multiplexing scheme is typically twice the number of common lines used in L the CD 20. for example, a 2x multiplex L CD has two common lines COM0 and COM1 and uses four phases, while a 4x multiplex L CD has common lines COM0 to COM3 and uses eight phases.

Controller 15 uses different voltage levels to generate appropriate waveforms for driving L CD20, sometimes described as "bias" for L CD for example, "half bias" L CD may have three bias voltage levels, e.g., 0, 1/2V, and V, where V may represent a voltage, such as a supply voltage, where 1/2V is often derived from the supply voltage, e.g., using a resistive divider.

Other voltage generation schemes or biasing and/or multiplexing techniques may be used depending on the desired specifications of the controller and/or L CD.

L CD is typically responsive to the Root Mean Square (RMS) voltage applied to these segments and not to attributes such as the polarity of the voltage, so that a L CD segment may be "ON" (ON) when the RMS voltage applied to that segment exceeds a threshold (which, as will be appreciated by those of ordinary skill in the art, depends ON a number of factors such as the design or specification of L CD 20.) the controller 15 provides a voltage or signal to the L CD20 to "turn ON" the appropriate segment for the desired display.

To meet those specifications, the controller 15 applies voltage pulses or signals having varying levels to the segments of L CD20, as shown in FIG. 4.

4A-4D show a conventional waveform applied to a common line of control L CD A controller corresponding to the waveform in FIG. 4 has four common lines COM0-COM3 and eight operating phases represented as phases 0-7.

The segment lines are driven by voltages that vary according to the desired data of the display (not shown in fig. 4). As shown in fig. 4, these common lines are driven by time-shifted versions of the same voltage waveform. More specifically, the waveforms in FIG. 4B are time-shifted (right-shifted) versions of the waveforms in FIG. 4A. Similarly, the waveforms in FIG. 4C are time-shifted versions of the waveforms in FIG. 4B. Finally, the waveforms in FIG. 4D constitute a time-shifted version of the waveforms in FIG. 4C.

In contrast, conventional L CD controllers charge and discharge segmented capacitors by using more charge supplied from the power supply.

Fig. 5, consisting of fig. 5A-5C, depicts an example of segment switching in a conventional L CD, more specifically, fig. 5 shows how the voltage across segment capacitor 36 is switched in response to a command or control signal from a controller (not shown.) switches 39 and 42 are controlled switches and are responsive to a L CD controller (not shown.) switches 39 and 42 switch the terminals of capacitor 36 between power supply 38 (in this case a 3V supply) and ground potential.

In fig. 5A, a switch 39 couples the left terminal of capacitor 36 to power source 38. Similarly, switch 42 couples the right terminal of capacitor 30 to ground 33. A power supply 38 provides charge to the capacitor 36. As a result, capacitor 36 eventually charges to supply voltage 3V with a time constant that depends on circuit component values and parasitic elements, as understood by those of ordinary skill in the art. The power supply 38 provides an absolute (irrespective of the direction of current flow) charge Q ═ CV, where V ═ 3 volts, or Q ═ 3C, where C is the value of the capacitor.

Conventional L CD controllers typically use a break-before-make (break-before-make) switch control scheme, as shown in fig. 5B, thus, the controller causes

switches

39 and 42 to open before changing or switching the voltage across capacitor 36, assuming charge leakage is negligible, the voltage across capacitor 36 remains at about 3V, i.e., the terminal charging voltage from the configuration in fig. 5A.

In fig. 5C, a controller (not shown) couples switch 39, thereby grounding the left terminal of capacitor 36. similarly, switch 42 couples the right terminal of capacitor 36 to power supply 38 using the notation convention of fig. 5A, the capacitor is now charged to-3V.

In an exemplary embodiment, the charge supplied from the power supply 30 may be reduced by resetting the segment between the operating phases of the controller (or L CD). fig. 6, which includes fig. 6A-6C, shows details of such operation according to an exemplary embodiment.

More specifically, fig. 6 shows how the voltage across the segmented capacitor 30 is switched in response to a command or control signal from the controller 15 (not shown).

Switches

39 and 42 are controlled switches and are responsive to controller 15.

Switches

39 and 42 switch the terminals of capacitor 30 having capacitance C between power supply 38 (in this example a 3V supply) and ground potential.

Referring to fig. 6A, during one phase of operation, e.g., phase 0, controller 15 causes switch 39 to couple the left terminal of capacitor 30 to power supply 38. Similarly, the controller 15 causes the switch 42 to couple the right terminal of the capacitor 30 to ground. As a result, the power supply 38 provides charge to the capacitor 30. As a result, the capacitor 30 is eventually charged to the supply voltage (3V in this example) with a time constant that depends on the circuit component values and parasitic elements. The power supply 38 provides an absolute (irrespective of the direction of current flow) charge Q ═ CsV, where Cs denotes the capacitance of the capacitor 30 and V ═ 3 volts, which yields Q ═ 3 Cs.

Referring to fig. 6B, this figure illustrates how the

switches

39 and 42 are configured between a first phase (phase 0 in this example) and a next phase (phase 1 in this example). More specifically, switches 39 and 42 are controlled by controller 15 to couple the terminals of capacitor 30 to a desired node, point or voltage (typically Vrst). In the example shown, switches 39 and 42 are controlled by controller 15 so as to couple the terminals of capacitor 30 to ground potential, i.e. to ground 33.

In this way, the segment corresponding to the capacitor 30 is reset. This operation does not draw any current or charge from the power supply 38 because any current from one terminal of the capacitor 30 flows through the node (ground 33 in this example) and reaches the other terminal of the capacitor 30.

Finally, referring to fig. 6C, controller 15 causes switch 39 to couple the left terminal of capacitor 30 to ground 33. Similarly, the controller 15 causes the switch 42 to couple the right terminal of the capacitor 30 to the power source 38. Using the notation convention of fig. 6A, the capacitor is now charged to-3V. Because the voltage change across capacitor 30 is from 0 volts to-3V (or typically-Vs, where Vs represents the supply voltage), power supply 38 provides an absolute charge Q ═ CsV, where V ═ 3 volts, or Q ═ 3 Cs.

The above-described segmented reset thus results in the power supply 38 providing a reduced total charge for charging and discharging the capacitor 30. As a result, the power dissipation of the L CD and/or the controller/L CD combination is reduced.

It is noted that the capacitor 30 shown in fig. 6 constitutes one segmented capacitor as will be appreciated by those of ordinary skill in the art, and as illustrated in fig. 3, multiple capacitors 30 may be used in a practical implementation as desired, the segment reset described above may be applied to the capacitors 30 in such an arrangement, furthermore, as will be appreciated by those of ordinary skill in the art, with reference to the switching examples shown in fig. 5 and 6, the controller may switch L CD segments between voltage values other than 3V and 0V.

Instead of coupling capacitor 30 to ground to achieve a segmented reset, other arrangements may be used. In general, a segmented reset may be performed by coupling capacitors 30 together, or coupling capacitors 30 together to a voltage source or potential (e.g., bias voltage) Vrst.

Fig. 7 shows a block diagram of a circuit arrangement 50 for a segmented reset using a plurality of reset schemes. Note that fig. 7 shows one output of the bias voltage generator 80 for convenience of introducing the concept, although as understood by those of ordinary skill in the art, the bias voltage generator 80 may have a plurality of outputs (not shown) coupled to the common line and the segment line through additional switches (not shown). A more general block diagram of the controller 15 appears in fig. 9.

Referring back to fig. 7, the array of capacitors 30 is similar to the configuration shown in fig. 3. Similar to fig. 3, the example shown in fig. 7 includes four common lines (COM0-COM3) and seven segment lines (SEG0-SEG 6). Referring to fig. 7, the controller 15 includes a plurality of switches that allow common lines and/or segment lines to be coupled to the node 70. More specifically, the controller 15 includes switches 53A-53D that are coupled to COM0-COM3, respectively, and also to node 70.

By controlling one or more switches 53A-53D, the controller 15 is able to couple one or more common lines COM0-COM3, respectively, to the node 70. For example, switches 53A and 53C are caused to closely couple common lines COM0 and COM2 to node 70. As another example, closing switches 53A-53D causes all common lines (COM0-COM3) to be coupled to node 70.

Controller 15 also includes switches 65A-65G. Switches 65A-65G are coupled to segment lines SEG0-SEG6, respectively. By controlling one or more switches 65A-65G, controller 15 is able to couple one or more segment lines SEG0-SEG6, respectively, to node 70. For example, switches 65B and 65F are caused to close couple segment lines SEG1 and SEG5 to node 70. As another example, closing switches 65A-65G causes all segment lines (SEG0-SEG6) to be coupled to node 70.

Further, the controller 15 includes a switch 75 capable of coupling the node 70 to an output of the bias voltage generator 80. Bias generator 80 may provide a desired bias level at its output, such as ground potential, or other desired potential (e.g., a primary voltage, as described in detail below), typically Vrst as indicated above. Controller 15 can couple the output of bias voltage generator 80 to node 70 by controlling switch 75.

In the exemplary embodiment, controller 15 uses switches 53A-53D, switches 65A-65G, and switch 75 to perform a step reset between the two operating phases. The use of switches 53A-53D, switches 65A-65G, and switch 75 with bias generator 80 allows for a variety of segmented reset operations. The choice of segment reset depends on a number of factors such as design and performance specifications, e.g., the degree of power dissipation reduction required, the level of parasitics present, etc.

In certain embodiments, controller 15 causes switches 53A-53D and switches 65A-65G to close in order to perform a segment reset. Closing switches 53A-53D and switches 65A-65G causes common line COM0-COM3 and segment lines SEG0-SEG6 to be coupled together (or to node 70) through node 70. The switch 75 remains open. This configuration causes segment reset by: common line COM0-COM3 is brought to the same voltage or potential as segment line SEG0-SEG6, thereby returning the charge on all segment capacitances coupled between COM0-COM3 and SEG0-SEG6 to zero.

In certain embodiments, controller 15 causes switches 53A-53D, switches 65A-65G, and switch 75 to close in order to perform a segment reset. Closing switches 53A-53D and switches 65A-65G causes common line COM0-COM3 and segment lines SEG0-SEG6 to be coupled together (or to node 70) through node 70. Switch 75 couples node 70 to the output of bias generator 80. Thus, in this configuration, segment reset is performed by applying the voltage at the output of the bias generator 80 to the common line COM0-COM3 and the segment lines SEG0-SEG 6.

Various output voltages or potentials may be supplied by bias generator 80 (typically Vrst, as noted above). In some configurations, the segment reset is performed by bias generator 80 coupling node 70 to ground potential via switch 75. In some embodiments, the segment reset is performed by bias generator 80 coupling node 70 to the desired potential via switch 75. The potential may constitute a bias voltage, a primary voltage (as described in detail below), or some other voltage. As understood by those of ordinary skill in the art, fig. 9 illustrates one possible implementation of the controller 15. Numerous other embodiments are possible and contemplated. For example, in some embodiments, switch 75 may not be used and bias generator 80 may not drive a potential onto node 70, or bias generator 80 may continuously drive a potential onto node 70.

As noted above, FIG. 7 presents a block diagram, actual implementations of controller 15 may use additional switches or other components for the common and segment lines, as desired, hi addition, bias generator 80 may provide more bias voltages, as desired, depending on the type of L CD panel, the type of control, etc. FIG. 9 shows a more general block diagram of controller 15.

In some cases, parasitic elements in the circuit (e.g., parasitic capacitances in the driver 15), interconnects (e.g., coupling mechanism 25 in FIG. 1), and/or the L CD20 may contribute to additional charge transfer from the power source 38.

In some embodiments, there may be parasitic capacitors coupled to or associated with the signal lines that couple the controller to L CD, as described above, the parasitic capacitors coupled to those signal lines will discharge if they are coupled to ground between phases during the segment reset.

Typically, to remedy the additional power dissipation due to parasitic effects, rather than resetting the segments by coupling the segmented capacitor 30 to ground 33 (see fig. 6), the segments are reset by coupling the segmented capacitor 30 to the primary voltage of a given operating phase (e.g., the current phase). In other words, segment resets are performed by coupling the common and segment lines to the same node (e.g., node 70 in fig. 7) and/or to the same potential (e.g., the output of bias generator 80 in fig. 7) between the operating phases, where the potential is the primary voltage for a given phase, as discussed below. Fig. 8 shows waveforms for deriving, selecting or determining the main voltage.

Specifically, FIG. 8 shows the waveforms of the common line COM0-COM3 of the L CD controller, note that the waveforms in FIG. 8 are similar to those in FIG. 4, but FIG. 8 shows typical voltage levels of the common line during each phase, which can be used to select or derive or determine the primary voltage.

Referring to the examples illustrated in fig. 8A to 8D, note that three of the four common lines have the same drive voltage, i.e., the main voltage, during any given phase. For example, during phase 3, the common line COM0, COM2, and COM3 lines are at +1V, the primary voltage of phase 3. As another example, during the subsequent phase (phase 4), the common lines COM0, COM2, and COM3 are at +2V, the primary voltage of phase 4.

Thus, during any phase shown, three of the four common lines are at the same potential (primary voltage), which for the illustrated example is +1V or + 2V. Note that typically for the example shown, during the even phases the main voltage is +2V, while during the odd phases the main voltage is + 1V.

Furthermore, for most, but not all, of the transitions shown, a common line that does not have a primary voltage at a given phase will cross the primary voltage at the next phase transition. For example, during phase 0, which has a dominant voltage of +2V, COM0 is at 0V. During the next phase transition, COM0 crosses the +2V level because it transitions to + 3V. As another example, during phase 2, the primary voltage is + 2V. During that phase, COM1 has a 0V level. During the subsequent phase transition, COM1 transitions from 0V to 3V across the +2V level.

Thus, during each phase, three of these common lines are at the primary voltage, and during some transitions of subsequent phase transitions, the fourth common line transitions across that primary voltage. Using this experience, in some embodiments, segment resets may be performed by coupling the common and segment lines to the primary voltage of a given phase. Alternatively, in some embodiments, during a given phase, segment resets may be performed by coupling the common and segment lines to the primary voltage of the subsequent phase.

Segment reset by coupling the common and segment lines to the main voltage does not increase or significantly increase the parasitic losses associated with the segment line, as most of the parasitic capacitors will be charged to the main voltage, or will switch to or pass through the main voltage during subsequent phases.

In a similar manner, resetting the segment by coupling the common line to the same node as the segment line but not driving the same node to a particular bias voltage (e.g., allowing the node to float) can also reduce power loss due to parasitic effects. In summary, the disclosed segment reset technique provides a way to reduce power dissipation or reduce battery drain in portable applications.

As noted, the controller 15 controls various operations associated with segment resetting. The controller 15 may be implemented in various ways. Fig. 9 shows a block diagram of the controller 15 according to an exemplary embodiment.

Specifically, controller 15 includes bias voltage generator 80, charge pump 85, phase generator 90, switch controller 100, segment enable circuit 105, host interface circuit 110, common line switch 115, and segment line switch 120. generally, controller 15 may operate from a given supply voltage (e.g., a battery voltage)_LCD) Which in the example described in connection with fig. 8 is + 3V. The charge pump 85 provides its output voltage to the bias generator 80.

The bias generator 80 uses the output voltage of the charge pump 85 to provide a set of bias voltages 95. In an exemplary embodiment corresponding to the waveforms in fig. 8, bias voltage 95 may include 0V (ground potential), +1V, +2V, and +3V, although other voltage levels and/or numbers may be used as understood by one of ordinary skill in the art.

Referring back to FIG. 9, the host interface circuitry 110 provides a mechanism for communicating with a host or controller (not shown). the host can control various operations of the controller 15 by providing information specifying L which of the CD segments should be switched on or off to indicate the information needed, if desired, the host interface circuitry 110 can provide information, such as data or status signals, from the controller 15 to the host.

The host may have various forms such as a processor, a microcontroller, a Central Processing Unit (CPU), and the like, as desired. In some embodiments, the host may be internal to the controller 15. For example, in some embodiments, the controller 15 (including the host) may be integrated in an Integrated Circuit (IC), a semiconductor die, or the like, as desired.

Segment enable circuit 105 holds information, for example in the form of register bits, which the host writes to specify the requested state of L CD segments (e.g., ON or OFF) to produce the desired display segment enable circuit 105 provides control signals to switch controller 100 corresponding to the desired state of L CD segments.

Phase generator 90 generates timing signals corresponding to the different switching phases used by controller 15. For example, for a controller driving four common lines, as discussed above, there are eight phases 0 to 7. Generally, in the exemplary embodiment, as described above, phase generator 90 provides a control signal to switch controller 100 that causes a segment reset to be performed. The duration of time for which the segment reset is performed (the period of time for which the segment reset between phases is performed) is typically a fraction of the duration of each phase and may be adjustable as desired in some embodiments.

Switch controller 100 uses the control signals from segment enable circuit 105 and the control signals from phase generator 90 to effect appropriate switching (described below) during the appropriate phase of operation to provide the appropriate bias voltages to the respective common and segment lines to ultimately cause L CD to produce the desired display.

As noted above, the controller 15 includes a common line switch 115 and a segmented line switch 120. Under the control of the switch controller 100, the common line switch 115 selectively couples the common line (e.g., COM0, COM1.. COM3) to a desired or appropriate bias voltage (e.g., 0V, +1V, +2V, or +3V in the illustrated exemplary embodiment). Further, under the control of switch controller 100, segmented line switch 120 selectively couples segmented lines (e.g., SEG0, SEG1 … SEG6) to a desired or appropriate bias voltage (e.g., 0V, +1V, +2V, or +3V in the illustrated exemplary embodiment). In the exemplary embodiment shown in fig. 9, one or more lines coupled to bias voltage 95 may function as node 70 shown in fig. 7.

For example, assuming equal probability random data provided to a L CD/L CD controller, power consumption may be reduced by 37.5% using these techniques.

More specifically, the waveform of the common line is independent of the data, i.e., the voltage applied to the common line of L CD is not dependent on the data requested to be displayed on L CD.

In other words, the nature of the waveform applied to the segment line (i.e., the voltage driving the segment line) depends on the data requested to be displayed on L CD.

More specifically, exemplary embodiments of the proposed technique change the reset or switching of a segment line based on data provided to or driving the segment line. Thus, the segment line is reset or held floating or allowed to float or float between transitions depending on the value of the data driving the segment line.

L the transition of the CD waveform generally requires a short period of time FIG. 10 illustrates this time period for an exemplary L CD waveform 150 the waveform 150 transitions from a voltage V1 during a L CD operational phase n to a voltage V2 during a L CD operational phase n +1, where n represents an integer.

Assume L CD common and segment lines exhibit some capacitance, as described aboveInstead, waveform 150 makes no instantaneous transition from voltage V1 to voltage V2, waveform 150 is during a relatively short period of time (labeled t in the figure) as compared to the duration of the L CD operating phase_rst(reset period)) to make a transition.

An L CD controller (e.g., the controller shown in FIG. 9) checks the data that drives the segment line As discussed above, several capacitors corresponding to the L CD element (and possibly parasitic elements) are coupled to the same L CD segment line for a given segment line, if both the segment that is energized during the current phase (whose common line has a voltage that is different from the voltage of other common lines) and the segment that is to be energized during the next phase have the same value (or both are on or both are off), the segment line remains floating or is allowed to float or is already floating during the reset period.

Conversely, if the segment excited during the current phase and the segment to be excited during the next phase both have opposite or different values (one on and the other off), the segment line is in the reset period (t)_rst) During which the segment line is reset by coupling it to the required voltage (typically Vrst) as described above. The common line is coupled to a desired voltage, typically Vrst.

Fig. 11 and 12 provide details of this technique fig. 11, consisting of fig. 11A and 11B, shows segment switching in the first scenario described above, i.e. the segment that is excited during the current phase and the segment that is to be excited during the next phase both have the same value fig. 11 more precisely shows how the voltage across the segment capacitance 36 is switched in response to a command or control signal from a controller (not shown) switches 39 and 42 are controlled switches and are responsive to an L CD controller (not shown) switches 39 and 42 switch the terminals of the capacitor 36 between the power supply 38 (in this case a 3V power supply) and ground potential.

Referring to fig. 11A, a switch 39 couples the left terminal of capacitor 36 to power source 38. Similarly, switch 42 couples the right terminal of capacitor 36 to ground 33. A power supply 38 provides charge to the capacitor 36. As a result, capacitor 36 eventually charges to supply voltage 3V with a time constant that depends on circuit component values and parasitic elements, as understood by those of ordinary skill in the art.

During the reset period discussed above, a controller (not shown) causes switch 42 to open and switch 39 to be coupled to the desired voltage (ground in the illustrated example) as described above, typically Vrst. (note that instead of being coupled to the desired voltage, switch 39 may be opened similar to switch 42 to float (or allow or maintain the float) the left terminal of capacitor 36).

As noted above, if the segment excited during the current phase and the segment to be excited during the next phase have opposite or different values, the segment line is in the reset period (t) using one or more of the techniques described above_rst) And during this period is coupled to voltage Vrst. Fig. 12 including fig. 12A and 12B shows details of the segment reset operation in this case.

More specifically, fig. 12 shows how the voltage across the segmented capacitor 30 is switched in response to a command or control signal from the controller 15 (not shown).

Switches

39 and 42 are controlled switches and are responsive to controller 15 (not shown).

Switches

39 and 42 switch the terminals of capacitor 30 having capacitance C between power supply 38 (shown in this example as a 3V supply) and ground potential.

Referring to fig. 12A, during one phase of operation, e.g., the current phase, controller 15 (not shown) causes switch 39 to couple the left terminal of capacitor 30 to power source 38. Similarly, the controller 15 (not shown) causes the switch 42 to couple the right terminal of the capacitor 30 to ground. As a result, the power supply 38 provides charge to the capacitor 30 with a time constant that depends on the circuit component values and parasitic elements, such that the capacitor eventually charges to the supply voltage (3V in this example).

Referring to fig. 12B, this figure illustrates how the

switches

39 and 42 are configured between the first phase (current phase) and the next phase. More specifically, switches 39 and 42 are controlled by controller 15 (not shown) to couple the terminals of capacitor 30 to a desired node, point or voltage (typically Vrst). In the example shown, switches 39 and 42 are controlled by controller 15 (not shown) to couple the terminals of capacitor 30 to ground potential, i.e., to ground 33. This operation does not draw any current or charge from the power supply 38 because any current from one terminal of the capacitor 30 flows through the node (ground 33 in this example) and reaches the other terminal of the capacitor 30.

During a reset period, the common line is coupled to a desired voltage or point or node as described above, typically Vrst. at 155, a segment line is selected to check the data of the currently activated segment and the data of the segments to be subsequently activated.

At 158, the data of the currently energized segment is examined to determine the data value (e.g., on, off). At 162, the data of the segment to be subsequently stimulated is examined to determine a data value (e.g., on, off). At 165, it is determined whether the data matches. In other words, it is determined whether the segment currently excited and the segment to be excited in the subsequent phase match (both are on or both are off).

If the data matches, then at 172, the segmented line remains floating or is allowed to float or is already floating during the reset period. Conversely, if the data does not match, then at 168, the segmented line is in a reset period t as described above_rstDuring which time it is coupled to the desired voltage, typically Vrst.

At 175, it is determined whether additional segmented lines remain to be processed. If so, control returns to 155 to process the additional segment line(s), as described above.

For example, in some embodiments, a Finite State Machine (FSM) may be used.

The data-dependent segment reset technique described above provides additional power savings compared to reset techniques that do not consider L CD data values in some embodiments, the data-dependent segment reset technique may provide a 30% to 35% reduction in power consumption compared to a data-independent segment reset technique.

In particular, if two consecutive segments in a segment line (e.g., a segment that is activated during a current phase and a segment that is to be activated during a next phase) are on or off, then the data-dependent segment reset or switching technique causes the L CD to use less power.

Conventional L CDs scan (drive) common lines in sequential order, for example, a conventional L CD having four common lines com1 through com4 scans these lines in the order com1, com2, com3, and com4 instead of sequentially or sequentially scanning common lines, an exemplary embodiment changes the scanning order based on L CD data values, as described in detail below, with reference to the L CD shown in fig. 14.

Specifically, L CD in FIG. 14 includes four common lines com1-com4 and ten segment lines S1-S10. in the example shown, the circles generally represent segments 177 at the intersections of the common lines and the respective segment lines, segments 180 are driven to be in an OFF state by the respective data values, and conversely, segments 183 are driven to be in an ON state by the respective data values.

As noted, a conventional L CD controller will scan common lines in

sequential order

1, 2, 3, 4 regardless of the segment data fig. 15 shows the common line scan order for such a L CD controller, thus, a conventional L CD controller will drive common line com1, then common lines com2, com3, and finally common line com 4.

Specifically, referring to FIG. 15, the switch-off-to-switch-on transition occurs at point 200, i.e., when the controller finishes scanning com1 and continues to drive com 2. similarly, the switch-on-to-switch-off transition occurs at point 203. another switch-off-to-switch-on transition occurs at point 206. As noted above, the switch-off-on or switch-on-off transition causes L CD power consumption to increase.

In contrast, the exemplary embodiment takes into account segmented data when selecting a common line scan order. FIG. 16 shows a common line scan order in accordance with an example embodiment.

As illustrated in fig. 16, the controller drives the common line com1, then drives the common line com3, the common line com2, and finally drives the common line com 4. The controller selects a common line scanning order based on the configuration of the segment data. Referring to the data configuration shown in fig. 14, the controller determines that the

common lines

1 and 3 correspond to the segment off configuration and the common lines 2 and 4 correspond to the segment on configuration. The controller then determines the order or sequence in which the common lines are driven or scanned in order to reduce or minimize the number of transitions between segment on and off states.

In view of the example configuration of the segment data in fig. 14, driving the common lines in the manner shown in fig. 16 causes one transition between the off and on states. Specifically, referring to fig. 16, the off-on transition occurs at point 210, i.e., when the controller finishes scanning com3 and continues to drive com 2.

The reordering of the scan of the common lines as shown in FIG. 16 results in fewer segmented line transitions, i.e., transitions between the OFF and ON states, compared to the conventional scanning method (see FIG. 15). As noted above, the reduction in the number of transitions between the OFF and ON states results in a reduction in power consumption of L CD.

Fig. 17 shows a flowchart of a data-dependent common line scanning method according to an exemplary embodiment. At 220, the data of the segmented lines is examined to select the scan order of the common lines.

At 223, the scan order of the common lines is selected to minimize or reduce the number of segment state transitions (off-on or on-off transitions). At 226, the common lines are scanned according to the selected scan order.

For example, in some embodiments, a Finite State Machine (FSM) may be used.

For example, although these figures show common lines and segment lines corresponding to an exemplary L CD, one of ordinary skill in the art will appreciate that many other numbers of common lines and segment lines may be used depending on the particular implementation.

Similarly, the number and levels of bias voltages may be selected and implemented in a variety of ways, whether for segment reset or otherwise for controlling L cd as desired as one of ordinary skill in the art will appreciate that the number of operating phases, supply voltage(s), etc. may also be selected depending on a number of factors such as the specifications of a given implementation.

Referring to the figures, those of ordinary skill in the art will note that the various blocks shown may primarily depict conceptual functions and signal flow. An actual circuit implementation may or may not contain separately identifiable hardware for the various functional blocks and may or may not use the specific circuitry shown. For example, the functionality of the various blocks may be combined into one circuit block, as desired. Furthermore, the functionality of a single block of several circuit blocks may be implemented as desired. The choice of circuit implementation depends on various factors, such as the specific design and performance specifications of a given implementation. Other modifications and alternative embodiments in addition to those described herein will be apparent to those of ordinary skill in the art. Accordingly, this description teaches those skilled in the art the manner of carrying out the disclosed concepts and should be construed as illustrative only.

The forms and embodiments shown and described are to be considered as illustrative embodiments. Various changes in the shape, size, and arrangement of parts may be made by those skilled in the art without departing from the scope of the concepts disclosed in the present document. For example, persons skilled in the art may substitute equivalent elements for the elements illustrated and described here. Moreover, those skilled in the art may use some of the features of the disclosed concepts independently of the use of other features, without departing from the scope of the disclosed concepts.

Claims

1. A display device comprising a multiplexed liquid crystal display (L) controller operating in at least first and second operating phases, the L CD controller driving a first plurality of signal lines to a first set of voltages during the first operating phase and a second set of voltages during the second operating phase, wherein the L CD controller selectively couples at least some of the first plurality of signal lines to a node in the L CD controller between the first and second operating phases based on data provided to the L CD controller.

2. The apparatus of claim 1, wherein the plurality of first signal lines comprises a plurality of segment lines.

3. The apparatus of claim 1, wherein the time period between the first operating phase and the second operating phase comprises a reset period.

4. The apparatus of claim 1, wherein the at least some of the plurality of first signal lines float between the first and second phases of operation if data of a segment that is energized during the first phase of operation matches data of a segment that is to be energized during the second phase of operation.

5. The apparatus of claim 4, wherein the at least some of the plurality of first signal lines are coupled to the node between the first and second phases of operation if data of a segment excited during the first phase of operation is different from data of a segment to be excited during the second phase of operation.

6. The apparatus of claim 1, wherein an order of scanning the plurality of second signal lines is selected according to the data provided to the L CD controller.

7. The apparatus of claim 6, wherein the plurality of second signal lines comprises a plurality of common lines.

8. The apparatus of claim 6, wherein the order in which the plurality of second signal lines are scanned is selected based on whether data for segments that are activated during the first phase of operation differs from data for segments that are to be activated during the second phase of operation.

9. The apparatus of claim 1, wherein the L CD controller selectively couples the first plurality of signal lines to (a) ground potential, or (b) a primary voltage of a common plurality of lines of the first operating phase, or (c) a primary voltage of a segmented plurality of lines of the second operating phase.

10. A display device, comprising:

a multiplexed liquid crystal display (L CD), the L CD having at least first and second operating phases, and

a controller coupled to the L CD, wherein the controller is to selectively perform a segment reset between the first and second operational phases of the L CD based on data provided to the controller.

11. The apparatus of claim 10, wherein the controller performs segment reset by selectively coupling segment lines of the L CD to a voltage if data of segments energized during the first phase of operation is different than data of segments to be energized during the second phase of operation.

12. The apparatus of claim 11, wherein the controller levitates the plurality of segment lines of the L CD between the first and second phases of operation if data of a segment energized during the first phase of operation matches data of a segment to be energized during the second phase of operation.

13. The apparatus of claim 12, wherein an order in which the plurality of second signal lines of the L CD are scanned is selected based on the data provided to the controller.

14. The apparatus of claim 13, wherein the second plurality of signal lines of the L CD comprise common lines of the L CD.

15. The apparatus of claim 11, wherein the voltage comprises (a) a ground potential of the apparatus, (b) a bias voltage, (c) a majority voltage of a common line of the L CD, or (d) a majority voltage of a segment line of the L CD.

16. The apparatus of claim 10, wherein the controller performs segment reset by selectively coupling segment lines of the L CD to common lines of the L CD.

17. A method of operating a liquid crystal display (L CD), the method comprising:

operating the L CD in a first operating phase;

selectively performing a segment reset based on data provided to the L CD controller after operating the L CD in the first operating phase, and

after performing the selective segment reset, the L CD is operated in the second phase of operation.

18. The method of claim 17, wherein performing segment reset further comprises selectively coupling segment lines of the L CD to a voltage if data of segments energized during the first phase of operation is different than data of segments to be energized during the second phase of operation.

19. The method of claim 18, wherein the L CD controller hovers the plurality of segment lines of the L CD between the first and second phases of operation if data of segments energized during the first phase of operation matches data of segments to be energized during the second phase of operation.

20. The method of claim 19, further comprising selecting an order of scanning common lines of the L CD based on the data provided to the L CD controller.