CN105632387A - Display device - Google Patents

Abstract

The present invention provides a display device, which operates in multiple display periods, and includes multiple scan lines, multiple data lines, multiple sub-pixels, and clock signals. On the same scan line, each of the preset number of these sub-pixels belongs to a pixel group. For each pixel group, in each display period, the enabling states of the multiple clock signals have a specific number (X=2×C ^K ₂ ) of multiple combinations, where C represents two clock signals from the preset number of these clock signals, and K is a positive integer. The specific number of these combinations at least includes a first combination and a second combination following the first combination. The enabling state sequence of the clock signals of the second combination is opposite to the enabling state sequence of the clock signals of the first combination.

Description

display device

technical field

The invention relates to a display device, in particular to a display device which can compensate the kickback voltage effect caused by a clock signal.

Background technique

Generally speaking, because the low temperature poly-silicon (LTPS) display panel has a high electron ionization rate, the LTPS panel has the advantages of fast response speed, high brightness, high resolution, and low power consumption. In the driving method of the LTPS display panel, a method of time-division switching (also known as de-multiplexer (DEMUX)) can be adopted, thereby reducing the number of input and output pins of the source driver. For example, for an LTPS display panel with a high resolution (eg, 1080×RGB×120) using a 1:3 demultiplexing driving method, each control clock signal will have a load of 1080 switches. At this time, the power consumed is proportional to C×V ² ×F, where C represents the parasitic capacitance, which depends on the size of the switch (W×L); V represents the voltage swing of the control clock signal; F represents the control clock the frequency of the signal.

According to the current development trend of electronic devices, how to minimize power consumption is an important issue. For an electronic device using an LTPS display panel, the overall consumption of the electronic device can be further reduced by reducing the power consumption caused by the demultiplexing method. According to the above, the power consumption of the LTPS display panel can be reduced by reducing C, V, and/or F. In some current technologies, it is proposed to reduce the power consumption by reducing the frequency of the control clock signal of the demultiplexing driving method. However, when these methods are used, the kickback voltage effect caused by the switch will cause uneven color of the image on the LTPS display panel.

Contents of the invention

Therefore, the present invention proposes a display device, which uses a demultiplexing driving method, which can not only reduce the input and output pins of the source driver, but also make the color of the image uniform.

The present invention provides a display device, which operates in multiple display periods and includes multiple scan lines, multiple data lines, multiple sub-pixels, and multiple clock signals. The data lines and the scan lines are arranged alternately, and transmit a plurality of data signals. Each data signal has multiple color information. The pixel units are coupled to the scan lines and the data lines. Each sub-pixel corresponds to one of these color information. The clock signals are correspondingly coupled to the sub-pixels. On the same scanning line, each preset number of these sub-pixels belongs to a pixel group, and these sub-pixels of each pixel group respectively receive the data signals according to the enabled state of a plurality of clock signals having a preset number One. For two pixel groups coupled to the same data lines and respectively coupled to two adjacent scan lines, the two pixel groups sequentially receive one of the data through the corresponding data lines, and respectively belong to Two pixel groups and two sub-pixels receiving the corresponding image signals sequentially receive one of the color information. For each pixel group, during each display period, there are a specific number (X) of multiple combinations of the enabled states of these clock signals. The specific number is X=2× ^CK ₂ , and C represents the preset Two clock signals are taken among the number of these clock signals, and K is a positive integer. The specified number of combinations includes at least a first combination and a second combination following the first combination. The enable state sequence of the clock signals of the second combination is opposite to the enable state sequence of the clock signals of the first combination.

The present invention also provides a display device, which operates in multiple display periods and includes multiple scan lines, multiple data lines, multiple sub-pixels, and multiple clock signals. The data lines and the scan lines are arranged alternately, and transmit a plurality of data signals. Each data signal has multiple color information. The pixel units are coupled to the scan lines and the data lines. Each sub-pixel corresponds to one of these color information. The clock signals are correspondingly coupled to the sub-pixels. On the same scanning line, each preset number (K) of these sub-pixels belongs to a pixel group, and these sub-pixels of each pixel group respectively receive these clock signals according to the enabling states of a preset number of clock signals. One of the data signals. For two pixel groups coupled to the same data lines and respectively coupled to two adjacent scan lines, the two pixel groups sequentially receive one of the data through the corresponding data lines, and respectively belong to Two pixel groups and two sub-pixels receiving corresponding data signals sequentially receive one of these color information. For two pixel groups coupled to the same data lines and respectively coupled to two adjacent scan lines, in each display period, the number of times of kickback voltage effects caused by the corresponding clock signals same. For each pixel group, during each display period, the specific number of these combinations includes at least a first combination and a second combination following the first combination, and the order of enabling states of these clock signals of the second combination The order of enable states of these clock signals is opposite to the first combination.

In order to make the above-mentioned objects, features and advantages of the present invention more comprehensible, a preferred embodiment will be described in detail below together with the accompanying drawings.

Description of drawings

FIG. 1 shows a display device according to an embodiment of the present invention.

FIG. 2 shows a switch unit and a pixel group according to an embodiment of the invention.

FIG. 3 shows a circuit structure diagram of a switch unit according to an embodiment of the present invention.

FIGS. 4A-4F show combinations of enabled states of clock signals during a plurality of frames (also referred to as “frames”) in a display period according to an embodiment of the present invention.

FIG. 5 shows a switch unit and a pixel group according to another embodiment of the present invention.

FIG. 6 is a circuit diagram of a switch unit according to another embodiment of the present invention.

7A and 7B show combinations of enable states of clock signals in multiple frame periods of a display period according to another embodiment of the present invention.

【Symbol Description】

1 ~ display device;

10～display array;

11 ~ gate driver;

12 ~ source driver;

13 ~ switch circuit;

14 ~ clock generator;

30...32~ switch;

60, 61 ~ switch;

100～subpixels;

100_1, 1...100_1, 6, 100_2, 1...100_2, 6～subpixel;

130_1, 130_2, 130_3～switch unit;

CK1, CK2 ~ clock signal;

CKR, CKG, CKB ~ clock signal;

DL1...DLm～data line;

PG1, 1, PG1, 2, PG2, 1, PG2, 2～pixel group;

Timing of PSL1, PSL2~data signals;

S[1], S[2], S[3]～data signal;

SL1...SLn～scanning lines.

detailed description

In order to make the above-mentioned objects, features and advantages of the present invention more comprehensible, a preferred embodiment will be described in detail below together with the accompanying drawings.

FIG. 1 shows a display device according to an embodiment of the present invention. Referring to FIG. 1, a display device 1 operates in a plurality of consecutive display periods, and includes a display array 10, a gate driver 11, a source driver 12, a switch circuit 13, a clock generator 14, data lines DL1-DLm, and scan lines SL1～SLn. The scan lines SL1˜SLn are arranged sequentially, and each scan line extends along the horizontal direction. The data lines DL1˜DLn are arranged in sequence, and each data line extends along a vertical direction. The scan lines SL1˜SLn and the data lines DL1˜DLn are arranged alternately, and each group of interleaved scan lines and data lines corresponds to one sub-pixel. For example, the alternate scan line SL1 and data line DL1 correspond to the sub-pixel 100 . According to the arrangement relationship between the scan lines SL1 ˜SLn, the data lines DL1 ˜DLm, and corresponding sub-pixels, a plurality of sub-pixels 100 are arranged in a plurality of rows and a plurality of columns to form the display array 10 . The gate driver 11 is coupled to the scan lines SL1˜SLn, and drives the scan lines SL1˜SLn in sequence. The source driver 12 is coupled to the switch circuit 13 and transmits data signals to the switch circuit 13 . The switch circuit 13 is coupled to the data lines DL1˜DLm. The clock generator 14 generates a plurality of clock signals to the switch circuit 13 . The switch circuit 13 transmits the received data signal to the corresponding sub-pixel 100 through the data lines DL1 -DLm according to the enabled state of the clock signal. The switch circuit 13 has a plurality of switch units. The switch unit of the switch circuit 13 will be described below.

In the embodiment of the present invention, among the sub-pixels coupled to the same scan line, every preset number (K) of sub-pixels belongs to/divides into a pixel group. The operation of the switch circuit 13 of the present application will be described below by taking three sub-pixels (K=3) belonging to one pixel group as an example. Referring to FIG. 2, for the scan line SL1, the first three sub-pixels 100_1, 1, 100_1, 2, and 100_1, 3 belong to the pixel group PG1, 1; the next three sub-pixels 100_1, 4, 100_1, 5, and 100_1 , 6 belong to the pixel group PG1, 2; the other sub-pixels belong by analogy. For the scan line SL2, the first three sub-pixels 100_2,1, 100_2,2, and 100_2,3 belong to the pixel group PG2,1; the next three sub-pixels 100_2,4, 100_2,5, and 100_2,6 belong to Pixel group PG2, 2; the belonging of other sub-pixels can be deduced by analogy. In order to clearly illustrate the relationship between sub-pixels and pixel groups, FIG. 2 only shows the sub-pixels and pixel groups on the scan lines SL1 and SL2. The relationship between the sub-pixels and pixel groups on the other scan lines SL3 ˜ SLn is the same as that of the scan lines SL1 and SL2 , so it is omitted here. Referring to FIG. 2 , the pixel groups PG1,1 and PG2,1 are coupled to the same data lines DL1˜DL3, and the pixel groups PG1,2 and PG2,2 are coupled to the same data lines DL4˜DL6.

In the embodiment of the present invention, the number of switch units in the switch circuit 13 is determined according to the number of pixel groups on the same scanning line. In detail, the number of switch units in the switch circuit 13 is equal to the number of pixel groups on the same scanning line. In this way, pixel groups coupled to the same scan line are respectively coupled to different switch units, and two pixel groups coupled to two adjacent scan lines and the same data line are coupled to the same switch unit. For example, the pixel groups PG1, 1 and PG1, 2 coupled to the scan line SL1 are respectively coupled to different switch units 130_1 and 130_2, and the pixel groups PG2, 1 and PG2, 2 coupled to the scan line SL2 are respectively coupled to different switch units 130_1 and 130_2. The switch units 130_1 and 130_2. On the other hand, the pixel groups PG1, 1 and PG2, 1 are controlled by the same switch unit 130_1, and the pixel groups PG1, 2 and PG2, 2 are controlled by the same switch unit 130_2.

In the embodiment of FIG. 2 , the three sub-pixels in each pixel group respectively correspond to different information. For example, the three sub-pixels of each pixel group respectively correspond to red (R), green (G), and blue (B) information, and in each single pixel group, respectively correspond to red (R), green ( G), sub-pixels with blue (B) information are configured in a specific manner. As shown in Figure 2, in the pixel groups PG1,1, PG2,1, PG1,2, and PG2,2, the sub-pixels corresponding to red (R), green (G), and blue (B) information respectively are Configure sequentially.

The display array 10 is driven by a time-division switching (also known as de-multiplexer (DEMUX)) driving method. Therefore, the number of clock signals generated by the clock generator 14 is based on the number of sub-pixels in each pixel group. (K) to decide. In the embodiment of FIG. 1, the number of clock signals generated by the clock generator 14 is determined by being equal to the number of sub-pixels in each pixel group, that is, the clock generator 14 generates three clock signals CKR, CKG, and CKB (K= 3), to control each switch unit. FIG. 3 shows the circuit structure of each switch unit. Referring to FIG. 3 , each switch unit includes three switches 30 , 31 , and 32 to implement a 1:3 demultiplexing driving method. Gates of the switches 30, 31, and 32 receive clock signals CKR, CKG, and CKB, respectively. The drains of the switches 30 , 31 , and 32 are coupled to the source driver 12 . The sources of the switches 30 , 31 , and 32 are respectively coupled to corresponding data lines. For example, for the switches 30 , 31 , and 32 of the switch unit 130_1 , their gates receive the clock signals CKR, CKG, and CKB respectively, and their drains are coupled to the source driver 12 to receive the data signal S[1] , and their sources are respectively coupled to the data lines DL1-DL3. The other switch units have the same structure as the switch unit 130_1 , so the related description is omitted here. When the clock signal is in an enabled state, its corresponding switch is turned on, so as to transmit the corresponding color information in the data signal to the corresponding data line. For example, for the switch unit 130_1, when the clock signal CKR is in the enabled state, the switch 30 is turned on to transmit the corresponding red information in the data signal S[1] to the data line DL1; when the clock signal CKG is in the In the enabled state, the switch 31 is turned on to transmit the corresponding green information in the data signal S[1] to the data line DL2; when the clock signal CKB is in the enabled state, the switch 32 is turned on to transfer the data signal S[ 1] The corresponding blue information is sent to the data line DL3. The operations of the other switch units and the relationship between the clock signal and the color information are the same as the switch unit 130_1.

The display device 1 of the present invention operates in a plurality of display periods. In one embodiment, however, each display period includes a plurality of frame periods ("picture frames"), and the number of frame periods within each display period depends on the synchronization of the clock signal for a pixel group during the display period. The number of combinations (X) of performance states. In another embodiment, for each pixel group, in each display period, there are 2× ^CK ₂ combinations of clock signal enabled states (X=2× ^CK ₂ ), where , C means to take two clock signals among the K clock signals. In the embodiment shown in FIGS. 2 and 3 , for each pixel group, in each display period, the number of enabled state combinations of the clock signals CKR, CKG, and CKB is equal to 6 (X=6). Therefore, each display period includes six frame periods, and for each pixel group, the six enable state combinations of the clock signals CKR, CKG, and CKB respectively appear in the six frame periods within a display period .

FIGS. 4A-4F respectively show six enable state combinations of the clock signals CKR, CKG, and CKB in six frame periods of a display period. The following will take the pixel groups PG1, 1 and PG2, 1, the clock signals CKR, CKG, and CKB, and the corresponding color information as examples to illustrate the six enable state combinations of the clock signals in a display period. In FIG. 4A-FIG. 4F, PSL1 represents the timing when the pixel group PG1, 1 receives the data signal S[1]. In 1], red, green, and blue information are transmitted to the sub-pixels 100_1, 1, 100_1, 2, and 100_1, 3 through the data lines DL1, DL2, and DL3, respectively. In FIG. 4A-FIG. 4F, PSL2 represents the timing when the pixel group PG2, 1 receives the data signal S[1]. In 1], red, green, and blue information are transmitted to the sub-pixels 100_2,1, 100_2,2, and 100_2,3 through the data lines DL1, DL2, and DL3, respectively.

Referring to FIG. 4A, in the first frame period of a display period, during the enable period of PSL1, the clock signals CKR, CKB, and CKG are sequentially in the enable state (for the pixel group PG1, 1, the first A combination of enabled states), and the enabled states of the clock signals CKR, CKB, and CKG do not overlap with each other. At this time, the red (R), blue (B), and green (G) information of the display signal S[ 1 ] are sequentially provided to the sub-pixels 100_1 , 1 , 100_1 , 3 , and 100_1 , 2 in time. Referring to FIG. 4B , in the second frame period of a display period, during the enable period of PSL1, the clock signals CKG, CKB, and CKR are sequentially in the enable state (for the pixel group PG1, 1, the first combination of the two enabled states), and the enabled states of the clock signals CKG, CKB, and CKR do not overlap with each other. At this time, the green (G), blue (B), and red (R) information of the display signal S[ 1 ] are sequentially provided to the sub-pixels 100_1 , 2 , 100_1 , 3 , and 100_1 , 1 in time. Similarly, referring to FIG. 4C-FIG. 4F, for the pixel groups PG1, 1, the third, fourth, fifth, and sixth frames (also referred to as "picture frames") within a display period are presented. Combinations of the third, fourth, fifth, and sixth enabled states.

Referring to FIG. 4A again, in the first frame period of a display period, during the enable period of PSL2, the clock signals CKG, CKB, and CKR are sequentially in the enable state (for the pixel group PG2, 1 The first enable state combination), and the enable states of the clock signals CKG, CKB, and CKR do not overlap with each other. At this time, the green, blue, and red information of the display signal S[1] are sequentially provided to the sub-pixels 100_2,2, 100_2,3, and 100_2,1 in time. Referring to FIG. 4B, in the second frame period of a display period, during the enable period of PSL2, the clock signals CKR, CKB, and CKG are sequentially in the enable state (for the pixel group PG2, the first combination of the two enabled states), and the enabled states of the clock signals CKR, CKB, and CKG do not overlap with each other. At this time, the red, blue, and green information of the display signal S[1] are sequentially provided to the sub-pixels 100_2,1, 100_2,3, and 100_2,2 in time. Similarly, referring to FIG. 4C to FIG. 4F , for pixel groups PG2 and 1, the third, fourth, fifth, and sixth frame periods of the third, fourth, fifth, and six frame periods within a display period respectively are shown. Enabled state combination.

According to FIG. 4A-FIG. 4F, it can be known that, for the pixel group PG1, 1, in a display period, the state of the combination of the enable state of the clock signal in the second frame period (enable sequence CKG->CLB-> CKR) is opposite to the state of the enable state combination of the clock signal in the first frame period (enabling sequence CKR->CLB->CKG); the state of the enable state combination of the clock signal in the fourth frame period (enable The sequence CKB->CLG->CKR) is opposite to the state of the enable state combination of the clock signal during the third frame period (enabling sequence CKR->CLG->CKB); the enable state of the clock signal during the sixth frame period The combination state (enabling sequence CKB->CLR->CKG) is opposite to the combination state (enabling sequence CKG->CLR->CKB) of the clock signals in the fifth frame period. Similarly, for the pixel group PG2, 1, in a display period, the states of the enable state combinations of the clock signals in the first and second frame periods are opposite to each other; the enable state of the clock signals in the third and four frame periods The states of the combination of states are opposite to each other; the states of the combination of enabled states of the clock signal in the fifth and sixth frame periods are opposite to each other.

According to FIG. 4A , in the first frame period of a display period, the pixel groups PG1 , 1 and PG2 , 1 sequentially receive the data signal S[ 1 ] in timing. In other words, the red, blue, and green information of the data signal S[1] is sequentially received by the sub-pixels 100_1,1, 100_1,3, and 100_1,2 of the pixel group PG1,1, and then the pixel The sub-pixels 100_2,2, 100_2,3, and 100_2,1 of the group PG2,1 sequentially receive the green, blue, and red information of the data signal S[1]. In this way, it can be seen that the state of the clock signal CKG corresponding to the green information is maintained from the enabling period of PSL1 to the enabling period of PSL2 . That is, during the enable period of PSL1 , the clock signals CKR and CKB each have a falling edge, while the clock signal CKG does not have a falling edge.

Similarly, as shown in FIG. 4B , in the second frame period of a display period, the state of the clock signal CKR corresponding to the red information is maintained from the enable period of PSL1 to the enable period of PSL2 . That is, during the enable period of PSL1 , the clock signals CKG and CKB each have a falling edge, while the clock signal CKR does not have a falling edge. During the third, fourth, fifth, and sixth frame periods of a display period, the states of the falling edges of the clock signals CKR, CKG, and CKB are analogous, as shown in FIGS. 4C-4F .

According to the above-mentioned embodiment, during the six pixel periods in a display period, the six enabled states of the clock signals CKR, CKG, and CKB are combined so that the red information transmitted to the pixel group PG1, 1 is subjected to the clock signal CKR The number of kickback voltage effects caused is the same as the number of times the red information transmitted to the pixel group PG2, 1 is subjected to the kickback voltage effect caused by the clock signal CKR. For the pixel groups PG1,1 and PG2,1, the green and blue information are subjected to the scanning signal as well. In this way, during a display period, the display device 1 compensates for the voltage difference caused by the aforementioned kickback voltage effect through the combination of six enabled states of the clock signal. The performance state can reduce the degree difference of the same color in different pixel groups, so that the image of the display device 1 is more uniform.

In another embodiment, two sub-pixels (K=2) belong to one pixel group as an example to illustrate the operation of the switch circuit 13 of the present application. Referring to FIG. 5 , for the scan line SL1, the first two sub-pixels 100_1,1 and 100_1,2 belong to the pixel group PG1,1; the next two sub-pixels 100_1,3 and 100_1,4 belong to the pixel group PG1,2; The attribution of other sub-pixels can be deduced by analogy. For the scan line SL2, the first two sub-pixels 100_2,1 and 100_2,2 belong to the pixel group PG2,1; the next two sub-pixels 100_2,3 and 100_2,4 belong to the pixel group PG2,2; the other sub-pixels attribution and so on. In order to clearly illustrate the relationship between sub-pixels and pixel groups, FIG. 5 only shows the sub-pixels and pixel groups on the scan lines SL1 and SL2. The relationship between the sub-pixels and pixel groups on the other scan lines SL3 ˜ SLn is the same as that of the scan lines SL1 and SL2 , so it is omitted here. Referring to FIG. 5 , pixel groups PG1, 1 and PG2, 1 are coupled to the same data lines DL1 and DL2, and pixel groups PG1, 2 and PG2, 2 are coupled to the same data lines DL3 and DL4.

Like the embodiment in FIG. 2 , in the embodiment of the present invention, the number of switch units in the switch circuit 13 is equal to the number of pixel groups on the same scanning line. In this way, pixel groups coupled to the same scan line are respectively coupled to different switch units, and two pixel groups coupled to two adjacent scan lines and the same data line are coupled to the same switch unit. The configuration between the pixel group and the switch unit is the same as the embodiment shown in FIG. 2 , and the description is omitted here.

In the embodiment of FIG. 5 , the two sub-pixels in each pixel group respectively correspond to different information. As shown in FIG. 5 , in the pixel groups PG1 , 1 and PG2 , 1 , sub-pixels respectively corresponding to red (R), green (G), and blue (B) information are arranged sequentially. In the pixel groups PG1, 2 and PG2, 2, sub-pixels respectively corresponding to blue (B) and red (R) information are arranged sequentially. From the perspective of all pixel groups on a scanning line, sub-pixels corresponding to red (R), green (G), and blue (B) information are arranged sequentially and repeatedly.

Since the display array 10 is driven by time-division switching (also called de-multiplexer (DEMUX)), the number of clock signals generated by the clock generator 14 is based on the number of sub-pixels in each pixel group. Quantity (K) to decide. In the embodiment of FIG. 5 , the number of clock signals generated by the clock generator 14 is determined equal to the number of sub-pixels in each pixel group, that is, the clock generator 14 generates three clock signals CK1 and CK2 (K=2), to control each switch unit. FIG. 6 shows the circuit structure of each switch unit. Referring to FIG. 6 , each switch unit includes two switches 60 and 61 to implement a 1:2 demultiplexing driving method. . The gates of the switches 60 and 61 receive the clock signals CK1 and CK2 respectively. The drains of the switches 60 and 61 are coupled to the source driver 12 . The sources of the switches 60 and 61 are respectively coupled to corresponding data lines. For example, for the switches 60 and 61 of the switch unit 130_1 , their gates receive the clock signals CK1 and CK2 respectively, their drains are coupled to the source driver 12 to receive the data signal S[1], and their sources respectively Coupled with data lines DL1 and DL2. The other switch units have the same structure as the switch unit 130_1 , so the related description is omitted here. When the clock signal is in an enabled state, its corresponding switch is turned on, so as to transmit the corresponding color information in the data signal to the corresponding data line. For example, for the switch unit 130_1, when the clock signal CK1 is in the enable state, the switch 60 is turned on to transmit the corresponding red information in the data signal S[1] to the data line DL1; when the clock signal CK2 is in the In the enabled state, the switch 61 is turned on to transmit the corresponding green information in the data signal S[1] to the data line DL2. For the switch unit 130_2, when the clock signal CK1 is in the enabled state, the switch 60 is turned on to transmit the corresponding blue information in the data signal S[2] to the data line DL3; when the clock signal CK2 is in the enabled state , the switch 61 is turned on to transmit the corresponding red information in the data signal S[2] to the data line DL4. For the switch unit 130_3, when the clock signal CK1 is in the enabled state, the switch 60 is turned on to transmit the corresponding green information in the data signal S[3] to the data line DL5; when the clock signal CK2 is in the enabled state , the switch 61 is turned on to transmit the corresponding blue information in the data signal S[3] to the data line DL6. In this embodiment, the operations of other switch units and the relationship between the clock signal and the color information are the same as the switch units 130_1˜130_3.

In this embodiment, for each pixel group, in each display period, the combination number of enabled states of the clock signals CK1 and CK2 is equal to 2 (X=2× ^CK ₂ , wherein K=2). Therefore, each display period includes two frame periods, and for each pixel group, the two enable state combinations of the clock signals CK1 and CK2 respectively appear in two frame periods within a display period.

FIG. 7A and FIG. 7B respectively show two enable state combinations of the clock signals CK1 and CK2 in two frame periods of a display period. The following will take the pixel groups PG1, 1 and PG2, 1, the clock signals CK1 and CK2, and the corresponding color information as examples to illustrate the two enable state combinations of the clock signals in a display period. In FIG. 7A and FIG. 7B , PSL1 represents the time sequence when the pixel group PG1, 1 receives the data signal S[1], that is, during the enabling period of PSL1, the switches 60 and 61 of the switch unit 103_1 are turned on to turn on the data signal S[ In 1], the red and green information are transmitted to the sub-pixels 100_1, 1 and 100_1, 2 through the data lines DL1 and DL2, respectively. In FIG. 7A and FIG. 7B , PSL2 represents the timing when the pixel group PG2, 1 receives the data signal S[1]. That is, during the enabling period of PSL2, the switches 60 and 61 of the switch unit 103_1 are turned on to turn on the data signal S[ In 1], the red and green information are transmitted to the sub-pixels 100_2,1 and 100_2,2 through the data lines DL1 and DL2 respectively.

Referring to FIG. 7A, in the first frame period of a display period, during the enable period of PSL1, the clock signals CK1 and CK2 are sequentially in the enable state (for the pixel group PG1, 1, the first enable combination of enabled states), and the enabled states of the clock signals CK1 and CK2 do not overlap with each other. At this time, the red (R) and green (G) information of the display signal S[ 1 ] are sequentially provided to the sub-pixels 100_1 , 1 and 100_1 , 2 in time. Referring to FIG. 7B, in the second frame period of a display period, during the enable period of PSL1, the clock signals CK2 and CK1 are sequentially in the enable state (for the pixel group PG1, 1, the second enable combination of enabled states), and the enabled states of the clock signals CK1 and CK2 do not overlap with each other. At this time, the green (G) and red (R) information of the display signal S[ 1 ] are sequentially provided to the sub-pixels 100_1 , 2 and 100_1 , 1 respectively in time.

Referring to FIG. 7A again, in the first frame period of a display period, during the enable period of PSL2, the clock signals CK2 and CK1 are sequentially in the enable state (for the pixel group PG2, 1, the first combination of enabled states), and the enabled states of the clock signals CK1 and CK2 do not overlap with each other. At this moment, the green and red information of the display signal S[ 1 ] are respectively provided to the sub-pixels 100_2 , 2 and 100_2 , 1 sequentially in time. Referring to FIG. 7B, in the second frame period of a display period, during the enable period of PSL2, the clock signals CK1 and CK2 are sequentially in the enable state (for the pixel group PG2, 1, the second enable combination of enabled states), and the enabled states of the clock signals CK1 and CK2 do not overlap with each other. At this time, the red and green information of the display signal S[ 1 ] are respectively provided to the sub-pixels 100_2 , 1 and 100_2 , 2 sequentially in time.

According to FIG. 7A and FIG. 7B , for the pixel group PG1, 1, in a display period, the state of the combination of enabled states of the clock signal in the second frame period (enabled sequence CK2 -> CL1) is opposite The state of the enable state combination of the clock signal in the first frame period (enable sequence CK1->CL2). Similarly, for the pixel group PG2, 1, in a display period, the combinations of enabled states of the clock signals in the first and second frame periods are opposite to each other.

According to FIG. 7A , in the first frame period of a display period, the pixel groups PG1 , 1 and PG2 , 1 sequentially receive the data signal S[ 1 ] in timing. In other words, firstly, the sub-pixels 100_1, 1 and 100_1, 2 of the pixel group PG1, 1 sequentially receive the red and green information of the data signal S[1], and then the sub-pixels 100_2, 100_2, of the pixel group PG2, 1 2 and 100_2,1 sequentially receive the green and red information of the data signal S[1]. From this, it can be known that the state of the clock signal CK2 is maintained from the enabling period of PSL1 to the enabling period of PSL2. That is, during the enable period of PSL1 , the clock signal CK1 has a falling edge, but the clock signal CK2 does not have a falling edge.

Similarly, as can be seen from FIG. 7B , in the second frame period of a display period, the state of the clock signal CK1 is maintained from the enable period of PSL1 to the enable period of PSL2 . That is, during the enable period of PSL1 , the clock signal CK2 has a falling edge, but the clock signal CK1 does not have a falling edge.

According to the above-mentioned embodiment, during two pixel periods in a display period, the combination of the two enabled states of the clock signals CK1 and CK2 causes the green information transmitted to the pixel group PG1,1 to be affected by the clock signal CK2 The number of times of the kickback voltage effect is the same as the number of times of the kickback voltage effect caused by the clock signal CK2 for the green information transmitted to the pixel group PG2,1. For the pixel groups PG1, 1 and PG2, 1, the red information receives the scanning signal as well. In this way, during a display period, the display device 1 compensates the voltage difference caused by the aforementioned kickback voltage effect through the combination of the two enabled states of the clock signal. The performance state can reduce the degree difference of the same color in different pixel groups, so that the image of the display device 1 is more uniform.

Although the present invention is disclosed above with preferred embodiments, it is not intended to limit the scope of the present invention. Those skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be subject to the scope defined by the appended claims.

Claims (10)

1. A display device, operating during a plurality of display periods, comprising: multiple scan lines; A plurality of data lines, arranged alternately with the scanning lines, and transmitting a plurality of data signals, wherein each data signal has a plurality of color information; and A plurality of sub-pixels, coupled to the scan line and the data line, each of the sub-pixels corresponds to one of the color information; A plurality of clock signals are correspondingly coupled to the sub-pixels; Wherein, on the same scanning line, each preset number of sub-pixels belongs to a pixel group, and the sub-pixels of each pixel group are respectively enabled according to the preset number of clock signals. state to receive one of said data signals; Wherein, for the two pixel groups coupled to the same data line and respectively coupled to two adjacent scan lines, the two pixel groups sequentially pass through the corresponding data lines receiving one of the data, and receiving one of the color information for the two sub-pixels that respectively belong to the two pixel groups and receive the corresponding data signal sequentially in sequence; Wherein, for each pixel group, during each display period, there are a certain number of multiple combinations of the enabling states of the clock signal, the specific number is 2×C ^K ₂ , and C represents that in the preset Two of the clock signals are selected from the number of clock signals, K is a positive integer; and Wherein, the specific number of combinations includes at least a first combination and a second combination following the first combination, and the order of enabling states of the clock signals of the second combination is opposite to that of the first combination. The enable state sequence of the clock signal. 2. The display device according to claim 1, wherein each display period includes the specific number of frame times, and each frame time corresponds to one of the specific number of enabled states of the clock signal a combination. 3. The display device as claimed in claim 1, wherein the preset number is greater than or equal to two. 4. The display device as claimed in claim 1, wherein in each pixel group, the sub-pixels receive different color information in the corresponding data signal. 5. The display device according to claim 1, further comprising: The switch circuit is coupled to the data line and includes: a plurality of switches, respectively receiving the data signals, and respectively coupling the data lines; Wherein, for each pixel group, the corresponding switches are respectively controlled by the preset number of the clock signals, so as to transmit the corresponding data signals to the corresponding data lines. 6. A display device, operating during a plurality of display periods, comprising: multiple scan lines; A plurality of data lines, arranged alternately with the scanning lines, and transmitting a plurality of data signals, wherein each data signal has a plurality of color information; and A plurality of sub-pixels, coupled to the scan line and the data line, each of the sub-pixels corresponds to one of the color information; A plurality of clock signals are correspondingly coupled to the sub-pixels; Wherein, on the same scanning line, each preset number of sub-pixels belongs to a pixel group, and the sub-pixels of each pixel group are respectively enabled according to the preset number of clock signals. state to receive one of said data signals; Wherein, for the two pixel groups coupled to the same data line and respectively coupled to two adjacent scan lines, the two pixel groups sequentially pass through the corresponding data lines receiving one of the data, and receiving one of the color information for the two sub-pixels that respectively belong to the two pixel groups and receive the corresponding data signal sequentially in sequence; Wherein, for the two sub-pixels coupled to the same data line and respectively coupled to two adjacent scan lines, in each display period, they are controlled by the corresponding clock signal. The number of kickback voltage effects induced is the same; and Wherein, for each pixel group, during each display period, the specific number of combinations includes at least a first combination and a second combination subsequent to the first combination, and the second combination of the The enable state sequence of the clock signals is opposite to the enable state sequence of the clock signals of the first combination. 7. The display device according to claim 6, wherein, in the two pixel groups corresponding to the same data line and respectively corresponding to two adjacent scanning lines, the pixels corresponding to the same color information Each of the sub-pixels is arranged at a specific position in the corresponding pixel group for the same number of times in each display period. 8. The display device as claimed in claim 6, wherein the preset number is greater than or equal to two. 9. The display device as claimed in claim 6, wherein in each pixel group, the sub-pixels receive different color information in the corresponding data signal. 10. The display device of claim 6, further comprising: The switch circuit is coupled to the data line and includes: a plurality of switches, respectively receiving the data signals, and respectively coupling the data lines; Wherein, for each pixel group, the corresponding switches are respectively controlled by the preset number of the clock signals, so as to transmit the corresponding data signals to the corresponding data lines.