CN105632387A - Display device - Google Patents

Abstract

The invention provides a display device which is operated in a plurality of display periods, and includes a plurality of scanning lines, a plurality of data lines, a plurality of sub pixels and clock signals. On a same scanning line, each preset number of sub pixels belong to a pixel group. For each pixel group, in each display period, the enabling state of the plurality of clock signals has a specific number (X=2*C<2><K>) of combinations, C represents taking two clock signals from the preset number of clock signals, and K is a positive integer. The specific number of combinations at least includes a first combination and a second combination following the first combination. The enabling state sequence of the clock signals of the second combination is opposite to that of the clock signals of the first combination.

Description

Display device

Technical field

The present invention relates to a kind of display device, particularly to a kind of display device, it can compensate for the Kickback voltage effect caused by clock signal.

Background technology

Generally, due to low temperature polycrystalline silicon (lowtemperaturepoly-silicon, LTPS) display floater has high electronics ionization rate, therefore LTPS panel has the advantages such as fast response speed, high brightness, high-res and low power consumption. In the driving method of LTPS display floater, the method that can adopt time-division switching (be also called and solve multiplexing (de-multiplexer, DEMUX)), thereby can reduce the import and export pin of source electrode driver. For example, for the solution multiplexing's driving method adopting 1:3 and for having the LTPS display floater of high-res (such as 1080 �� RGB �� 120), each control clock signal will have the loads of 1080 switches. Now, the power proportional consumed is in C �� V²�� F, wherein, C represents parasitic capacitance, and it depends on the size (W �� L) of switch; V represents the voltage swing controlling clock signal; F then represents the frequency controlling clock signal.

How development trend according to present electronic installation, minimize that to consume power be important subject under discussion. For the electronic installation using LTPS display floater, by reducing the power consumption solved caused by multiplexing's method, the total consumption of electronic installation can be reduced further. According to above-mentioned, the power consumption of LTPS display floater can be reduced by minimizing C, V and/or F. In some current technology, it is proposed that reduce power consumption by reducing the control clock signal frequency solving multiplexing's driving method. But, when adopting these means, the Kickback voltage effect caused by switch but will cause the uneven of LTPS display floater epigraph color.

Summary of the invention

Therefore, the present invention proposes a kind of display device, and it adopts solution multiplexing's driving method, can not only reduce the import and export pin of source electrode driver, and can make the color homogenization of image.

The present invention provides a kind of display device, and operation is during multiple displays, including multiple scanning lines, multiple data wire, multiple sub-pixel and multiple clock signal. These data wires are crisscross arranged with these scanning lines, and transmit multiple data signal. Each data signal has multiple colouring information. These pixel cells, couple these scanning lines and these data wires. In each sub-pixel these colouring informations corresponding one. These clock signals correspondence respectively couples these sub-pixels. In same scan line, these sub-pixels of each predetermined number belong to a pixel groups, and these sub-pixels of each pixel groups receive in these data signals one according to the enabled status of multiple clock signals with predetermined number respectively. For couple these identical data wires and be respectively coupled to adjacent two scanning line two pixel groups for, two pixel groups receive in these data by these corresponding data wires in order, and are belonging respectively to two pixel groups and two sub-pixels receiving these corresponding image signals that continue in sequential receive in these colouring informations one. For each pixel groups, during each display, the enabled status of these clock signals has multiple combinations of a specific quantity (X), and this specific quantity is X=2 �� C^K ₂, C represents and takes two clock signals in these clock signals of predetermined number, and K is positive integer. These combinations certain amount of at least include one first combination and are connected in one second combination of this first combination. The enabled status order of these clock signals of the second combination is in contrast to the enabled status order of these clock signals of the first combination.

The present invention also provides for a kind of display device, and operation is during multiple displays, including multiple scanning lines, multiple data wire, multiple sub-pixel and multiple clock signal. These data wires are crisscross arranged with these scanning lines, and transmit multiple data signal. Each data signal has multiple colouring information. These pixel cells couple these scanning lines and these data wires. In each sub-pixel these colouring informations corresponding one. These clock signals correspondence respectively couples these sub-pixels. In same scan line, these sub-pixels of each predetermined number (K) belong to a pixel groups, and these sub-pixels of each pixel groups receive in these data signals one according to the enabled status of multiple clock signals with predetermined number respectively. For couple these identical data wires and be respectively coupled to adjacent two scanning line two pixel groups for, two pixel groups receive in these data by these corresponding data wires in order, and are belonging respectively to two pixel groups and two sub-pixels receiving corresponding data signal that continue in sequential receive and have in these colouring informations one. For coupling these identical data wires and being respectively coupled to two pixel groups of adjacent two bar scanning line, in during each display, the number of times of the Kickback voltage effect caused by such clock signal being subject to correspondence is identical. For each pixel groups, during each display, these combinations certain amount of at least include one first combination and are connected in one second combination of the first combination, and the enabled status order of these clock signals of the second combination is in contrast to the enabled status order of these clock signals of the first combination.

For making the above-mentioned purpose of the present invention, feature and advantage to become apparent, a preferred embodiment cited below particularly, and coordinate accompanying drawing, it is described in detail below.

Accompanying drawing explanation

Fig. 1 represents display device according to an embodiment of the invention.

Fig. 2 represents switch element and pixel group according to an embodiment of the invention.

Fig. 3 represents switch element circuit framework figure according to an embodiment of the invention.

Fig. 4 A��Fig. 4 F represents according to one embodiment of the invention, in multiple frames (also referred to as " the picture frame ") period during one shows, and the enabled status combination of clock signal.

Fig. 5 represents switch element and pixel group according to another embodiment of the present invention.

Fig. 6 represents switch element circuit framework figure according to another embodiment of the present invention.

Fig. 7 A and Fig. 7 B represents according to another embodiment of the present invention, in during the multiple frames during shows, and the enabled status combination of clock signal.

[symbol description]

1��display device;

10��array of display;

11��gate drivers;

12��source electrode driver;

13��on-off circuit;

14��clock generator;

30 ... 32��switch;

60,61��switch;

100��sub-pixel;

100_1,1 ... 100_1,6,100_2,1 ... 100_2,6��sub-pixel;

130_1,130_2,130_3��switch element;

CK1, CK2��clock signal;

CKR, CKG, CKB��clock signal;

DL1 ... DLm��data wire;

PG1,1, PG1,2, PG2,1, PG2,2��pixel groups;

The sequential of PSL1, PSL2��data signal;

S [1], S [2], S [3]��data signal;

SL1 ... SLn��scanning line.

Detailed description of the invention

For making the above-mentioned purpose of the present invention, feature and advantage to become apparent, a preferred embodiment cited below particularly, and coordinate accompanying drawing, it is described in detail below.

Fig. 1 indicates that display device according to an embodiment of the invention. Consulting Fig. 1, display device 1 operates during multiple continuous print show, and includes array of display 10, gate drivers 11, source electrode driver 12, on-off circuit 13, clock generator 14, data wire DL1��DLm and scanning line SL1��SLn. Scanning line SL1��SLn sequentially configures, and every scan line extends along horizontal direction. Data wire DL1��DLn sequentially configures, and each data wire vertically extends. Scanning line SL1��SLn and data wire DL1��DLn is crisscross arranged, and a scanning line sub-pixel corresponding to data wire each group staggered. For example, staggered scanning line SL1 and data wire DL1 corresponding sub-pixel 100. Configuration relation according to scanning line SL1��SLn, data wire DL1��DLm and corresponding sub-pixel, multiple sub-pixels 100 are arranged on multiple row and multiple row, to form array of display 10. Gate drivers 11 couples scanning line SL1��SLn, and is sequentially driven scanning line SL1��SLn. Source electrode driver 12 couples on-off circuit 13, and transmits data signal to on-off circuit 13. On-off circuit 13 couples data wire DL1��DLm. Clock generator 14 produces multiple clock signal to on-off circuit 13. On-off circuit 13 is made to transmit the received data signal sub-pixel 100 to correspondence by data wire DL1��DLm according to the enabled status of clock signal. On-off circuit 13 has multiple switch element. Switch element about on-off circuit 13 will in description.

In embodiments of the present invention, in the sub-pixel coupling same scanning line, the sub-pixel of every predetermined number (K) belongs to/is divided into a pixel groups. Hereinafter will belong to a pixel groups to illustrate that the application on-off circuit 13 operates for three sub-pixels (K=3). Consult Fig. 2, for scanning line SL1, first three sub-pixel 100_1,1,100_1,2 and 100_1,3 belong to pixel groups PG1, and 1; Three the sub-pixel 100_1 continued, 4,100_1,5 and 100_1,6 belong to pixel groups PG1, and 2; The ownership of other sub-pixel is by that analogy. For scanning line SL2, first three sub-pixel 100_2,1,100_2,2 and 100_2,3 belong to pixel groups PG2, and 1; Three the sub-pixel 100_2 continued, 4,100_2,5 and 100_2,6 belong to pixel groups PG2, and 2; The ownership of other sub-pixel is by that analogy. In order to know the relation illustrated between sub-pixel and pixel groups, Fig. 2 only shows the sub-pixel on scanning line SL1 and SL2 and pixel groups. On other scanning line SL3��and SLn, the relation between sub-pixel and pixel groups is such as scanning line SL1 and SL2, therefore omits at this. Consulting Fig. 2, pixel groups PG1,1 and PG2,1 is coupled to identical data wire DL1��DL3 and pixel groups PG1, and 2 and PG2,2 are coupled to identical data wire DL4��DL6.

In embodiments of the present invention, the quantity of on-off circuit 13 breaker in middle unit is to determine according to the quantity of pixel groups on same scanning line. Specifically, the quantity of on-off circuit 13 breaker in middle unit scans the quantity of pixel groups on line equal to according at same. Consequently, it is possible to the pixel groups coupling same scanning line is respectively coupled to different switch elements, and couples adjacent two scanning lines and couple two pixel groups of identical data wire and be coupled to same switch element. For example, the pixel groups PG1 of scanning line SL1 is coupled, 1 and PG1,2 are respectively coupled to different switch element 130_1 and 130_2, couple the pixel groups PG2 of scanning line SL2, and 1 and PG2,2 are respectively coupled to different switch element 130_1 and 130_2. On the other hand, pixel groups PG1,1 and PG2,1 is all affected by same switch element 130_1 is controlled, and pixel groups PG1, and 2 and PG2,2 are all affected by same switch element 130_2 is controlled.

In the embodiment of fig. 2, the information that three sub-pixels in each pixel groups are corresponding different respectively. For example, three sub-pixels of each pixel groups are corresponding red (R), green (G) and blue (B) information respectively, and at each pixel Dan Zuzhong, the sub-pixel of corresponding red (R), green (G) and blue (B) information configures with specific pattern respectively. As in figure 2 it is shown, at pixel groups PG1,1, PG2,1, PG1,2 and PG2, in 2, the sub-pixel of corresponding red (R), green (G) and blue (B) information is sequentially to configure respectively.

The driving of array of display 10 is to adopt time-division switching (to be also called solution multiplexing (de-multiplexer, DEMUX) driving method), therefore, the quantity of clock signal produced by clock generator 14 determines according to the quantity (K) of sub-pixel in each pixel groups. In the embodiment in figure 1, the quantity of clock signal produced by clock generator 14 determines equal to the quantity of sub-pixel in each pixel groups, namely clock generator 14 produces three clock signal CKR, CKG and CKB (K=3), to control each switch element. Fig. 3 represents the circuit framework of each switch element. Consulting Fig. 3, each switch element includes three switches 30,31 and 32, to realize solution multiplexing's driving method of 1:3. The grid of switch 30,31 and 32 receives clock signal CKR, CKG and CKB respectively. The drain electrode of switch 30,31 and 32 couples source electrode driver 12. Switch 30,31 is respectively coupled to corresponding data wire with the source electrode of 32. For example, for the switch 30,31 and 32 of switch element 130_1, its grid receives clock signal CKR, CKG and CKB respectively, and its drain electrode couples source electrode driver 12 to receive data signal S [1], and its source electrode is respectively coupled to data wire DL1��DL3. Other switch element has the framework identical with switch element 130_1, therefore omits related description at this. When clock signal is in enabled status, the switch conduction of its correspondence, to be sent to colouring information corresponding in data signal the data wire of correspondence. For example, for switch element 130_1, when clock signal CKR is in enabled status, switch 30 conducting, to be sent to data wire DL1 red information corresponding in data signal S [1]; When clock signal CKG is in enabled status, switch 31 conducting, to be sent to data wire DL2 green information corresponding in data signal S [1]; When clock signal CKB is in enabled status, switch 32 conducting, to be sent to data wire DL3 blue information corresponding in data signal S [1]. Relation between operation and clock signal and the colouring information of other switch elements is such as switch element 130_1.

The display device 1 of the present invention operates in during multiple displays. And in one embodiment, include multiple frame frame (" picture frame ") period during each display, and during each display in quantity during frame depend in during this display the number of combinations (X) of enabled status of clock signal for a pixel groups. In another embodiment, for each pixel groups, in during each display, the combination one of the enabled status of clock signal has 2 �� C^K ₂Individual combination (X=2 �� C^K ₂), wherein, C represents and takes two clock signals in K clock signal. With the embodiment of the 2nd and 3 figure, for each pixel groups, in during each display, clock signal CKR, CKG and CKB enabled status number of combinations equal to 6 (X=6). Therefore, during including six frames during each display, and for each pixel groups, clock signal CKR, CKG and CKB the combination of six enabled status respectively during occurring in a display in six frames during in.

Fig. 4 A��Fig. 4 F is illustrated respectively in during six frames during a display, clock signal CKR, CKG and CKB the combination of six enabled status. Below will with pixel groups PG1,1 and PG2,1, the colouring information of clock signal CKR, CKG and CKB and correspondence be that example illustrates that six enabled status of the clock signal in during shows combine. In Fig. 4 A��Fig. 4 F, PSL1 represents pixel groups PG1,1 sequential receiving data signal S [1], namely during the enable of PSL1, switch 30��32 conducting of switch element 103_1, so that red in data signal S [1], green and blue information are sent to sub-pixel 100_1 respectively through data wire DL1, DL2 and DL3,1,100_1,2 and 100_1,3. In Fig. 4 A��Fig. 4 F, PSL2 represents pixel groups PG2,1 sequential receiving data signal S [1], namely during the enable of PSL1, switch 30��32 conducting of switch element 103_1, so that red in data signal S [1], green and blue information are sent to sub-pixel 100_2 respectively through data wire DL1, DL2 and DL3,1,100_2,2 and 100_2,3.

Consult Fig. 4 A, in during first frame in during shows, during the enable of PSL1, clock signal CKR, CKB and CKG are in enabled status in order (for pixel groups PG1, the first enabled status combination of 1), and the enabled status of clock signal CKR, CKB and CKG do not overlap each other. Now, the redness (R) of display signal S [1], blue (B) and green (G) information one after the other provide in time respectively to sub-pixel 100_1, and 1,100_1,3 and 100_1,2. Consult Fig. 4 B, in during second frame in during shows, during the enable of PSL1, clock signal CKG, CKB and CKR are in enabled status in order (for pixel groups PG1, the second enabled status combination of 1), and the enabled status of clock signal CKG, CKB and CKR do not overlap each other. Now, the green (G) of display signal S [1], blue (B) and red (R) information one after the other provide in time respectively to sub-pixel 100_1, and 2,100_1,3 and 100_1,1. Similarly, consult Fig. 4 C��Fig. 4 F, in referring now to pixel groups PG1,1, in during a display respectively third and fourth, five and six frames (also referred to as " picture frame ") periods third and fourth, five and six kind of enabled status combine.

Referring again to Fig. 4 A, in during first frame in during shows, during the enable of PSL2, clock signal CKG, CKB and CKR are in enabled status in order (for pixel groups PG2, the first enabled status combination of 1), and the enabled status of clock signal CKG, CKB and CKR do not overlap each other. Now, the green of display signal S [1], blueness and red information one after the other provide in time respectively to sub-pixel 100_2, and 2,100_2,3 and 100_2,1. Consult Fig. 4 B, in during second frame in during shows, during the enable of PSL2, clock signal CKR, CKB and CKG are in enabled status in order (for pixel groups PG2, the second enabled status combination of 1), and the enabled status of clock signal CKR, CKB and CKG do not overlap each other. Now, the redness of display signal S [1], blueness and green information one after the other provide in time respectively to sub-pixel 100_2, and 1,100_2,3 and 100_2,2. Similarly, consult Fig. 4 C��Fig. 4 F, in referring now to pixel groups PG2,1, in during a display respectively third and fourth, during five and six frames third and fourth, five and six kind of enabled status combine.

Can learn according to Fig. 4 A��Fig. 4 F, for pixel groups PG1,1, in during one shows, the pattern (enable order CKG-> CLB-> CKR) of the enabled status combination of clock signal during the second frame is in contrast to the pattern (enable order CKR-> CLB-> CKG) of the enabled status combination of clock signal during the first frame; The pattern (enable order CKB-> CLG-> CKR) of the enabled status combination of clock signal during the 4th frame is in contrast to the pattern (enable order CKR-> CLG-> CKB) of the enabled status combination of clock signal during the 3rd frame; The pattern (enable order CKB-> CLR-> CKG) of the enabled status combination of clock signal during the 6th frame is in contrast to the pattern (enable order CKG-> CLR-> CKB) of the enabled status combination of clock signal during the 5th frame. Similarly, for pixel groups PG2,1, in during one shows, first is opposite each other with the pattern that the enabled status of two clock signal during frame combines; During 3rd and four frames, the pattern of the enabled status combination of clock signal is opposite each other; During 5th and six frames, the pattern of the enabled status combination of clock signal is opposite each other.

Can learn according to Fig. 4 A, in during the first frame during shows, pixel groups PG1,1 and PG2,1 receives data signal S [1] in order in sequential. In other words, first by pixel groups PG1, the sub-pixel 100_1 of 1,1,100_1,3 and 100_1,2 receive the redness of data signal S [1], blueness and green information in order, then again by pixel groups PG2, the sub-pixel 100_2 of 1,2,100_2,3 and 100_2,1 receives the green of data signal S [1], blueness and red information in order. Can learning thus, the state of the clock signal CKG of corresponding green information is by during maintaining the enable of PSL2 during the enable of PSL1. That is, in during the enable of PSL1, clock signal CKR and CKB each has a trailing edge, and clock signal CKG does not have trailing edge.

Similarly, such as Fig. 4 B it can be seen that in during the second frame during one shows, the state of the clock signal CKR of corresponding red information is by during maintaining the enable of PSL2 during the enable of PSL1. That is, in during the enable of PSL1, clock signal CKG and CKB each has a trailing edge, and clock signal CKR does not have trailing edge. During one shows third and fourth, five and six during frame in, clock signal CKR, CKG and CKB trailing edge state by that analogy, as shown in Fig. 4 C��Fig. 4 F.

According to above-described embodiment, in during six pixels in during shows, six enabled status combinations by clock signal CKR, CKG and CKB, make to be sent to pixel groups PG1, the red information of 1 is subjected to the number of times of the Kickback voltage effect caused by clock signal CKR, being same as and be sent to pixel groups PG2, the red information of 1 is at the number of times of the Kickback voltage effect being subjected to caused by clock signal CKR. For pixel groups PG1,1 and PG2,1, the green situation being subjected to scan signal with blue information is also the same. Thus, in during one shows, display device 1 compensates, by the six of clock signal enabled status combinations, the voltage differences that above-mentioned Kickback voltage effect causes, in other words, the degree difference of same color in different pixels group can be reduced so that the image of display device 1 is more uniformly distributed by six enabled status of clock signal.

In another embodiment, two sub-pixels (K=2) belong to a pixel groups is that example is to illustrate that the application on-off circuit 13 operates. Consult Fig. 5, for scanning line SL1, first two sub-pixel 100_1,1 and 100_1,2 belong to pixel groups PG1, and 1; Two the sub-pixel 100_1 continued, 3 and 100_1,4 belong to pixel groups PG1, and 2; The ownership of other sub-pixel is by that analogy. For scanning line SL2, first two sub-pixel 100_2,1 and 100_2,2 belong to pixel groups PG2, and 1; Two the sub-pixel 100_2 continued, 3 and 100_2,4 belong to pixel groups PG2, and 2; The ownership of other sub-pixel is by that analogy. In order to know the relation illustrated between sub-pixel and pixel groups, Fig. 5 only shows the sub-pixel on scanning line SL1 and SL2 and pixel groups. On other scanning line SL3��and SLn, the relation between sub-pixel and pixel groups is such as scanning line SL1 and SL2, therefore omits at this. Consulting Fig. 5, pixel groups PG1,1 and PG2,1 is coupled to identical data wire DL1 and DL2 and pixel groups PG1, and 2 and PG2,2 are coupled to identical data wire DL3 and DL4.

Such as the embodiment of Fig. 2, in embodiments of the present invention, the quantity of on-off circuit 13 breaker in middle unit scans the quantity of pixel groups on line equal to according at same. Consequently, it is possible to the pixel groups coupling same scanning line is respectively coupled to different switch elements, and couples adjacent two scanning lines and couple two pixel groups of identical data wire and be coupled to same switch element. Configuration between pixel groups and switch element, such as the embodiment of Fig. 2, omits narration at this.

In the 5 embodiment of figure 5, the information that two sub-pixels in each pixel groups are corresponding different respectively. As it is shown in figure 5, at pixel groups PG1,1 and PG2, in 1, corresponding red (R) and green (G) and blue (B) information sub-pixel is sequentially to configure respectively. At pixel groups PG1,2 and PG2, in 2, corresponding blue (B) respectively and red (R) information sub-pixel is sequentially to configure. With all pixel groups scanned on line, the sub-pixel of corresponding red (R), green (G) and blue (B) information is configuration sequentially and repeatedly respectively.

Owing to the driving of array of display 10 is to adopt time-division switching (to be also called solution multiplexing (de-multiplexer, DEMUX) driving method), therefore, the quantity of clock signal produced by clock generator 14 determines according to the quantity (K) of sub-pixel in each pixel groups. In the 5 embodiment of figure 5, the quantity of clock signal produced by clock generator 14 determines equal to the quantity of sub-pixel in each pixel groups, and namely clock generator 14 produces three clock signal CK1 and CK2 (K=2), to control each switch element. Fig. 6 represents the circuit framework of each switch element. Consulting Fig. 6, each switch element includes two switches 60 and 61, to realize solution multiplexing's driving method of 1:2. . Switch 60 and 61 grids receive clock signal CK1 and CK2 respectively. The drain electrode of switch 60 and 61 couples source electrode driver 12. Switch 60 is respectively coupled to corresponding data wire with the source electrode of 61. For example, for the switch 60 and 61 of switch element 130_1, its grid receives clock signal CK1 and CK2 respectively, and its drain electrode couples source electrode driver 12 to receive data signal S [1], and its source electrode is respectively coupled to data wire DL1 and DL2. Other switch element has the framework identical with switch element 130_1, therefore omits related description at this. When clock signal is in enabled status, the switch conduction of its correspondence, to be sent to colouring information corresponding in data signal the data wire of correspondence. For example, for switch element 130_1, when clock signal CK1 is in enabled status, switch 60 conducting, to be sent to data wire DL1 red information corresponding in data signal S [1]; When clock signal CK2 is in enabled status, switch 61 conducting, to be sent to data wire DL2 green information corresponding in data signal S [1]. For switch element 130_2, when clock signal CK1 is in enabled status, switch 60 conducting, to be sent to data wire DL3 blue information corresponding in data signal S [2]; When clock signal CK2 is in enabled status, switch 61 conducting, to be sent to data wire DL4 red information corresponding in data signal S [2]. For switch element 130_3, when clock signal CK1 is in enabled status, switch 60 conducting, to be sent to data wire DL5 green information corresponding in data signal S [3]; When clock signal CK2 is in enabled status, switch 61 conducting, to be sent to data wire DL6 blue information corresponding in data signal S [3]. In this embodiment, the relation between operation and clock signal and the colouring information of other switch elements is such as switch element 130_1��130_3.

In this embodiment, for each pixel groups, in during each display, the enabled status number of combinations of clock signal CK1 and CK2 is equal to 2 (X=2 �� C^K ₂, wherein, K=2). Therefore, during including two frames during each display, and for each pixel groups, two enabled status of clock signal CK1 and CK2 combine in during two frames in respectively during occurring in a display.

Fig. 7 A and Fig. 7 B is illustrated respectively in during two frames during a display, two enabled status combinations of clock signal CK1 and CK2. Below will with pixel groups PG1,1 and PG2,1, the colouring information of clock signal CK1 and CK2 and correspondence be that example illustrates that two enabled status of the clock signal in during shows combine. In Fig. 7 A and Fig. 7 B, PSL1 represents pixel groups PG1,1 sequential receiving data signal S [1], namely during the enable of PSL1, switch 60 and 61 conducting of switch element 103_1, to be sent to sub-pixel 100_1 with green information respectively through data wire DL1 and DL2 by red in data signal S [1], 1 and 100_1,2. In Fig. 7 A and Fig. 7 B, PSL2 represents pixel groups PG2,1 sequential receiving data signal S [1], namely during the enable of PSL2, switch 60 and 61 conducting of switch element 103_1, to be sent to sub-pixel 100_2 with green information respectively through data wire DL1 and DL2 by red in data signal S [1], 1 and 100_2,2.

Consult Fig. 7 A, in during first frame in during shows, during the enable of PSL1, clock signal CK1 and CK2 is in enabled status in order (for pixel groups PG1, the first enabled status combination of 1), and the enabled status of clock signal CK1 and CK2 do not overlap each other. Now, the redness (R) of display signal S [1] and green (G) information one after the other provide in time respectively to sub-pixel 100_1, and 1 and 100_1,2. Consult Fig. 7 B, in during second frame in during shows, during the enable of PSL1, clock signal CK2 and CK1 is in enabled status in order (for pixel groups PG1, the second enabled status combination of 1), and the enabled status of clock signal CK1 and CK2 do not overlap each other. Now, the green (G) of display signal S [1] and red (R) information one after the other provide in time respectively to sub-pixel 100_1, and 2 and 100_1,1.

Referring again to Fig. 7 A, in during first frame in during shows, during the enable of PSL2, clock signal CK2 and CK1 is in enabled status in order (for pixel groups PG2, the first enabled status combination of 1), and the enabled status of clock signal CK1 and CK2 do not overlap each other. Now, green and the red information of display signal S [1] one after the other provides in time respectively to sub-pixel 100_2, and 2 and 100_2,1. Consult Fig. 7 B, in during second frame in during shows, during the enable of PSL2, clock signal CK1 and CK2 is in enabled status in order (for pixel groups PG2, the second enabled status combination of 1), and the enabled status of clock signal CK1 and CK2 do not overlap each other. Now, redness and the green information of display signal S [1] one after the other provides in time respectively to sub-pixel 100_2, and 1 and 100_2,2.

Can learn according to Fig. 7 A and Fig. 7 B, for pixel groups PG1,1, in during one shows, the pattern (enable order CK2-> CL1) of the enabled status combination of clock signal during the second frame is in contrast to the pattern (enable order CK1-> CL2) of the enabled status combination of clock signal during the first frame. Similarly, for pixel groups PG2,1, in during one shows, first is opposite each other with the pattern that the enabled status of two clock signal during frame combines.

Can learn according to Fig. 7 A, in during the first frame during shows, pixel groups PG1,1 and PG2,1 receives data signal S [1] in order in sequential. In other words, first by pixel groups PG1, the sub-pixel 100_1 of 1,1 and 100_1,2 redness and the green informations receiving data signal S [1] in order, then again by pixel groups PG2, the sub-pixel 100_2 of 1,2 and 100_2,1 receives green and the red information of data signal S [1] in order. Can learning thus, the state of clock signal CK2 is by during maintaining the enable of PSL2 during the enable of PSL1. That is, in during the enable of PSL1, clock signal CK1 has a trailing edge, and clock signal CK2 does not have trailing edge.

Similarly, such as Fig. 7 B it can be seen that in during the second frame during one shows, the state of clock signal CK1 is maintained during the enable of PSL2 by during the enable of PSL1. That is, in during the enable of PSL1, clock signal CK2 has a trailing edge, and clock signal CK1 does not have trailing edge.

According to above-described embodiment, in during two pixels in during shows, combined by the two of clock signal CK1 and CK2 enabled status, make to be sent to pixel groups PG1, the green information of 1 is subjected to the number of times of the Kickback voltage effect caused by clock signal CK2, being same as and be sent to pixel groups PG2, the green information of 1 is at the number of times of the Kickback voltage effect being subjected to caused by clock signal CK2. For pixel groups PG1,1 and PG2,1, it is also the same that red information is subjected to the situation of scanning signal. Thus, in during one shows, display device 1 compensates, by the two of clock signal enabled status combinations, the voltage differences that above-mentioned Kickback voltage effect causes, in other words, the degree difference of same color in different pixels group can be reduced so that the image of display device 1 is more uniformly distributed by two enabled status of clock signal.

Though the present invention is with preferred embodiment openly as above; so it is not limited to the scope of the present invention; without departing from the spirit and scope of the present invention, when doing a little change and retouching, therefore protection scope of the present invention is when being as the criterion depending on appended claims confining spectrum for those skilled in the art.

Claims (10)

1. a display device, operates during multiple displays, including:

Multiple scanning lines;

Multiple data wires, are crisscross arranged with described scanning line, and transmit multiple data signal, and wherein, this data signal each has multiple colouring information; And

Multiple sub-pixels, couple described scanning line and described data wire, in the corresponding described colouring information of this sub-pixel each one;

Multiple clock signals, correspondence couples described sub-pixel respectively;

Wherein, on this scanning line same, the described sub-pixel of each predetermined number belongs to a pixel groups, and the described sub-pixel of this pixel groups each receives in described data signal one according to the enabled status of the described clock signal with this predetermined number respectively;

Wherein, for coupling identical described data wire and being respectively coupled to two described pixel groups of adjacent two bar described scanning line, two described pixel groups are passed through corresponding described data wire in order and are received in described data, and are belonging respectively in two described pixel groups and two the described sub-pixels described colouring informations of reception receiving this corresponding data signal that continue in sequential one;

Wherein, for this pixel groups each, during this display each, the enabled status of described clock signal has certain amount of multiple combination, and this specific quantity is 2 �� C^K ₂, C represents and takes two described clock signals in the described clock signal of this predetermined number, and K is positive integer; And

Wherein, this certain amount of described combination at least includes the first combination and is connected in the second combination of this first combination, and the enabled status order of the described clock signal of this second combination is in contrast to the enabled status order of the described clock signal of this first combination.

2. display device as claimed in claim 1, wherein, includes this specific quantity frame time and a combination in this certain amount of described enabled status of the corresponding described clock signal of this frame time each during this display each.

3. display device as claimed in claim 1, wherein, this predetermined number is more than or equal to 2.

4. display device as claimed in claim 1, wherein, in this pixel groups each, described sub-pixel receives colouring informations different in corresponding described data signal.

5. display device as claimed in claim 1, also includes:

On-off circuit, couples described data wire, and includes:

Multiple switches, receive described data signal respectively, and are respectively coupled to described data wire;

Wherein, for this pixel groups each, corresponding described switch is subject to the described clock signal of this predetermined number respectively and is controlled, so that corresponding described data signal to be sent to the described data wire of correspondence.

6. a display device, operates during multiple displays, including:

Multiple scanning lines;

Multiple data wires, are crisscross arranged with described scanning line, and transmit multiple data signal, and wherein, this data signal each has multiple colouring information; And

Multiple sub-pixels, couple described scanning line and described data wire, in the corresponding described colouring information of this sub-pixel each one;

Multiple clock signals, correspondence couples described sub-pixel respectively;

Wherein, on this scanning line same, the described sub-pixel of each predetermined number belongs to a pixel groups, and the described sub-pixel of this pixel groups each receives in described data signal one according to the enabled status of the described clock signal with this predetermined number respectively;

Wherein, for coupling identical described data wire and being respectively coupled to two described pixel groups of adjacent two bar described scanning line, two described pixel groups are passed through corresponding described data wire in order and are received in described data, and are belonging respectively in two described pixel groups and two the described sub-pixels described colouring informations of reception receiving this corresponding data signal that continue in sequential one;

Wherein, for coupling identical described data wire and being respectively coupled to two described sub-pixels of two adjacent two described scanning lines, in during each display, the number of times of the Kickback voltage effect caused by described clock signal being subject to correspondence is identical; And

Wherein, for this pixel groups each, during this display each, this certain amount of described combination at least includes the first combination and is connected in the second combination of this first combination, and the enabled status order of the described clock signal of this second combination is in contrast to the enabled status order of the described clock signal of this first combination.

7. display device as claimed in claim 6, wherein, in two described pixel groups of corresponding identical described data wire and two corresponding adjacent respectively described scanning lines, each of the described sub-pixel of corresponding same color information, it is identical to be arranged in this pixel groups of correspondence the number of times of an ad-hoc location in during this display each.

8. display device as claimed in claim 6, wherein, this predetermined number is more than or equal to 2.

9. display device as claimed in claim 6, wherein, in this pixel groups each, described sub-pixel receives colouring informations different in corresponding described data signal.

10. display device as claimed in claim 6, also includes:

On-off circuit, couples described data wire, and includes:

Multiple switches, receive described data signal respectively, and are respectively coupled to described data wire;

Wherein, for this pixel groups each, corresponding described switch is subject to the described clock signal of this predetermined number respectively and is controlled, so that corresponding described data signal to be sent to the described data wire of correspondence.