CN105610502A - Special visible light communication based integrated circuit for receiver - Google Patents

Abstract

A receiver ASIC based on visible light communication, including a transimpedance amplifier connected in sequence for converting the obtained current signal into a voltage signal and amplifying it, and amplifying the voltage signal output by the transimpedance amplifier to a digital voltage A horizontal limiting amplifier, the input end of the transimpedance amplifier is connected to the output end of the pre-equalizing unit used to compensate the current received from the photodiode, and the output end of the limiting amplifier is connected for limiting the output from the photodiode. The input terminal of the post-equalization unit for secondary compensation of the voltage signal output by the amplifier, the output terminal of the post-equalization unit is connected to the input terminal of the comparator used for signal judgment, and the output of the comparator constitutes a receiver based on visible light communication ASIC output. The invention effectively reduces the volume and reduces the errors brought in when each module is cascaded. It has the advantages of low power consumption, high integration, low cost, and easy mass production.

Description

A receiver ASIC based on visible light communication

technical field

The invention relates to an integrated circuit. In particular, it relates to a receiver application specific integrated circuit based on visible light communication.

Background technique

In recent years, with the rapid development of electronic technology, the total number of users and the penetration rate of smart devices have increased significantly year by year, and people's demand for high-speed broadband multimedia communication has also increased. At this time, the traditional radio frequency communication has a shortage of spectrum resources, coupled with the limitations of electromagnetic radiation interference and other factors, and people's increasing attention to the impact of radiation on physical health, prompting the creation of a resource that can broaden the spectrum, through green and energy-saving LED lights. The communication method of the transmission base station - visible light communication. In recent years, with the development of white light LED technology, the potential of VLC technology in various scenarios has begun to show, and it has attracted more and more attention at home and abroad.

Compared with infrared wireless optical communication systems, the light emitted by white LEDs in VLC systems is safe for human eyes, so the transmission power can be very high. Higher transmit power, the light intensity is still very weak. Most VLC systems are designed as light intensity modulation and direct detection systems (Intensity modulation/direct detection, IM/DD). The strength of the light signal received by the receiver photoelectric detection device will directly determine whether the entire system can work normally. At the same time, the light emitted by the LED is modulated at high speed, and the bandwidth and response rate of the receiver must be able to match the light source of the modulated signal. Therefore, designing a receiver that meets the performance requirements and costs less is the key to the wide application of visible light communication technology.

The research on receivers in visible light communication has just started in the past two years. In terms of design process, gallium arsenide or bipolar silicon processes have been used to realize them in the past, but they have the disadvantages of high cost, high power consumption, and low integration. In addition, due to the large difference in the characteristics of the receiving devices, the overall structure of the system contains many modules, and the interaction between them is more complicated. The existing research is mainly based on the research on its feasibility, and the receivers are built using commercial discrete modules. device to perform the function. Therefore, the overall stand-alone receiver ASIC designed for VLC system is in the innovative research and development stage, and there are few reports on this aspect.

Contents of the invention

The technical problem to be solved by the present invention is to provide a receiver application specific integrated circuit based on visible light communication that can effectively reduce the volume and reduce the error introduced when each module is cascaded.

The technical solution adopted in the present invention is: a receiver ASIC based on visible light communication, including a transimpedance amplifier connected in sequence for converting the obtained current signal into a voltage signal and amplifying it; The voltage signal output by the amplifier is amplified to a limiting amplifier at a digital voltage level, the input terminal of the transimpedance amplifier is connected to the output terminal of the pre-equalizing unit used to compensate the current received from the photodiode, and the limiting amplifier The output terminal is connected to the input terminal of the post-equalization unit for performing secondary compensation to the voltage signal output from the limiting amplifier, and the output terminal of the post-equalization unit is connected to the input terminal of a comparator used as a signal judgment, and the comparator The output of constitutes the output of the receiver ASIC based on visible light communication.

The front equalization unit includes: a current source and a first capacitor connected in parallel, one end of the current source and the first capacitor is connected to the voltage VDD, and the other end of the current source and the first capacitor is respectively connected to the first resistor One end, one end of the inductance and the gate of the first NMOS transistor, the other end of the inductance is grounded through the second resistor, and the other end of the first resistor and the drain of the first NMOS transistor are commonly connected to the source of the second NMOS transistor pole, this end of the first resistor, the drain of the first NMOS transistor and the source of the second NMOS transistor jointly constitute the output end of the pre-equalization unit connected to the input end of the transimpedance amplifier, and the drain of the second NMOS transistor The gate is connected to the voltage VDD, and the gate is connected to the voltage VDD through the third resistor.

The post-equalization unit includes a second capacitor and a fourth resistor connected in parallel, one end of the second capacitor and the fourth resistor is commonly connected to the output end of the limiting amplifier, and the second capacitor and the fourth resistor The other end of the second capacitor and the fourth resistor are connected to the ground through a load resistor, and the output end of the post-balance unit is connected to the input end of the comparator.

A receiver application specific integrated circuit based on visible light communication of the present invention, through a new system topology, simultaneously uses pre-equalization and post-equalization techniques to increase bandwidth, integrates the optical receiver as a whole, and effectively reduces the volume and reduces the The error introduced when each module is cascaded is eliminated. The overall use of standard CMOS process monolithic integration realizes the receiver function of high-speed data in the visible light environment, and has the advantages of low power consumption, high integration, low cost, and easy mass production. The present invention has the following advantages:

1. Based on the emerging visible light communication technology, the data receiving function in the visible light environment is realized. Compared with the traditional radio frequency communication technology, it has the advantages of wide applicability, strong anti-interference and confidentiality, and no electromagnetic radiation is harmless to the human body. There are many advantages in dangerous goods storage and item detection in special places.

2. Visible light receiver chip. Manufactured using a relatively mature CMOS process, replacing the existing discrete device system structure of various parts, achieving high integration, reducing volume and cost. It provides the possibility for the research and development of miniature visible light detection equipment and large-scale promotion.

3. The circuit structure of pre-equalization and post-equalization is added to the circuit structure at the same time, which improves the overall bandwidth of the receiver and improves the information and data transmission capability of the receiver. It provides a foundation for the overall visible light communication integrated system to carry out big data transmission.

4. This circuit adopts a low-power design method to effectively control the energy consumption of the overall optical receiver chip. Compared with the existing receiver, it only needs to provide milliwatt-level energy to work, which improves the continuous operation of the receiving system ability, significantly reducing the energy consumption problem in practical use.

To sum up, the VLC-based receiver ASIC structure and implementation method proposed by the present invention have good application prospects.

Description of drawings

Fig. 1 is a schematic structural diagram of the application of the present invention in a visible light receiving end system;

Fig. 2 is a block diagram of a receiver application specific integrated circuit based on visible light communication in the present invention;

Fig. 3 a is the circuit schematic diagram of front equalization unit in the present invention;

Fig. 3 b is the equivalent circuit of the parallel resonant circuit in the front equalization unit of the present invention;

Fig. 3c is the equivalent circuit diagram of the RLC network in the front equalization unit of the present invention;

Fig. 4 is a schematic circuit diagram of the post equalization unit in the present invention.

in the picture

1: blue filter 2: integrated circuit chip

3: Digital terminal or oscilloscope 21: Front equalization unit

22: Transimpedance amplifier 23: Limiting amplifier

24: Post equalization unit 25: Comparator

detailed description

A VLC-based receiver ASIC of the present invention will be described in detail below in conjunction with the implementation process and the accompanying drawings.

FIG. 1 shows a schematic structural diagram of a visible light receiving end system applied in the present invention. As shown in Figure 1, the silicon PIN photodiode PD is used as a visible light detector, and the visible light loaded with the 0/1 signal emitted by the front-end white light LED is converted into a current signal through the blue filter 1, and then through the visible light communication based on the present invention. The receiver ASIC chip 2 converts the tiny current signal into a voltage signal at a digital voltage level.

As shown in FIG. 2, a receiver ASIC based on visible light communication of the present invention includes a transimpedance amplifier 22 connected in sequence for converting the obtained current signal into a voltage signal and amplifying it, and for converting the transimpedance Impedance amplifier 22 outputs a voltage signal with a very small amplitude and amplifies it to a limiting amplifier 23 at a digital voltage level, and the input terminal of said transimpedance amplifier 22 is connected to the pre-equalizing unit 21 for compensating the current received from photodiode PD Output terminal, the output terminal of described limiting amplifier 23 is connected to the input terminal of the rear equalization unit 24 that is used to carry out secondary compensation to the voltage signal output from limiting amplifier 23, and the output terminal of described rear equalization unit 24 is connected as The input terminal of the comparator 25 for signal judgment, the output of the comparator 25 constitutes the receiver ASIC based on visible light communication. The output terminal is connected to the digital terminal for modulation or connected to the oscilloscope 3 .

The received visible light signal flows out from the PIN photodiode PD in the form of a weak current, and enters the transimpedance amplifier after being compensated by the pre-equalization module, where the current is converted into a small voltage signal. Then, the signal is amplified through multi-stage limiting amplifiers, and the obtained larger swing voltage signal is post-equalized for secondary compensation. Since the junction capacitance of the detector itself is often relatively large, coupled with the parasitic effects generated by all levels of the circuit, the obtained signal has been deformed at this time, which is not conducive to the modulation processing of the back-end digital module, so a hysteresis comparator is added after post-equalization , to process the waveform to achieve the purpose of adjusting the waveform, so that the output can be restored to the original signal at the digital voltage level, and the transmission of the visible light signal can be completed. The output terminal can also be connected to an oscilloscope to observe the received signal.

Pre-equalization means that before the photo-generated input current signal generated by the photodetector enters the transimpedance preamplifier, the electrical bandwidth of the input signal is improved by means of compensation to restore the high-frequency components in the signal and prevent the high-frequency signal from being amplified. The circuit cannot be restored due to excessive loss. The pre-equalization module in the present invention is realized by using parallel resonant circuit peaking technology.

As shown in FIG. 3a, the front equalization unit 21 includes: a current source I _s and a first capacitor C _pd connected in parallel, one terminal of the current source I _s and the first capacitor C _pd is connected to a voltage VDD, and the The other end of the current source I _s and the first capacitor C _pd are respectively connected to one end of the first resistor R _fA , one end of the inductor L _eq and the gate of the first NMOS transistor n _A1 , and the other end of the inductor L _eq passes through the second The resistor R _eq is grounded, the other end of the first resistor R _fA and the drain of the first NMOS transistor n _A1 are jointly connected to the source of the second NMOS transistor nA2, and this end of the first resistor R _fA is connected to the drain of the first NMOS transistor nA1. The drain of _A1 and the source of the second NMOS transistor n _A2 also together form the output end of the pre-equalization unit 21 connected to the input end of the transimpedance amplifier 22, the drain of the second NMOS transistor n _A2 is connected to the voltage VDD, and the gate The voltage VDD is connected through the third resistor _RdA .

The photodiode PD, the current source I _s and the first capacitor C _pd are connected in parallel to form an equivalent circuit of the photodetector, which are respectively the ideal photodiode, the photogenerated current and the junction capacitance of the photodetector. The inductance L _eq and the second resistance R _eq are the on-chip inductance and resistance respectively, and they are related to the input capacitance C _in of the transimpedance preamplifier (approximately equal to the gate-source capacitance C _{gs,A2 of the NMOS transistor n A2 )} , the input resistance R _{in, A} constitutes a parallel resonant tank (as shown in Figure 3b).

Since the impedances of the LR parts connected in series and in parallel are equal, the relationship is as follows:

${\mathrm{<span\; class="notranslate">\; j\&omega;</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}{\mathrm{<span\; class="notranslate">\; L</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}}<span\; class="notranslate">\; =</span><span\; class="notranslate">\; \&lsqb;</span><span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; j\&omega;</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}{\mathrm{<span\; class="notranslate">\; L</span>}}_{\mathrm{<span\; class="notranslate">\; P</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; |</span><span\; class="notranslate">\; |</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; P</span>}}<span\; class="notranslate">\; \&rsqb;</span><span\; class="notranslate">\; =</span>\frac{{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; \&omega;</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}{\mathrm{<span\; class="notranslate">\; L</span>}}_{\mathrm{<span\; class="notranslate">\; P</span>}}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; P</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; j\&omega;</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}{\mathrm{<span\; class="notranslate">\; L</span>}}_{\mathrm{<span\; class="notranslate">\; P</span>}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; P</span>}}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}}{{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; P</span>}}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; \&omega;</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}{\mathrm{<span\; class="notranslate">\; L</span>}}_{\mathrm{<span\; class="notranslate">\; P</span>}}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}}$

Where Q＝R _P /ω ₀ L _P ＝ω ₀ L _S /R _S , then:

R _P ＝ R _S (Q ² +1)

${\mathrm{<span\; class="notranslate">\; L</span>}}_{\mathrm{<span\; class="notranslate">\; P</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; L</span>}}_{\mathrm{<span\; class="notranslate">\; S</span>}}<span\; class="notranslate">\; (</span>\frac{{\mathrm{<span\; class="notranslate">\; Q</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; Q</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}}<span\; class="notranslate">\; )</span>$

Equivalent this circuit to a typical RLC network (Figure 3c), where:

R＝[R _eq (1+Q ² )]||R _in,A

$\mathrm{<span\; class="notranslate">\; L</span>}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; L</span>}}_{\mathrm{<span\; class="notranslate">\; e</span>}\mathrm{<span\; class="notranslate">\; q</span>}}<span\; class="notranslate">\; (</span>\frac{{\mathrm{<span\; class="notranslate">\; Q</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; Q</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}}<span\; class="notranslate">\; )</span>$

C＝C _pd +C _gs,A2

Then the resonant frequency of the resonant circuit is

In addition, the first NMOS transistor n _A1 and the third resistor R _dA of the load of the transimpedance preamplifier form an active inductance, and they also form a parallel resonant circuit with the input capacitance and input resistance of the next stage. The resonant peaks generated by the two resonant circuits overlap each other through parameter optimization and adjustment, which can effectively improve the bandwidth of the pre-transimpedance amplifier. In addition, the input resistance of the optical receiver can be increased by greatly increasing the resistance values of the first resistor R _fA used as a transimpedance and the second resistor Req used as a pre-resistance, and the first resistor R _fA and the second resistor R _eq can be reduced. Noise current introduced by resistor R _eq .

As shown in Figure 4, the post equalization unit 24 includes a second capacitor C and a fourth resistor R connected in parallel, one end of the second capacitor C and the fourth resistor R are commonly connected to the limiting amplifier 13 The output terminal, the other end of the second capacitor C and the fourth resistor R is grounded through a load resistor _RL , and this end of the second capacitor C and the fourth resistor R also constitutes the output terminal of the post-equalizing unit 24 to connect to the comparison The input terminal of device 25.

The frequency response transfer function of this equalizer is

${\mathrm{<span\; class="notranslate">\; h</span>}}_{\mathrm{<span\; class="notranslate">\; e</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; \&omega;</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; k</span>}}<span\; class="notranslate">\; \&times;</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; j</span>}\mathrm{<span\; class="notranslate">\; \&omega;</span>}\mathrm{<span\; class="notranslate">\; T</span>}}{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; j</span>}\mathrm{<span\; class="notranslate">\; \&omega;</span>}\mathrm{<span\; class="notranslate">\; T</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; k</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>$

Among them, 1/k= _RL /(R+ _RL ), T=RC, _RL is the load resistance, and 1/k is the DC coefficient of the equalizer (ω=0). Then its magnitude response is

$<span\; class="notranslate">\; |</span>{\mathrm{<span\; class="notranslate">\; h</span>}}_{\mathrm{<span\; class="notranslate">\; e</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; \&omega;</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; |</span><span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; k</span>}}<span\; class="notranslate">\; \&times;</span>\sqrt{\frac{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; \&omega;</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; T</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}}{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; \&omega;</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; T</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; /</span>{\mathrm{<span\; class="notranslate">\; k</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span>$

The 3dB point calculation for this equalizer is

${\mathrm{<span\; class="notranslate">\; \&omega;</span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}\mathrm{<span\; class="notranslate">\; d</span>}\mathrm{<span\; class="notranslate">\; B</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; T</span>}}\sqrt{\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; /</span>{\mathrm{<span\; class="notranslate">\; k</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; )</span>$

when , this 3dB point exists. Around this _3dB point, |He (ω)| is approximately linear. The slope s _e of the equalizer frequency response can be approximated as

${\mathrm{<span\; class="notranslate">\; the\; s</span>}}_{\mathrm{<span\; class="notranslate">\; e</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 6</span>}\mathrm{<span\; class="notranslate">\; \&pi;</span>}\mathrm{<span\; class="notranslate">\; T</span>}}{\sqrt{\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; /</span>{\mathrm{<span\; class="notranslate">\; k</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; )</span>$

In order to balance the gains of the high-frequency band and low-frequency band of the blue light component, the response of the equalizer requires s _e = -s _b , where s _b is the slope of the frequency response curve of the blue light component without equalization, which is approximately -0.24dB/MHz. The expected bandwidth obtained by equalization can be approximated as

${\mathrm{<span\; class="notranslate">\; W</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; a</span>}\mathrm{<span\; class="notranslate">\; x</span>}}<span\; class="notranslate">\; \&le;</span>\frac{\mathrm{<span\; class="notranslate">\; 20</span>}\mathrm{<span\; class="notranslate">\; lg</span>}\mathrm{<span\; class="notranslate">\; k</span>}}{<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; the\; s</span>}}_{\mathrm{<span\; class="notranslate">\; b</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 5</span>}<span\; class="notranslate">\; )</span>$

It can be seen from (4) and (5) that the choice of T and k will determine the equalization bandwidth and the gain of the equalized signal. Choosing a larger k value will result in a higher modulation bandwidth.

Claims (3)

1. A receiver ASIC based on visible light communication, comprising a transimpedance amplifier (22) connected in sequence for converting the obtained current signal into a voltage signal and amplifying it and for converting the transimpedance amplifier (22) The output voltage signal is amplified to the limiting amplifier (23) of digital voltage level, it is characterized in that, the input terminal of described transimpedance amplifier (22) is connected to be used for from the front that the electric current that photodiode (PD) receives is compensated The output end of the equalization unit (21), the output end of the limiting amplifier (23) is connected to the input end of the rear equalization unit (24) for performing secondary compensation to the voltage signal output from the limiting amplifier (23), The output end of the post-equalization unit (14) is connected to the input end of a comparator (25) used for signal judgment, and the output of the comparator (25) constitutes the output of a receiver ASIC based on visible light communication. 2. A receiver ASIC based on visible light communication according to claim 1, characterized in that said pre-equalization unit (21) includes: a current source (I _s ) connected in parallel and a first capacitor (C _pd ), one end of the current source (I _s ) and the first capacitor (C _pd ) is connected to the voltage VDD, and the other end of the current source (I _s ) and the first capacitor (C _pd ) is respectively connected to the first One end of the resistor (R _fA ), one end of the inductor (L _eq ) and the gate of the first NMOS transistor (n _A1 ), the other end of the inductor (L _eq ) is grounded through the second resistor (R _eq ), the The other end of the first resistor (R _fA ) and the drain of the first NMOS transistor (n _A1 ) are connected to the source of the second NMOS transistor (n _A2 ), and this end of the first resistor (R _fA ) is connected to the first NMOS transistor (n A1 ). The drain of the tube (n _A1 ) and the source of the second NMOS tube (n _A2 ) also jointly form the output end of the front equalization unit (21) to connect the input end of the transimpedance amplifier (22), and the second NMOS tube ( The drain of n _A2 ) is connected to the voltage VDD, and the gate is connected to the voltage VDD through the third resistor (R _dA ). 3. A receiver ASIC based on visible light communication according to claim 1, characterized in that the post-equalization unit (24) includes a second capacitor (C) and a fourth resistor (C) connected in parallel R), one end of the second capacitor (C) and the fourth resistor (R) are commonly connected to the output of the limiting amplifier (23), the second capacitor (C) and the fourth resistor (R) The other end is grounded through a load resistor ( _RL ), and this end of the second capacitor (C) and the fourth resistor (R) also constitutes the output end of the rear equalization unit (24) and is connected to the input end of the comparator (25). .