CN105609560A - Semiconductor device having high quality epitaxial layer and method of manufacturing the same - Google Patents
Semiconductor device having high quality epitaxial layer and method of manufacturing the same Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
A semiconductor device having a high-quality epitaxial layer and a method of manufacturing the same are disclosed. According to an embodiment, a semiconductor device may include: a substrate; a fin-shaped first semiconductor layer spaced apart from the substrate, the first semiconductor layer including a first portion and a second portion along a longitudinal extension thereof; a second semiconductor layer at least partially surrounding a first portion of the first semiconductor layer; a third semiconductor layer at least partially surrounding an outer periphery of the second portion of the first semiconductor layer; an isolation layer formed on the substrate, the isolation layer at least partially exposing the second semiconductor layer and the third semiconductor layer, the exposed second semiconductor layer and the exposed third semiconductor layer respectively extending in a fin shape; and a first gate stack intersecting the second semiconductor layer and a second gate stack intersecting the third semiconductor layer formed on the isolation layer.
Description
Technical field
The disclosure relates to semiconductor applications, more specifically, relates to one and has high-quality epitaxial layerSemiconductor devices and manufacture method thereof.
Background technology
Along with the development of semiconductor devices, expect with mobility the semiconductor material higher than silicon (Si)Material is made high-performance semiconductor device as mos field effect transistor(MOSFET). But, be difficult to form high-quality high mobility semiconductor material.
Summary of the invention
Object of the present disclosure is to provide a kind of half of high-quality epitaxial layer that has at least in partConductor device and manufacture method thereof.
According to an aspect of the present disclosure, a kind of semiconductor devices is provided, comprising: substrate;With fin-shaped the first semiconductor layer that substrate separates, the first semiconductor layer is along its direction extending longitudinallyComprise Part I and Part II; At least partly outside the Part I around the first semiconductor layerSecond semiconductor layer in week; At least partly around the of the Part II periphery of the first semiconductor layerThree semiconductor layers; The separation layer forming on substrate, separation layer exposes the second half at least in partConductor layer and the 3rd semiconductor layer, the second semiconductor layer exposing and the 3rd semiconductor layer are respectivelyFin-shaped is extended; And the first grid crossing with the second semiconductor layer forming on separation layer is stackingAnd the second gate stack crossing with the 3rd semiconductor layer.
According to another aspect of the present disclosure, provide a kind of method of manufacturing semiconductor devices, bagDraw together: on substrate, form fin structure; Cover a part for fin structure, with at the first deviceFin structure is exposed in region; At the first device area, for the fin structure exposing, remove itNear the part of substrate, to form the Part I of the first semiconductor layer, this Part I withSubstrate is separated; At the first device area, taking the Part I of the first semiconductor layer as Seed Layer,Second semiconductor layer of growing; Cover the first device area, and expose fin-shaped at the second device areaStructure; At the second device area, for the fin structure exposing, remove it near one of substratePart, to form the Part II of the first semiconductor layer, this Part II and substrate are separated;And at the second device area, taking the Part II of the first semiconductor layer as Seed Layer, growth regulationThree semiconductor layers.
According to embodiment of the present disclosure, can utilize (thin) the first half suspending with respect to substrateConductor layer is as Seed Layer, second, third semiconductor layer of growing, and second and/or the 3 half leadsBody layer can have high mobility. This thin Seed Layer that suspends can make first, second and/orStress relaxation in three semiconductor layers, thus contribute to suppress or avoid in these semiconductor layersProduce defect. In addition, structure of the present invention is specially adapted to CMOS (CMOSSemiconductor) technique.
Brief description of the drawings
By the description to disclosure embodiment referring to accompanying drawing, of the present disclosure above-mentioned with andHis object, feature and advantage will be more clear, in the accompanying drawings:
Fig. 1-2 2 is the manufacture semiconductor devices stream having schematically shown according to disclosure embodimentThe schematic diagram of journey.
Detailed description of the invention
Below, embodiment of the present disclosure is described with reference to the accompanying drawings. But should be appreciated that, theseDescription is exemplary, and does not really want to limit the scope of the present disclosure. In addition, in following explanationIn, omit the description to known features and technology, of the present disclosure to avoid unnecessarily obscuringConcept.
Shown in the drawings according to the various structural representations of disclosure embodiment. These figure alsoNon-ly draw in proportion, wherein, for the clear object of expressing, amplified some details, andAnd may omit some details. Various regions shown in figure, layer shape and theyBetween relative size, position relationship be only exemplary, may be due to manufacturing tolerance in realityOr technical limitations and deviation to some extent, and those skilled in the art according to reality is required can be in additionDesign has the regions/layers of difformity, size, relative position.
In context of the present disclosure, when one deck/element is called be positioned at another layer/element " on "Time, this layer/element can be located immediately on this another layer/element, or can deposit between themAt intermediate layer/element. In addition, if be positioned at another layer/element in one towards middle one deck/element" on ", so when turn towards time, this layer/element can be positioned at this another layer/element D score.
According to embodiment of the present disclosure, provide a kind of semiconductor device with the fin structure that suspendsPart. Particularly, the fin of this device suspends with respect to substrate. At this, so-called " suspending ", refers toFin and substrate are separated. Note, the interval between fin and substrate can be by other materials (for example,Separation layer) fill. Fin can comprise high mobility semiconductor material, to improve device performance.At this, so-called " high mobility " refers to respect to the mobility of silicon (Si) and wants high. Gao QianThe rate semi-conducting material of moving is Ge, SiGe or III-V compound semiconductor etc. such as.
Fin can be (for example, extension) on the first semiconductor layer separating with substrate on substrateSecond half conductor layer forming. The first semiconductor layer can be fin-shaped, and suspends with respect to substrate.So this second half conductor layer can form around the periphery of the first semiconductor layer at least in part,Thereby be also fin-shaped and subsequently can be as the fin of device. At this, so-called " partly around ",Refer to along the direction extending longitudinally of the first semiconductor layer and can have a scope, within the scope of this,This second half conductor layer can be sealed the outer surface of the first semiconductor layer completely. Also, at this modelIn enclosing, on the cross section vertical with the direction extending longitudinally of the first semiconductor layer, this second half leadIt is (for example, corresponding with the cross sectional shape of the first semiconductor layer that body layer can form closed patternRectangle, polygon etc.). The first semiconductor layer can be relatively thin, and (for example, thickness is for approximately3～20nm), and suspend with respect to substrate. Like this, in growth course the first semiconductor layer andStress in this second half conductor layer can be able to relaxation, and therefore can suppress or avoidIn semi-conductor layer or this second half conductor layer, produce defect.
According to embodiment, at least partly can shape around the Part I periphery of the first semiconductor layerBecome the second semiconductor layer, and at least partly can around the Part II periphery of the first semiconductor layerForm the 3rd semiconductor layer. Like this, the second semiconductor layer can be used as the fin of the first device, andThe 3rd semiconductor layer can be as the fin of the second device. The first device can be N-shaped device asNFinFET, the second device can be that p-type device is as pFinFET; Vice versa. So, carrySupply a kind of CMOS configuration.
The first device and the second device can be isolated from each other. For example, can be formed with dielectric layer,So that the Part I of the first semiconductor layer and Part II are separated. This dielectric layer can along withThe crossing direction of the direction extending longitudinally of the first semiconductor layer is extended, and can be further just theTwo semiconductor layers and the 3rd semiconductor layer separate. The Part I of the first semiconductor layer except with thisOutside the side that dielectric layer joins, remaining surface all can be covered by the second semiconductor layer. SimilarGround, the Part II of the first semiconductor layer except the side joining with this dielectric layer, itsRemaining surface all can be covered by the 3rd semiconductor layer.
On substrate, can be formed with separation layer, in order to the grid heap superimposition substrate of electrical isolation device. EveryAbsciss layer can be filled the space between first, second, and third semiconductor layer and substrate, and few portionPoint ground exposes second and the 3rd semiconductor layer. For example, below the second semiconductor layer, separation layerCan join with the second semiconductor layer, below the 3rd semiconductor layer, separation layer can be with secondSemiconductor layer joins, and in all the other positions, the end face of separation layer can be than second, third partlyElectrode conductor layer will be near substrate to the bottom surface of substrate. Second and/or the 3rd below semiconductor layer,Separation layer can have undercutting. Like this, grid are stacking can be embedded in this undercutting, thereby canThe effectively bottom of control gate.
This semiconductor devices for example can be made as follows. Particularly, can on substrate, formFin structure. Subsequently, when remove this fin structure near the part (" bottom ") of substrate withWhile obtaining the first semiconductor layer, the first semiconductor layer can suspend with respect to substrate.
In order to form respectively the second semiconductor layer and the 3 half around the first semiconductor layer as mentioned aboveConductor layer, the part that can first cover fin structure, to expose fin-shaped at the first device areaAnother part of structure. So, at the first device area, for the fin structure part of exposing,Can remove its underpart, thereby form the Part I of the first semiconductor layer. At the first device regionTerritory, due to the removal of fin structure bottom, the Part I of the first semiconductor layer is with respect to substrateSuspend. Now, the support that the fin structure part of crested can be served as this mounting structure.
Because thereby expose on the Part I of the first semiconductor layer its surface that suspends, can show at itSecond semiconductor layer of growing on face. So, in the situation that fully growing, the second semiconductor layerCan cover all surface that the Part I of the first semiconductor layer exposes. This second semiconductorLayer can equally be fin-shaped with the first semiconductor layer, and can serve as subsequently the fin of the first device.
Afterwards, can cover the first device area, and expose fin structure at the second device area(for example,, by removing before in order to cover the shielding layer of this part fin structure). At the second devicePart region can similarly be processed. Particularly, at the second device area, for what exposeFin structure part, can remove its underpart, thereby forms the Part II of the first semiconductor layer.At the second device area, due to the removal of fin structure bottom, second of the first semiconductor layerDivide and suspend with respect to substrate. Now, the layer structure forming in the first device area of crested canTo serve as the support of this mounting structure.
Because thereby expose on the Part II of the first semiconductor layer its surface that suspends, can show at itGrowth regulation three semiconductor layers on face. So, in the situation that fully growing, the 3rd semiconductor layerCan cover all surface that the Part II of the first semiconductor layer exposes. This second semiconductorLayer can equally be fin-shaped with the first semiconductor layer, and can serve as subsequently the fin of the second device.
For the ease of removing the bottom of fin structure, fin structure can be included on substrate successivelyThe sacrifice layer forming and the lamination of the first semiconductor layer. For example, can on substrate, form successivelySacrifice layer and the first semiconductor layer, then can be patterned into fin by the first semiconductor layer and sacrifice layerShape structure. Can proceed in substrate in this pattern step, thus on substrate with fin structureCorresponding position can have projection. Subsequently, can selective removal sacrifice layer.
Taking fin as basis, can there is various ways to complete the manufacture of device. For example, Ke YiOn substrate, form separation layer, and on separation layer form respectively with the second semiconductor layer and the 3 halfThe first grid heap superimposition second gate stack that conductor layer is crossing. Separation layer can be filled the first semiconductorSpace between layer, the second semiconductor layer, the 3rd semiconductor layer and substrate, and at least in partExpose the second semiconductor layer, the 3rd semiconductor layer. Separation layer can be by deposit dielectric as oxygenCompound also eat-backs to obtain. Separation layer can be eat-back for making below the second semiconductor layer,Separation layer and the second semiconductor layer join, below the 3rd semiconductor layer, and separation layer and the 3 halfConductor layer joins, and in all the other positions, the end face of separation layer is than the second semiconductor layer the 3 halfElectrode conductor layer will be near substrate to the bottom surface of substrate. In addition, in the time eat-backing, can second and/Or the 3rd semiconductor layer below form undercutting.
Can between the first device area and the second device area, form dielectric layer, with byPart I and the Part II of semi-conductor layer are isolated, and by the second semiconductor layer and the 3rdSemiconductor layer is isolated. Like this, the first device and the second device can be isolated from each other.
The stacking formation of separation layer and grid can be carried out respectively in each device area. For example, existWhen the first device area is processed, can and cover after forming the second semiconductor layerBefore the first device area, form the Part I of separation layer, and at the Part I of separation layerThe upper formation first grid is stacking. Similarly, in the time that the second device area is processed, Ke YiAfter forming the 3rd semiconductor layer, form the Part II of separation layer, and at second of separation layerIn part, form second gate stack.
In this case, cover the first device area and can comprise that formation shielding layer is to cover firstThe end face of device area and side. After forming second gate stack, can be by for example flatSmoothization, removes the shielding layer part on the first interval region end face. Then, can selectively goExcept the shielding layer part on the first device area side. So, the first device area and secondBetween device area, form space (originally by the shielding layer part on the first device area sideThe position occupying). Can be via this space, selective etch fin structure, thus make firstThe Part I of semiconductor layer and Part II disconnect. In addition, can be at the first device areaWith second form dielectric layer between device area, thereby by the Part I of the first semiconductor layerIsolated with Part II, and by isolated to the second semiconductor layer and the 3rd semiconductor layer.
The disclosure can present by various forms, below will describe some of them example.
As shown in Figure 1, provide substrate 1001. This substrate 1001 can be various forms of liningsThe end, such as but not limited to bulk semiconductor material substrate as body Si substrate etc. In the following description,For convenience of description, be described as an example of body Si substrate example. Particularly, substrate 1001 can beSilicon single crystal body, its surface can be for example (110) crystal face, (100) crystal face or (112) crystalline substanceFace.
On substrate 1001, for example, by epitaxial growth, form successively sacrifice layer 1003 andSemi-conductor layer 1005. Sacrifice layer 1003 can comprise and substrate 1001 and the first semiconductor layer1005 different semi-conducting materials, as SiGe (atomic percent of Ge is for example approximately 5～20%),Thickness is about 10～100nm. The first semiconductor layer 1005 can comprise suitable semi-conducting material,For example Si, thickness is about 10～100nm.
Subsequently, can (can to the first semiconductor layer 1005 and the sacrifice layer 1003 of formation like thisSelection of land, also has substrate) carry out composition, to form fin structure. For example, this can enter as followsOK.
Particularly, can on the first semiconductor layer 1005, form hard mask layer. In this exampleIn, hard mask layer can comprise oxide (for example, silica) layer 1007 and polycrystalline Si layer1009. For example, the thickness of oxide skin(coating) 1007 is about 2～10nm, polycrystalline Si layer 1009Thickness is about 50～120nm. In this example, utilize figure transfer techniques, by hard maskBe patterned into fin-shaped. For this reason, can on hard mask layer, form composition (for example, by exposure,Develop) photoresist PR. At this, extend perpendicular to paper direction on the patterned edge of photoresist PRStrip, and its width (dimension in figure in horizontal direction) can be roughly corresponding to two finsSpacing between shape structure.
Then, as shown in Figure 2, taking this photoresist PR as mask, to polycrystalline Si layer 1009(with respect to oxide layer 1007) carries out selective etch as reactive ion etching (RIE). Like this,Polycrystalline Si layer 1009 can be patterned into the strip corresponding with photoresist PR. Then, asShown in Fig. 3 (a), remove photoresist PR, and form side wall on the sidewall of polycrystalline Si layer 1009(spacer) 1011. This area exists multiple means to form side wall. For example, can pass throughFor example, as roughly conformal deposition one deck nitride (, silicon nitride) of atomic layer deposition (ALD),Thickness is for example about 3～20nm, then the nitride of deposit is carried out to selective etch as RIE,Remove its laterally extending part, vertical extension is retained, to form side wall 1011. SideWall 1011 covers the sidewall of polycrystalline Si layer 1009.
Fig. 3 (b) shows the top view of structure shown in Fig. 3 (a). Note, although in Fig. 3 (b)Not shown, but on the sidewall at the two ends up and down of strip polycrystalline Si layer 1009, also there is sideWall 1011, thus side wall 1011 forms closed pattern around the periphery of strip polycrystalline Si layer 1009.
In order to obtain the mask of fin-shaped, as Fig. 4 (a) and 4 (b), (Fig. 4 (a) is top view, 4 (b)The sectional view along AA ' line in Fig. 4 (a)) shown in, can selective removal polycrystalline Si layer 1009(for example, by TMAH solution), and then the photoresist 1013 of formation composition. Photoresist1013 can cover the middle part of side wall 1011, and expose the part of side wall both sides Shang Xia 1011.Taking this photoresist 1013 as mask, side wall 1011 is carried out to selective etch as RIE, therebyOriginally the side wall 1011 that is closed pattern can be separated into two parts, as shown in Figure 5. EachPart is corresponding to the fin structure that will form, in this example for to prolong along the vertical direction in figureThe strip of stretching.
Then, as shown in Figure 6, taking side wall 1011 as mask, can be successively to oxide skin(coating)1007, the first semiconductor layer 1005 and sacrifice layer 1003 carry out selective etch as RIE. ThisSample, in the layer of below, obtains fin structure by the design transfer of side wall 1011. Therefore,The width (dimension of horizontal direction in figure) of semi-conductor layer 1005 and the width of side wall 1011Roughly the same (for example, approximately 3～20nm). At this, further selective etch substrate1001. Therefore,, in the position corresponding with fin structure, on substrate 1001, can have prominentRise. The projection of fin structure on substrate is roughly positioned at the middle part of this projection. Due to the spy of etchingProperty, the sacrifice layer 1003 after etching and the projection of substrate 1001 can be from top to bottom graduallyBecome large shape. Afterwards, can selective removal side wall 1011 (can also be further selectiveRemove oxide skin(coating) 1007).
Although utilizing above figure transfer techniques to form fin structure, the disclosure is not limitIn this. For example, can directly on the first semiconductor layer 1005, form the photoresist of fin-shaped, andTaking photoresist as mask, selective etch the first semiconductor layer 1005, sacrifice layer 1003 and liningThe end 1001,, to form fin structure. Or, also can on hard mask layer, directly form fin-shapedPhotoresist, utilize photoresist that hard mask is patterned into fin-shaped, and utilize the hard mask of fin-shaped to comply withInferior selective etch the first semiconductor layer 1005, sacrifice layer 1003 and substrate 1001, to formFin structure.
In this fin structure, in the time that substrate surface is (110) crystal face, the first semiconductor layer1005 bearing of trend can be parallel to (110) crystal face and (1-11) crystal face cross spider or(110) crystal face and (1-1-1) cross spider or (110) crystal face and (111) crystal face of crystal faceCross spider, the side of the first semiconductor layer 1005 can be roughly parallel to (111) family of crystal planes;Or in the situation that substrate surface is (112) crystal face, the extension side of the first semiconductor layer 1005To can be parallel to the cross spider of (112) crystal face and (1-11) crystal face or (112) crystal face with(11-1) cross spider of crystal face, the side of the first semiconductor layer 1005 also can be roughly parallel to(111) family of crystal planes. Or the bearing of trend of the first semiconductor layer 1005 can be corresponding to < 110 > direction, in the situation that substrate surface is (100) crystal face, the first semiconductor layer 1005Side can be roughly parallel to (110) crystal face. These crystal faces are easy to reduce growth defect.
At this, show two fin structures. But the disclosure is not limited to this, for example canForm more or less fin structure. In addition, the layout of fin structure can be according to device needTo differently design.
Afterwards, can cover a part (for example, Lower Half as shown in Figure 8) for fin structure,For example, to expose fin structure at the first device area (, upper half area) as shown in Figure 8.Particularly, as shown in Figure 7, can on the substrate that is formed with fin structure, for example, pass through ALD,In roughly conformal mode, deposited oxide layer 1015 and nitride layer 1017. Oxide skin(coating)1015 thickness can be about 1～10nm, and the thickness of nitride layer 1017 can be for approximately2～15nm. Afterwards, as shown in the top view in Fig. 8, can be in the structure shown in Fig. 7 shapeBecome the photoresist 1019 of composition. This photoresist 1019 is patterned to second that covers fin structurePortion's (corresponding to the second device area), and extend along the horizontal direction in figure. Here it may be noted that, in the top view of Fig. 8, only for simplicity, and not shown nitride layer 1017The pattern rising and falling with fin structure on substrate, below so same in top view.
Subsequently, as Fig. 9 (a), 9 (b) and 9 (c), (Fig. 9 (a) is top view, and Fig. 9 (b) is along figureThe sectional view of AA ' line in 9 (a), Fig. 9 (c) is the sectional view along A1A1 ' line in Fig. 9 (a)) shown in,Taking photoresist 1019 as mask, for example, select by RIE (with respect to oxide skin(coating) 1015)Property remove nitride layer 1017. Like this, as shown in Fig. 9 (a) and 9 (b), at the first device areaIn, nitride layer 1017 is removed; And in the second device area, as Fig. 9 (a) and 9 (c)Shown in, nitride layer 1017 is retained on fin structure. Like this, nitride layer 1017 is by finShape structure is connected physically with substrate 1001, and therefore can support fin structure (particularlyAfter removal sacrifice layer 1003 as described below). Afterwards, can remove photoresist 1019.
In this embodiment, formed the covering of laminated construction of oxide skin(coating) and nitride layerLayer. But the disclosure is not limited to this. Shielding layer can comprise various suitable dielectric substances,Supporting layer even can also comprise semi-conducting material or conductive material.
Afterwards, as Figure 10 (a) and 10 (b), (Figure 10 (a) is corresponding to the sectional view in Fig. 9 (b), figure10 (b) are corresponding to the sectional view in Fig. 9 (c)) shown in, can pass through for example RIE, (with respect toThe sacrifice layer of the substrate 1001 of Si material and the first semiconductor layer 1005 and SiGe material1003), selective removal oxide skin(coating) 1015. As shown in Figure 10 (a) and 10 (b), firstIn device area, expose fin structure completely; And in the second device area, oxide skin(coating)1015 are nitrided thing layer 1017 covers, and can be retained.
So fin structure exposes in the first device area, and in the second device area quiltCover.
Then, as Figure 11 (a) and 11 (b) (corresponding respectively to the sectional view of Figure 10 (a) and 10 (b))Shown in, at the first device area, can pass through for example wet etching, (with respect to Si materialSubstrate 1001 and the first semiconductor layer 1005) selective removal sacrifice layer 1003. Like this, existIn the first device area, between the first semiconductor layer 1005 of fin-shaped and substrate 1001, formInterval 1021.
At this, can control the amount of etching, make as shown in Figure 11 (b), at the second device areaIn, sacrifice layer 1003 is not removed. Like this, by the layer structure in the second device area(1003,1005,1015,1017), can effectively support in the first device region unsettled firstSemiconductor layer 1005. Certainly, even if this partial sacrifice layer by part or even completely remove, byIn the existence of shielding layer (1015,1017), unsettled the first semiconductor layer in the first device regionAlso can be supported.
In above example, shielding layer, except nitride layer 1017, also comprises oxideLayer 1015, but the disclosure is not limited to this. For example, in the operation of describing in conjunction with Fig. 7 above,Can not form oxide skin(coating) 1015, and directly form nitride layer 1017. Like this, equally canTo carry out successor operation by the mode of describing in conjunction with Fig. 8-11 (b) above. Certainly, also can in support portionTo be other dielectric substances or laminated construction.
In addition,, in above example, for two fin structures, all covered they secondPortion. But the disclosure is not limited to this. For example, for a fin structure, can cover under itHalf portion; And for another fin structure, can cover its first half. This can be according to designedDevice layout and determine.
Then, as shown in Figure 12 (corresponding to the sectional view of Figure 11 (a)), at the first device regionIn territory, second semiconductor layer 1023 of can growing on the first semiconductor layer 1005. At this,The second semiconductor layer 1023 can comprise high mobility material, for example Ge, SiGe or III-VCompound semiconductor as InSb, InGaSb, InAs, GaAs, InGaAs, AlSb, InP,III-nitrides etc., thickness can be about 5～15nm. At compound semiconductor as the feelings of SiGeUnder condition, its composition (for example, Ge atomic percent) can gradual change, for example makes from firstThe lattice paprmeter of semiconductor layer 1005 (at this, Si) differs less and becomes and the first semiconductor layer1005 lattice paprmeter differs larger, to suppress the generation of dislocation or defect. The second semiconductorLayer 1023 side can with substrate in (111) family of crystal planes or (110) family of crystal planes roughly flatOK.
This growth can be selective growth, thereby 1023 of the second semiconductor layers are partly being ledOn the surface of first semiconductor layer 1005 (and substrate 1001) of body material, grow. Can controlMake the growth of the second semiconductor layer 1023, make it not fill up the first semiconductor layer 1005 completelyAnd the interval 1021 between substrate 1001. Due to the structure that suspends of the first semiconductor layer 1005,Stress in growth course in the first semiconductor layer 1005 and the second semiconductor layer 1023 canBe able to relaxation. Like this, can suppress or avoid the first semiconductor layer 1005 or the second semiconductor layerIn 1023, produce defect, this contribute to improve device performance (for example, reduce OFF leakage current withAnd lifting ON state current).
In this example, the surface that the first semiconductor layer 1005 exposes is all by the second semiconductor layer1023 cover. Certainly, on the surface of substrate 1001, also can grow and have the second semiconductor layer 1023.
In this example, the side whole extending longitudinally of the first semiconductor layer 1005 exposed portions serveTo, the second semiconductor layer 1023 is sealed the periphery of the first semiconductor layer 1005 completely. At this,So-called " direction extending longitudinally " refer to the first semiconductor layer length direction (in Figure 12 perpendicular toThe direction of paper), substantially consistent with the length direction of the channel region forming afterwards. Like this, existThe cross section vertical with the direction extending longitudinally of the first semiconductor layer 1005 is (, shown in Figure 12Cross section) upper, the second semiconductor layer 1023 forms closed pattern (being rectangle in this example). WhenSo, this closed pattern is determined at the pattern of this section by the first semiconductor layer 1005, Ke YiweiSuch as polygon of other shapes.
So the second semiconductor layer 1023 of shape can serve as the fin of device subsequently.
After forming fin 1023 by above-mentioned processing, can form the grid crossing with fin stacking,And form device (for example, FinFET).
For isolated gate heap superimposition substrate, as Figure 13 (a) and 13 (b) (correspond respectively to Figure 11 (a)Sectional view with 11 (b)) on substrate 1001 (in this example, in the first device area,On the second semiconductor layer 1023 forming on substrate 1001; And in the second device area,On nitride layer 1017) first form separation layer 1025. This separation layer for example can lead toCross on substrate deposit dielectric material as oxide, and then eat-back to form. ReturningIn erosion process, control and eat-back the degree of depth, the separation layer 1025 obtaining can be revealed at least in partGo out the second semiconductor layer 1023. In addition, separation layer 1025 has also been filled interval 1021. At thisIn example, below the second semiconductor layer 1023, separation layer 1025 and the second semiconductor layer 1023Join; And in all the other positions, the end face of separation layer 1025 is than the second semiconductor aspect 1023Bottom surface low. In addition, below the second semiconductor layer 1023, separation layer 1025 can shapeBecome to have undercutting (causing owing to eat-backing).
In this embodiment, separation layer 1025 substantially filled up the first semiconductor layer 1005,Space between the second semiconductor layer 1023 and substrate 1001. But the disclosure is not limited to this.For example, the end face of separation layer 1025 can depart from the bottom surface of the second semiconductor layer 1023.
Subsequently, the grid crossing with fin can be formed on separation layer 1025 stacking. For example, thisCan carry out as follows. Particularly, as Figure 14 (a) and 14 (b) (correspond respectively to Figure 13 (a) and 13 (b)Sectional view) shown in, can form successively gate dielectric layer 1027 and grid conductor layer 1029. ExampleAs, gate dielectric layer 1027 can comprise that thickness is oxide (for example, the SiO of approximately 0.3～2nm2Or GeO2), grid conductor layer 1029 can comprise polysilicon; Or gate dielectric layer 1027 canTo comprise that thickness is as the high-K gate dielectric of about 1～4nm is as HfO2Or Al2O3, grid conductor layer 1029Can comprise metal gate conductor. The in the situation that of high-K gate dielectric/metal gate conductor, at gate mediumBetween layer 1027 and grid conductor layer 1029, can also form work function regulating course (not shown), exampleAs TiN, Al, Ti, TiAlC, thickness is about 1～3nm.
In this example, only for the purpose of diagram is convenient, by corresponding two of left and right fin difference twoThe grid of device are stacking is depicted as identical configuration and one is extended, but the disclosure is not limited to this. DevicePart can have different grid stack arrangement, and grid are separately stacking can be according to device layoutAnd carry out composition.
After formation grid are stacking, for example can be stacked as mask by grid, carry out haloing (halo)Inject and extension area (extension) injection. Next, can be on the stacking sidewall of grid shapeBecome grid side wall. Then, can grid stacking and grid side wall be mask, carry out source/leakage (S/D) noteEnter. Subsequently, can, by annealing, activate the ion injecting, to form source/drain region.
Those skilled in the art will know that various ways taking fin as basis make device, this forForming fin technique afterwards repeats no more.
After forming device as mentioned above in the first device area, can locate similarlyReason, to form another device in the second device area. For example, this can be by covering firstCurrent structure in device area (for example, obtain as mentioned above comprise that fin and grid are stacked inDevice), and expose the fin structure in the second device area, same to the fin structure exposingCarry out above-mentioned processing, thereby form another device at the second device area.
Particularly, as Figure 15 (a), 15 (b) and 15 (c), (Figure 15 (a) is top view, Figure 15 (b)Be the sectional view along AA ' line in Figure 15 (a), Figure 15 (c) is cutting along A1A1 ' line in Figure 15 (a)Face figure) shown in, in the structure shown in Figure 14 (a) and 14 (b), for example form nitrogenize by depositThing layer 1031. For example, the thickness of nitride layer can be about 30～70nm, and is preferably more thanThe height of fin structure. Then, can on nitride layer 1031, form the photoresist of composition1033. At this, photoresist 1033 is patterned to and exposes the second device area (in Figure 15 (a)Half area), and cover the first device area (upper half area in Figure 15 (a)).
Subsequently, as shown in Figure 16 (corresponding to the sectional view in Figure 15 (c)), can be secondIn device area, expose fin structure. Particularly, successively selective etch as RIE nitrogenizeThing layer 1031, grid conductor layer 1029 (for example, polysilicon), gate dielectric layer 1027 are (for example,Oxide), separation layer 1025 (for example, oxide; At gate dielectric layer 1027 and separation layer 1025Be in the situation of oxide, can in same step, remove gate dielectric layer 1027 and separation layer1025), nitride layer 1017. After selective etch nitride layer 1031, can removePhotoresist 1033.
Like this, in the second device area, fin structure exposes (by further selectionProperty remove oxide skin(coating) 1015). Afterwards, can be described above, in the second device area,The bottom (in this example, sacrifice layer 1003) of selective removal fin structure, thenSelective generation the 3rd semiconductor layer on the surface of semi-conductor layer 1005, and lead with the 3 halfBody layer is as fin, by for example forming as mentioned above stacking another device that forms of separation layer and grid.
The second semiconductor layer and the 3rd semiconductor layer can comprise identical or different material. ThisOutward, the 3rd semiconductor layer can be formed as the thickness roughly the same with the second semiconductor layer. Due toThe first semiconductor layer periphery that they all extend around one forms, therefore the second semiconductor layer and theThree semiconductor layers rough alignment and joining each other. Thereby at the first device area and the second deviceThe device that part region forms respectively can be connected to each other.
Certainly, also these two devices can be isolated from each other. For example, can be at the first device regionBorder (for example, the horizontal central line in Figure 15 (a)) both sides (example between territory and the second device areaAs, upper and lower both sides in Figure 15 (a)) in certain limit, by selective etch, by active layer (exampleAs, the first semiconductor layer, the second semiconductor layer, the 3rd semiconductor layer) and also will alternativelyOther layer cut off, and in the space causing thus filling dielectric layer, thereby by the first deviceThe device forming in region and the second device area is isolated from each other.
At this, for the ease of this isolation, can form and be self-aligned to the first device area andMask between two device areas. Particularly, as Figure 17 (a), 17 (b), 17 (c) and 17 (d) (figure17 (a) are top views, and Figure 17 (b) is that Figure 17 (c) is edge along the sectional view of AA ' line in Figure 17 (a)The sectional view of A1A1 ' line in Figure 17 (a), Figure 17 (d) is the sectional view along BB ' line in Figure 17 (a))Shown in, can be in the first device area the sidewall (midline position in Figure 17 (a) of current layer structurePlace is towards the sidewall of below, or in Figure 17 (d) right side layer structure 1023,1025,1027,1029,1031 sidewalls towards left side) the upper side wall 1035 that forms. As mentioned above, side wall canBy roughly conformal deposition one deck nitride of ALD, thickness is for example about 2～10nm, then rightThe nitride of deposit carries out selective etch as RIE, removes its laterally extending part, makes to erectStraight extension retains to form. As shown in Figure 17 (a) and 17 (d), because side wall 1035 is alongOne device area forms towards the sidewall of the second device area, thereby is self-aligned to the first device regionBorder between territory and the second device area.
In the first device area, due to the nitride layer 1031 existing before, thereby top stillCan retain a part of nitride layer 1031. So, nitride layer 1031 and side wall 1,035 oneRise and formed shielding layer, not only covered the top of the first device area middle level structure, but alsoCover the sidewall of the first device area middle level structure (towards the second device area).
Formed as mentioned above cover the first device area shielding layer (1031,1035) itAfter, in the second device area, can pass through for example RIE, (with respect to the substrate of Si material1001 and first semiconductor layer 1005, the sacrifice layer 1003 of SiGe material and the screening of nitrideCover layer), selective removal oxide skin(coating) 1015. Like this, in the second device area, completelyExpose fin structure.
Then,, as Figure 18 (corresponding to the sectional view in Figure 17 (c)), can pass through for example wet methodCorrosion, (with respect to substrate 1001 and first semiconductor layer 1005 of Si material) selectively goesExcept sacrifice layer 1003. Like this, in the second device area, at the first semiconductor layer 1005 of fin-shapedAnd between substrate 1001, form interval 1037. Due to the existence of side wall 1035, this corrosion baseIn basis, can not affect the first device area. Due to the established layer of industry in the first device area structure,The first semiconductor layer unsettled in the second device area can effectively be supported.
Then, as shown in Figure 19 (corresponding to the sectional view of Figure 18), at the second device areaIn, can be on the first semiconductor layer 1005 growth regulation three semiconductor layers 1039. At this, theThree semiconductor layers 1039 can comprise high mobility material, for example Ge, SiGe or III-V familyCompound semiconductor as InSb, InGaSb, InAs, GaAs, InGaAs, AlSb, InP,III-nitrides etc., thickness can be about 5～15nm. At compound semiconductor as the feelings of SiGeUnder condition, its composition (for example, Ge atomic percent) can gradual change, for example makes from firstThe lattice paprmeter of semiconductor layer 1005 (at this, Si) differs less and becomes and the first semiconductor layer1005 lattice paprmeter differs larger, to suppress the generation of dislocation or defect. The 3rd semiconductorLayer 1039 side can with substrate in (111) family of crystal planes or (110) family of crystal planes roughly flatOK.
The material of the 3rd semiconductor layer 1039 can be identical with the material of the second semiconductor layer 1023Or different, their thickness also can be identical or different. Particularly, the first device area shapeBecome N-shaped device (or p-type device) and form p-type device (or N-shaped at the second device areaDevice) time, the second semiconductor layer 1023 and the 3rd semiconductor layer 1039 can be respectively for nType device (or p-type device), p-type device (or N-shaped device) are configured and optimize.
This growth can be selective growth, thereby 1039 of the 3rd semiconductor layers are partly being ledOn the surface of first semiconductor layer 1005 (and substrate 1001) of body material, grow. Can controlMake the growth of the 3rd semiconductor layer 1039, make it not fill up the first semiconductor layer 1005 completelyAnd the interval 1037 between substrate 1001. Due to the structure that suspends of the first semiconductor layer 1005,Stress in growth course in the first semiconductor layer 1005 and the 3rd semiconductor layer 1039 canBe able to relaxation. Like this, can suppress or avoid the first semiconductor layer 1005 or the 3rd semiconductor layerIn 1093, produce defect, this contribute to improve device performance (for example, reduce OFF leakage current withAnd lifting ON state current).
In this example, the surface that the first semiconductor layer 1005 exposes is all by the 3rd semiconductor layer1039 cover. Certainly, on the surface of substrate 1001, also can grow and have the 3rd semiconductor layer 1039.
In this example, the side whole extending longitudinally of the first semiconductor layer 1005 exposed portions serveTo, the 3rd semiconductor layer 1039 is sealed the periphery of the first semiconductor layer 1005 completely. Like this,In the cross section vertical with the direction extending longitudinally of the first semiconductor layer 1005 (, shown in Figure 19Cross section) upper, the 3rd semiconductor layer 1039 forms closed pattern (being rectangle in this example).Certainly, this closed pattern is determined at the pattern of this section by the first semiconductor layer 1005, canFor such as polygon of other shapes.
So the 3rd semiconductor layer 1039 of shape can serve as the fin of device subsequently.
After forming fin 1039 by above-mentioned processing, can form the grid crossing with fin stacking,And form device (for example, FinFET).
For example, as Figure 20 (a), 20 (b) and 20 (c) (correspond respectively to Figure 17 (b), 17 (c) andThe sectional view of 17 (d)) shown in, for isolated gate heap superimposition substrate, on substrate 1001 (In this example, in the second device area, the 3rd semiconductor layer forming on substrate 1001On 1039) first form separation layer 1041. This separation layer for example can be by forming sediment on substrateAmass dielectric substance as oxide, and then eat-back to form. In etch back process, controlSystem is eat-back the degree of depth, makes the separation layer 1041 obtaining can expose at least in part the 3rd semiconductorLayer 1039. In addition, separation layer 1041 has also been filled interval 1037. In this example,Three semiconductor layer 1039 belows, separation layer 1041 and the second semiconductor layer 1039 join; AndAll the other positions, the end face of separation layer 1041 is lower than the bottom surface of the 3rd semiconductor aspect 1039.In addition, below the 3rd semiconductor layer 1039, separation layer 1041 can be formed with undercutting (byCause in eat-backing).
In this embodiment, separation layer 1041 substantially filled up the first semiconductor layer 1005,Space between the 3rd semiconductor layer 1039 and substrate 1001. But the disclosure is not limited to this.For example, the end face of separation layer 1041 can depart from the bottom surface of the 3rd semiconductor layer 1039. SeparatelyOutward, the thickness of separation layer 1041 can with roughly phase of the thickness of the separation layer of previous formation 1025With.
Subsequently, the grid crossing with fin can be formed on separation layer 1041 stacking. For example, asShown in Figure 20 (b), can form successively gate dielectric layer 1043 and grid conductor layer 1045. For example,Gate dielectric layer 1043 can comprise that thickness is oxide (for example, the SiO of approximately 0.3～2nm2OrGeO2), grid conductor layer 1045 can comprise polysilicon; Or gate dielectric layer 1043 canComprise that thickness is that the high-K gate dielectric of approximately 1～4nm is as HfO2Or Al2O3, grid conductor layer 1045Can comprise metal gate conductor. The in the situation that of high-K gate dielectric/metal gate conductor, at gate mediumBetween layer 1043 and grid conductor layer 1045, can also form work function regulating course (not shown), exampleAs TiN, Al, Ti, TiAlC, thickness is about 1～3nm. The grid of the first device area stacking (1027,1029) grid stacking (1043,1045) of and the second device area can be identical or different. SpecialNot, at the first device area formation N-shaped device (or p-type device) and at the second device regionTerritory forms p-type device when (or N-shaped device), the grid of the first device area stacking (1027,1029) grid stacking (1043,1045) of and the second device area can be respectively for N-shaped devicePart (or p-type device), p-type device (or N-shaped device) are configured and optimize.
In this example, only for the purpose of diagram is convenient, by corresponding two of left and right fin difference twoThe grid of device are stacking is depicted as identical configuration and one is extended, but the disclosure is not limited to this. DevicePart can have different grid stack arrangement, and grid are separately stacking can be according to device layoutAnd carry out composition.
After formation grid are stacking, for example can be stacked as mask by grid, carry out haloing (halo)Inject and extension area (extension) injection. Next, can be on the stacking sidewall of grid shapeBecome grid side wall. Then, can grid stacking and grid side wall be mask, carry out source/leakage (S/D) noteEnter. Subsequently, can, by annealing, activate the ion injecting, to form source/drain region.
Those skilled in the art will know that various ways taking fin as basis make device, this forForming fin technique afterwards repeats no more.
Like this, just in the first device area and the second device area, form device respectively. WithAfter, can as mentioned above these two devices be isolated.
Particularly, can carry out for example chemically mechanical polishing of planarization (CMP), to goExcept the nitride layer 1031 at the first device area top place, as shown in Figure 20 (a). Like this, asShown in Figure 20 (c), the side wall 1035 between the first device area and the second device area exposes.
Then, as shown in figure 21, can pass through for example RIE, the side of selective removal nitrideWall 1035. So, between the first device area and the second device area, formed space. WarpBy this space, can pass through for example RIE, selective removal oxide skin(coating) 1015, and furtherSelective removal fin structure (the first semiconductor layer 1005, sacrifice layer 1003), like this, justSeparate the device forming respectively in the first device area and the second device area. Then, as figureShown in 22, can in this space, form dielectric layer 1047, for example oxide, so that isolationThese two devices.
It is pointed out that the composition stacking for grid at this, can form dielectric layerAfter 1047, carry out. Also, gate dielectric layer 1027 and grid conductor layer 1029 can cover wholeThe first device area, similarly gate dielectric layer 1043 and grid conductor layer 1045 can cover wholeThe second device area. After forming dielectric layer, by gate dielectric layer 1027 and grid conductor layer1029 are patterned into the grid crossing with fin 1023 stacking (for example, strip), and by gate dielectric layer 1043Be patterned into the grid crossing with fin 1039 stacking (for example, strip) with grid conductor layer 1045.
Like this, just obtain the semiconductor devices of this embodiment. As Figure 20 (a), 20 (b) and 22Shown in, this semiconductor devices can comprise the first semiconductor layer 1005 separating with substrate 1001And based on this and at the first device of the first device area formation and the second device area shapeThe second device becoming. The first device area can comprise the First around the first semiconductor layer 1005Point periphery and the second semiconductor layer 1023 of forming, serve as the fin of this first device. The second deviceRegion can comprise form around the Part II periphery of the first semiconductor layer 1005 the 3 halfConductor layer 1039, serves as the fin of this second device. In addition, this device also comprise separation layer (1025,1041) and the first grid crossing with fin 1023 forming on separation layer stacking (1027,1029) and the second gate stack crossing with fin 1039 (1043,1045). Due to separation layerThe undercutting of (1025,1041), grid are stacking can be embedded in this undercutting, thereby can more haveThe bottom of fin is controlled on effect ground. Dielectric layer 1047 is positioned at the first device area and the second device areaBetween, for example, extend along the direction of crossing with the vertical bearing of trend of fin (, substantially vertical),Thereby two devices are isolated from each other.
In above embodiment, in the first device area and the second device area, form respectivelySeparation layer also then forms gate dielectric layer and grid conductor layer on separation layer. But the disclosure is notBe limited to this. Can form separation layer together with the second device area for the first device area. ExampleAs, after second semiconductor layer 1023 of growing as shown in figure 12, replace and form separation layer1025, gate dielectric layer 1027 and grid conductor layer 1029 can form the first oxidation on substrateThing layer (thickness is enough to fill the gap between fin structure, and can planarization), and firstOn oxide skin(coating), form nitride layer. Afterwards, can utilize photoresist (for example, 1033) to hideCover the first device area, and expose the fin structure of the second device area by selective etch.At the second device area, can remove the bottom of fin structure, then growth regulation three semiconductor layers.These operations can be similar to the description of above combination Figure 15 (a)-19. Afterwards, can be furtherForm the second oxide skin(coating). Then, can carry out such as CMP of planarization. To the second oxygenThe CMP of compound layer can stop at nitride layer, and then nitride layer is carried out to CMP.Can stop at the first oxide skin(coating) to the CMP of nitride layer. Now, the first device areaIn the first oxide skin(coating) and the second oxide skin(coating) in the second device area roughly with high, canThey are eat-back, to form separation layer. Afterwards, can on separation layer, form gate mediumLayer and grid conductor layer, and it is stacking that they are patterned into corresponding grid.
Can be applied to various electronic equipments according to the semiconductor devices of disclosure embodiment. ExampleAs, for example, by integrated multiple such semiconductor devices and other devices (, other formsTransistor etc.), can form integrated circuit (IC), and build electronic equipment thus. Therefore,The disclosure also provides a kind of electronic equipment that comprises above-mentioned semiconductor device. Electronic equipment also canTo comprise the display screen coordinating with integrated circuit and the wireless transceiver coordinating with integrated circuitDeng parts. This electronic equipment for example smart phone, panel computer (PC), individual digital helpHand (PDA) etc.
According to embodiment of the present disclosure, also provide the manufacturer of a kind of chip system (SoC)Method. The method can comprise the method for above-mentioned manufacture semiconductor devices. Particularly, can be at coreIntegrated multiple device on sheet, wherein at least some are manufactured according to method of the present disclosure.
In above description, do not make for the ins and outs such as composition, etching of each layerDetailed explanation. Can be by various technological means but it will be appreciated by those skilled in the art that,Form layer, the region etc. of required form. In addition, in order to form same structure, this area skillArt personnel can also design and the not identical method of method described above. In addition,Although describing respectively above each embodiment, this does not also mean that in each embodimentMeasure can not advantageously be combined with.
Above embodiment of the present disclosure is described. But, these embodiment be only forThe object of explanation, and be not intended to limit the scope of the present disclosure. The scope of the present disclosure is by appendedClaim and equivalent thereof limit. Do not depart from the scope of the present disclosure, those skilled in the art canTo make multiple substituting and amendment, these substitute and amendment all should fall within the scope of the present disclosure.
Claims (28)
1. a semiconductor devices, comprising:
Substrate;
With fin-shaped the first semiconductor layer that substrate separates, the first semiconductor layer is extending longitudinally along itDirection comprises Part I and Part II;
The second semiconductor layer of at least part of Part I periphery around the first semiconductor layer;
The 3rd semiconductor layer of at least part of Part II periphery around the first semiconductor layer;
The separation layer forming on substrate, separation layer expose at least in part the second semiconductor layer andThe 3rd semiconductor layer, the second semiconductor layer exposing and the 3rd semiconductor layer are respectively fin-shaped and extend;And
The first grid crossing with the second semiconductor layer that form on separation layer is stacking and withThe second gate stack that three semiconductor layers are crossing.
2. semiconductor devices according to claim 1, wherein, at least partly around firstThe second semiconductor layer of the Part I periphery of semiconductor layer is positioned at the First of the first semiconductor layerBetween point stacking with the first grid, at least part of Part II periphery around the first semiconductor layerThe 3rd semiconductor layer is between the Part II and second gate stack of the first semiconductor layer.
3. semiconductor devices according to claim 1, wherein, of the first semiconductor layerBetween a part and Part II, separate by dielectric layer.
4. semiconductor devices according to claim 3, wherein, described dielectric layer along withThe crossing direction of the direction extending longitudinally of the first semiconductor layer is extended, and further leads the second halfBody layer and the 3rd semiconductor layer separate.
5. semiconductor devices according to claim 3, wherein,
The Part I of the first semiconductor layer except the side joining with described dielectric layer,Remaining surface is all covered by the second semiconductor layer; And/or
The Part II of the first semiconductor layer except the side joining with described dielectric layer,Remaining surface is all covered by the 3rd semiconductor layer.
6. semiconductor devices according to claim 1, wherein, the second semiconductor layer andOne grid are stacking for N-shaped device, and the 3rd semiconductor layer and second gate stack are used for p-type device,Vice versa.
7. semiconductor devices according to claim 1, wherein, separation layer fills the first halfSpace between conductor, the second semiconductor layer, the 3rd semiconductor layer and substrate.
8. semiconductor devices according to claim 1, wherein, under the second semiconductor layerSide, separation layer and the second semiconductor layer join, and below the 3rd semiconductor layer, separation layer andThe 3rd semiconductor layer joins, and in all the other positions, the end face of separation layer than the second semiconductor layer,The 3rd semiconductor layer will be near substrate towards the bottom surface of substrate.
9. semiconductor devices according to claim 8, wherein, at the second semiconductor layer and/ or the 3rd semiconductor layer below, separation layer has undercutting.
10. semiconductor devices according to claim 1, wherein, the first semiconductor layer bagDraw together Si, the second semiconductor layer, the 3rd semiconductor layer comprise Ge, SiGe or III-V compounds of groupSemiconductor.
11. semiconductor devices according to claim 1, wherein, substrate is silicon single crystal body.
12. semiconductor devices according to claim 11, wherein, the second semiconductor layer and/ or side and the substrate of the 3rd semiconductor layer in (111) family of crystal planes or (110) family of crystal planes largeCause parallel.
13. semiconductor devices according to claim 3, wherein, separation layer comprises oxidationThing, described dielectric layer comprises oxide.
Manufacture the method for semiconductor devices, comprising for 14. 1 kinds:
On substrate, form fin structure;
Cover a part for fin structure, to expose fin structure at the first device area;
At the first device area, for the fin structure exposing, remove its near substratePoint, to form the Part I of the first semiconductor layer, this Part I and substrate are separated;
At the first device area, taking the Part I of the first semiconductor layer as Seed Layer, growth regulationTwo semiconductor layers;
Cover the first device area, and expose fin structure at the second device area;
At the second device area, for the fin structure exposing, remove its near substratePoint, to form the Part II of the first semiconductor layer, this Part II and substrate are separated; WithAnd
At the second device area, taking the Part II of the first semiconductor layer as Seed Layer, growth regulationThree semiconductor layers.
15. methods according to claim 14, wherein, fin structure is included on substrateThe sacrifice layer forming successively and the lamination of the first semiconductor layer.
16. methods according to claim 15, wherein, form fin structure and comprise: comply withInferior the first semiconductor layer and sacrifice layer are patterned into fin structure.
17. methods according to claim 15, wherein, remove fin structure near substrateA part comprise: selective removal sacrifice layer.
18. methods according to claim 14, wherein, by selective growth, next lifeLong the second semiconductor layer and the 3rd semiconductor layer.
19. methods according to claim 14, also comprise:
Form separation layer, wherein separation layer exposes the second semiconductor layer and the 3 half at least in partConductor layer, the second semiconductor layer exposing and the 3rd semiconductor layer are respectively fin-shaped and extend; And
On separation layer, form the first grid crossing with the second semiconductor layer stacking and with the 3rdThe second gate stack that semiconductor layer is crossing.
20. methods according to claim 19, wherein, form separation layer and form theOne grid heap superimposition second gate stack comprises:
In the first device area, forming after the second semiconductor layer and covering the first deviceBefore region, form the Part I of separation layer, and on the Part I of separation layer, form theOne grid are stacking; And
In the second device area, forming after the 3rd semiconductor layer, form the of separation layerTwo parts, and form second gate stack on the Part II of separation layer.
21. methods according to claim 19, wherein, separation layer fill the first semiconductor,Space between the second semiconductor layer, the 3rd semiconductor layer and substrate.
22. methods according to claim 19, wherein, form separation layer and comprise:
On substrate, form oxide skin(coating);
Oxide skin(coating) is eat-back, make below the second semiconductor layer separation layer and secondSemiconductor layer joins, and below the 3rd semiconductor layer, separation layer and the 3rd semiconductor layer join,And in all the other positions, the end face of separation layer than the second semiconductor layer, the 3rd semiconductor layer towardsThe bottom surface of substrate will be near substrate.
23. methods according to claim 22, wherein, are eat-backing oxide skin(coating)Time, below the second semiconductor layer and/or the 3rd semiconductor layer, form undercutting.
24. methods according to claim 14, also comprise:
Between the first device area and the second device area, form dielectric layer, with by the first halfPart I and the Part II of conductor layer are isolated, and the second semiconductor layer and the 3 half is ledBody layer is isolated.
25. methods according to claim 20, wherein, cover the first device area and comprise:
Form shielding layer to cover end face and the side of the first device area.
26. methods according to claim 25, wherein, after forming second gate stack,The method also comprises:
By planarization, remove the shielding layer part on the first device area end face;
Shielding layer part on selective removal the first device area side;
Via owing to removing shielding layer part on the first device area side at the first deviceThe space forming between region and the second device area, selective etch fin structure; And
Between the first device area and the second device area, form dielectric layer, with by the first halfPart I and the Part II of conductor layer are isolated, and the second semiconductor layer and the 3 half is ledBody layer is isolated.
27. 1 kinds of electronic equipments, comprise by partly leading as described in any one in claim 1～13The integrated circuit that body device forms.
28. electronic equipments according to claim 27, also comprise: with described integrated circuitThe display coordinating and the wireless transceiver coordinating with described integrated circuit.
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| US15/781,988 US11038057B2 (en) | 2015-12-07 | 2016-06-27 | Semiconductor device with high-quality epitaxial layer and method of manufacturing the same |
| PCT/CN2016/087244 WO2017096780A1 (en) | 2015-12-07 | 2016-06-27 | Semiconductor device having high-quality epitaxial layer and method for manufacturing same |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106057678A (en) * | 2016-06-17 | 2016-10-26 | 中国科学院微电子研究所 | Epitaxial layer-based semiconductor device, method of manufacturing the same, and electronic apparatus including the same |
| CN106057900A (en) * | 2016-06-17 | 2016-10-26 | 中国科学院微电子研究所 | Epitaxial layer-based semiconductor device, method of manufacturing the same, and electronic apparatus including the same |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050148137A1 (en) * | 2003-12-30 | 2005-07-07 | Brask Justin K. | Nonplanar transistors with metal gate electrodes |
| CN1921116A (en) * | 2005-08-25 | 2007-02-28 | 国际商业机器公司 | Semiconductor structures and methods for forming such semiconductor structures |
| CN101404257A (en) * | 2007-10-05 | 2009-04-08 | 株式会社东芝 | Field effect transistor and method for manufacturing the same |
| CN103855219A (en) * | 2012-11-30 | 2014-06-11 | 三星电子株式会社 | Semiconductor devices including protruding insulation portions between active fins |
| CN104347630A (en) * | 2013-08-01 | 2015-02-11 | 台湾积体电路制造股份有限公司 | Semiconductor device and fabricating the same |
-
2015
- 2015-12-07 CN CN201510888548.9A patent/CN105609560B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050148137A1 (en) * | 2003-12-30 | 2005-07-07 | Brask Justin K. | Nonplanar transistors with metal gate electrodes |
| CN1921116A (en) * | 2005-08-25 | 2007-02-28 | 国际商业机器公司 | Semiconductor structures and methods for forming such semiconductor structures |
| CN101404257A (en) * | 2007-10-05 | 2009-04-08 | 株式会社东芝 | Field effect transistor and method for manufacturing the same |
| CN103855219A (en) * | 2012-11-30 | 2014-06-11 | 三星电子株式会社 | Semiconductor devices including protruding insulation portions between active fins |
| CN104347630A (en) * | 2013-08-01 | 2015-02-11 | 台湾积体电路制造股份有限公司 | Semiconductor device and fabricating the same |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106057678A (en) * | 2016-06-17 | 2016-10-26 | 中国科学院微电子研究所 | Epitaxial layer-based semiconductor device, method of manufacturing the same, and electronic apparatus including the same |
| CN106057900A (en) * | 2016-06-17 | 2016-10-26 | 中国科学院微电子研究所 | Epitaxial layer-based semiconductor device, method of manufacturing the same, and electronic apparatus including the same |
| CN106057678B (en) * | 2016-06-17 | 2019-07-30 | 中国科学院微电子研究所 | Epitaxial layer-based semiconductor device, method of manufacturing the same, and electronic apparatus including the same |
| CN106057900B (en) * | 2016-06-17 | 2019-07-30 | 中国科学院微电子研究所 | Epitaxial layer-based semiconductor device, method of manufacturing the same, and electronic apparatus including the same |
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