CN106057678B - Epitaxial layer-based semiconductor device, method of manufacturing the same, and electronic apparatus including the same - Google Patents
Epitaxial layer-based semiconductor device, method of manufacturing the same, and electronic apparatus including the same Download PDFInfo
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- CN106057678B CN106057678B CN201610438765.2A CN201610438765A CN106057678B CN 106057678 B CN106057678 B CN 106057678B CN 201610438765 A CN201610438765 A CN 201610438765A CN 106057678 B CN106057678 B CN 106057678B
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A semiconductor device and a method of manufacturing the same are disclosed. According to an embodiment, the method may comprise: forming a first fin structure and a second fin structure on a substrate, the first fin structure being stacked over the second fin structure; forming a support part for supporting the first fin-shaped structure on the substrate; at least partially removing a portion of the second fin structure near the bottom of the first fin structure, such that at least a portion of the first fin structure is separated from the second fin structure; growing a first semiconductor layer with a first part of the at least one part of the first fin-shaped structure as a seed layer, and growing a second semiconductor layer with a second part of the at least one part of the first fin-shaped structure as a seed layer; and removing the first fin-shaped structure in at least partial longitudinal extension range of the first fin-shaped structure, and cutting off the first semiconductor layer and the second semiconductor layer on the side of the first fin-shaped structure, which is far away from the substrate, and the side of the first fin-shaped structure, which is close to the substrate.
Description
Technical field
This disclosure relates to semiconductor field, more particularly, to a kind of semiconductor devices based on high quality epitaxial layer and
Its manufacturing method and electronic equipment including it.
Background technique
With the development of semiconductor devices, it is expected that being higher than the semiconductor material of silicon (Si) with mobility to make high-performance half
Conductor device such as Metal Oxide Semiconductor Field Effect Transistor (MOSFET).However, it is very difficult to form the high mobility of high quality
Semiconductor material.
Summary of the invention
The purpose of the disclosure is at least partly to provide a kind of semiconductor devices and its system based on high quality epitaxial layer
Make method and the electronic equipment including it.
According to one aspect of the disclosure, a kind of method of manufacturing semiconductor devices is provided, comprising: be formed on the substrate
First fin structure and the second fin structure, the first fin structure are stacked on the second fin structure；Use is formed on the substrate
To support the support portion of the first fin structure；The second fin structure is at least partly removed close to the portion of the first fin structure bottom
Point, so that at least part of the first fin structure is mutually separated with the second fin structure；With the first fin structure this at least one
First part in part is seed layer growth regulation semi-conductor layer, and with the in at least part of the first fin structure
Two parts are two semiconductor layer of seed layer growth regulation；In at least partly longitudinal extent of the first fin structure, removal the
One fin structure, and in the first fin structure away from one side of substrate and close to one side of substrate respectively by the first semiconductor layer and the
The cutting of two semiconductor layers.
According to another aspect of the present disclosure, a kind of semiconductor devices is provided, comprising: substrate；It is formed on a substrate extremely
Few two fin, wherein at least a pair of adjacent fin edge is roughly parallel to substrate table at least two fin
The direction in face arranges, and be separated from each other substantially parallel extension, and is essence on crystal structure relative to the middle line between them
Upper mirror symmetry, each fin includes the first semiconductor layer and the second semiconductor layer along its longitudinal extension.
According to the another aspect of the disclosure, a kind of electronic equipment is provided, including the collection formed by above-mentioned semiconductor device
At circuit.
In accordance with an embodiment of the present disclosure, it can use (thin) semiconductor layer relative to substrate suspension as seed layer, come
Other semiconductor layer is grown, which can have high mobility.This thin seed layer of suspension can make to plant
Stress relaxation in sublayer and the semiconductor layer grown, to help to inhibit in seed layer or the semiconductor layer grown
Defect.Later, seed layer can be removed, the semiconductor layer grown can be used for being formed device (for example, the semiconductor layer is used as
The fin of FinFET).
Detailed description of the invention
By referring to the drawings to the description of the embodiment of the present disclosure, the above-mentioned and other purposes of the disclosure, feature and
Advantage will be apparent from, in the accompanying drawings:
Fig. 1-32 (b) is to diagrammatically illustrate the schematic diagram of the manufacturing semiconductor devices process according to the embodiment of the present disclosure；
Figure 33-39 (b) is diagrammatically illustrated in the middle part of the manufacturing semiconductor devices process according to another embodiment of the disclosure
Schematic diagram stage by stage.
Specific embodiment
Hereinafter, will be described with reference to the accompanying drawings embodiment of the disclosure.However, it should be understood that these descriptions are only exemplary
, and it is not intended to limit the scope of the present disclosure.In addition, in the following description, descriptions of well-known structures and technologies are omitted, with
Avoid unnecessarily obscuring the concept of the disclosure.
The various structural schematic diagrams according to the embodiment of the present disclosure are shown in the attached drawings.These figures are not drawn to scale
, wherein some details are magnified for the purpose of clear expression, and some details may be omitted.It is shown in the drawings
Various regions, the shape of layer and relative size, positional relationship between them are merely exemplary, in practice may be due to system
It makes tolerance or technical restriction and is deviated, and those skilled in the art may be additionally designed as required with difference
Shape, size, the regions/layers of relative position.
In the context of the disclosure, when one layer/element is referred to as located at another layer/element "upper", which can
May exist intermediate layer/element on another layer/element or between them.In addition, if in a kind of direction
In one layer/element be located at another layer/element "upper", then when turn towards when, which can be located at another layer/member
Part "lower".
In accordance with an embodiment of the present disclosure, a kind of semiconductor devices with fin is provided.Here, so-called " fin-shaped
Portion " refers to relative to substrate surface construction outstanding, the including but not limited to fin in fin formula field effect transistor (FinFET).
Fin may include high mobility semiconductor material, to improve device performance.Here, so-called " high mobility " refers to relatively
Want high in the mobility of silicon (Si).High mobility semiconductor material such as Ge, SiGe or Group III-V compound semiconductor etc..
In accordance with an embodiment of the present disclosure, this fin can be manufactured based on suspension construction.Here, so-called " suspension ",
Refer to and is mutually separated with substrate.Note that this separation can then be filled by other materials (for example, separation layer).
For example, fin can be (example on the semiconductor layer (or being referred to as " seed layer ") separated on substrate with substrate
Such as, extension) formed other semiconductor layer.Seed layer can be in fin-shaped (for example, straight line fin-shaped), and outstanding relative to substrate
It sets.Then, which can be formed with the periphery of at least partly about seed layer.Here, so-called " partly ring
Around ", there may be a ranges for the longitudinal extension for referring to along seed layer, and in the range, which can be with
The outer surface of encapsulating seed layer completely.That is, in the range, on the section vertical with the longitudinal extension of seed layer,
The other semiconductor layer can form closed pattern (for example, rectangle corresponding with the cross sectional shape of seed layer, polygon
Deng).Certainly, other than the surface that supported portion covers, remaining surface can also be covered seed layer by the other semiconductor layer
Lid.Seed layer can relatively thin (for example, with a thickness of about 3~20nm), and relative to substrate suspend.In this way, in growth course
Stress in middle seed layer and the other semiconductor layer can be able to relaxation, and therefore can inhibit or avoid in seed body layer
Or defect is generated in the other semiconductor layer.
According to embodiment, semiconductor devices may include p-type device (such as pFinFET) and n-type device (such as nFinFET),
To form complementary metal oxide semiconductor (CMOS) device.In this case, according to an advantageous embodiment, a pair of of p-type
Device and n-type device can be manufactured based on the seed layer integrally extended originally.For example, first at least partially about seed layer
Portion perimeter can form the first semiconductor layer, and can form the second half at least partially about the second part periphery of seed layer
Conductor layer.The first part of seed layer and second part can be separated from each other along its longitudinal extension.In this way, the first semiconductor
Layer may be used as the fin of the first device, and the second semiconductor layer may be used as the fin of the second device.First device can be N-shaped device
Part such as nFinFET, the second device can be p-type device such as pFinFET；Vice versa.
In order to further decrease defect, one layer of transition zone can be first grown on the seed layer, it is then raw on transition zone again
Long first/second semiconductor layer.The lattice constant of the transition zone can gradually change (for example, the change for passing through its ingredient), example
It is such as gradually changed into from the lattice constant equal or close to seed layer normal equal or close to the lattice of first/second semiconductor layer
Number.As described above, transition zone can be formed with the periphery of at least partly about seed layer, and first/second semiconductor layer can be with
The periphery of at least partly about transition zone is formed.
In accordance with an embodiment of the present disclosure, seed layer (and transition zone, if present) can remove, leave first/
At least part of second semiconductor layer is used for example as the fin of device.It is located at for example, first/second semiconductor layer can be left
The part of seed layer both lateral sides (here, being referred to as " left side " and " right side "), that is, be approximately perpendicular to the part of substrate surface extension.
Since first/second semiconductor layer is using seed layer as seed growth, the left part and right part of first/second semiconductor layer
Grown since the left side side wall of seed layer (or transition zone) and right sidewall respectively, thus their crystal structure relative to
Center between them can be symmetrical with substantial mirror images.
Seed layer can be physically connected to substrate through support portion and therefore by substrate supports.In longitudinal extension side of seed layer
Upwards, the expanded range for the part that seed layer is connected with support portion can be less than the longitudinal extent of seed layer.In this way, working as
When only observing positional relationship (not the considering other layer of structure) between seed layer, substrate and support portion, seed layer is similar to one kind
Overarm construction, support portion are similar to the anchoring structure (anchor) of overarm.
Support portion may include that the lateral extension portions extended along substrate surface and edge are approximately perpendicular to substrate surface
The vertical extension that direction extends, wherein vertical extension extends to the vertical side that seed layer is approximately perpendicular to substrate surface
On wall.In this way, seed layer is physically connected on substrate, and by the support portion therefore by substrate supports.Support portion it is vertical
Extension can extend in the upright side walls of the opposite sides of seed layer, to clamp seed layer.
Support portion can be set to the seed layer of fin-shaped along the middle part of its longitudinal extension or remaining position such as two sides
One of end or both ends.
This semiconductor devices can for example make as follows.Specifically, it can be formed on the substrate vertical along (for example, straight line)
The first fin structure and the second fin structure extended to extending direction, wherein the first fin structure is stacked on the second fin structure
On.Then, when at least removing part of second fin structure close to the first fin structure bottom, the first fin structure can
Mutually to be separated with the second fin structure, so that the first fin structure can be relative to substrate (in other words, relative to substrate+the second
The remainder of fin structure) suspension.
In order to support then the first fin structure by suspension, support portion can be formed.This support portion can following shape
At.Specifically, stratified material (hereinafter referred to as supporting layer) can be formed on the substrate for being formed with the first and second fin structures,
And it physically connects the surfaces of the first and second fin structures by the way that the supporting layer to be patterned into and forms support portion.In this way,
When at least removing part of second fin structure close to the first fin structure bottom, the first fin structure can pass through support portion
It is physically connected to the remainder of the second fin structure, and is therefore supported by the remainder of the second fin structure.More into
One step, supporting layer can be patterned into and extend to the surface of the first fin structure from substrate surface and therefore by the first fin-shaped knot
The support portion that structure is physically connect with substrate.Even if the first fin structure can also in this way, the second fin structure is completely removed
To be physically connected to substrate and with this by substrate supports by support portion.
The composition of supporting layer can use mask progress.Perpendicular to the first and second fin structure longitudinal extensions
On direction, mask extends beyond the range of the first and second fin structures (in this way, mask above the first and second fin structures
The part that supporting layer extends on the substrate surface of the first and second fin structure two sides can be covered, so that the part then may be used
To be retained)；And in the longitudinal extension of the first and second fin structures, mask is on the first and second fin structures
The only a part of the longitudinal extent of the first and second fin structures of side's covering is (in this way, the first and second fin-shaped of masked
The only a part of the longitudinal extent of structure, so that the part can then be connected with support portion).Mask can cover first
With the middle part (alternatively, a side end or both side ends) of the second fin structure, obtained support portion can be correspondingly situated at fin-shaped
The middle part (alternatively, a side end or both side ends or) of structure.
Later, the second fin structure can at least be removed close to the part of the first fin structure bottom.In this way, the first fin-shaped
Structure is similar to overarm construction relative to substrate, and support portion is similar to the anchoring structure (anchor) of overarm, will be as overarm
First fin structure is anchored into substrate.
The second fin structure is at least removed close to the part of the first fin structure bottom for the ease of removal or or even is gone
Except entire second fin structure, the second fin structure may include sacrificial layer formed on a substrate, and the first fin structure can
To include the semiconductor layer (" seed layer ") being stacked on sacrificial layer.For example, sacrificial layer and kind can be sequentially formed on substrate
Then seed layer and sacrificial layer can be patterned into fin structure by sublayer.It may proceed in substrate in the pattern step, thus
It can have protrusion at position corresponding with fin structure on substrate.Then, sacrificial layer can be removed.
Due to seed layer suspension to expose on its surface, it can grow that (transition zone and) is other partly to lead on the surface thereof
Body layer.As set forth above, it is possible to form two or more devices based on same fin structure.These devices can have different match
It sets, such as the configuration for n-type device and the configuration for p-type device.For example, can be with seed layer along its longitudinal extension
First part be the first semiconductor layer of seed growth, and using seed layer along its longitudinal extension second part as seed growth
Second semiconductor layer.
In this case, in order to be respectively formed different semiconductor materials around seed layer as described above, kind can first be covered
A part of sublayer, to expose the first part of seed layer in the first device area.In the first device area, the first of seed layer
Part is relative to substrate suspension so that its surface is exposed, therefore can grow a kind of semiconductor material on the surface thereof.Then, exist
In the case where sufficiently growing, the semiconductor material of growth can cover all surface of seed layer exposing.The semiconductor material can
Equally it is in fin-shaped with same seed layer, and may then act as the fin of the first device (for example, n-type device).Later, can be covered
One device area, and expose the second part of seed layer in the second device area.In the second device area, second of seed layer
Split-phase is for substrate suspension so that its surface is exposed, therefore can grow another semiconductor material on the surface thereof.Then, it is filling
In the case where mitogenetic length, the semiconductor material of growth can cover all surface of seed layer exposing.Another semiconductor material
It equally can be in fin-shaped with seed layer, and may then act as the fin of the second device (for example, p-type device).
Between device between the active area of such as n-type device and p-type device, isolation can be formed.For example, can be
Between one device area (for example, n-type device region) and the second device area (for example, p-type device region), it can will likely connect
The first semiconductor layer and the second semiconductor layer being connected together are isolated.This isolation can by the two device areas it
Between position at realize that (dielectric layer that can be then subsequently formed in notch such as interlevel dielectric layer etc. is filled out by cutting off
It fills).
In at least partly longitudinal extent, seed layer (and transition zone, if present) can be removed, is left
First/second semiconductor layer, such as the fin as device.Since seed layer (and transition zone) is by first/second semiconductor layer
It surrounds, for convenient for removing seed layer (and transition zone), can deviate from one side of substrate (here, being referred to as " upside ") in seed layer will
First/second semiconductor layer opening is cut off in other words, with (transition zone and) seed layer of exposing inside thereof.First/second is partly led
The scale of opening notch in other words in body layer is enough to support then to be formed grid via it and stacks that (including gate dielectric layer and grid are led
Body layer and optional work function regulating course).Further, it is also possible to further close to one side of substrate (here, being referred to as " downside ")
First/second semiconductor layer opening is cut off in other words.Especially it is possible to by first/second semiconductor layer upside and under
The lateral extension portions part of extension (the be roughly parallel to substrate surface) removal of side, at least partly longitudinally extend model at this
In enclosing, the remaining portion for being located at the first semiconductor layer both lateral sides (that is, " left side " and " right side ") originally of first/second semiconductor layer
Point, that is, it is approximately perpendicular to the part of substrate surface extension, this can be used for making devices, such as serve as the fin of device.
Further, it is also possible to cut off end (example of the first/second semiconductor layer in the longitudinal extension of fin structure
It such as, can be by first/second semiconductor layer in the part that transition zone or seed layer extend on end face in longitudinal extension
Removal), so that first/second semiconductor layer to be divided into two parts relative to each other.First/second is partly being led as described above
In the case where the lateral extension portions removal of the upper and lower two sides of body layer, each section of remaining first/second semiconductor layer is equal at this time
The direction for being approximately perpendicular to substrate surface extends, similar to the form of fin in routine techniques.
It, can there are ways to complete the manufacture of device based on fin.For example, isolation can be formed on the substrate
Layer, and formed on separation layer and stacked with the first/second semiconductor layer grid that fin intersects in other words.
The disclosure can be presented in a variety of manners, some of them example explained below.
As shown in Figure 1, providing substrate 1001.The substrate 1001 can be various forms of substrates, such as, but not limited to body
Semiconductive material substrate such as body Si substrate etc..In the following description, for convenience of description, it is described by taking body Si substrate as an example.
In particular, substrate 1001 can be silicon single crystal body, surface can be such as (110) crystal face, (100) crystal face or (112) crystal face.
On substrate 1001, such as by epitaxial growth, sequentially form sacrificial layer 1003 and the first semiconductor layer 1005.It is sacrificial
Domestic animal layer 1003 may include the semiconductor material different from substrate 1001 and the first semiconductor layer 1005, such as the SiGe (atom of Ge
Percentage for example about 5~20%), with a thickness of about 10~100nm.First semiconductor layer 1005 may include suitable semiconductor
Material, such as Si, with a thickness of about 10~100nm.
It then, can (optionally, there are also substrates to the first semiconductor layer 1005 and sacrificial layer 1003 being thusly-formed
1001) it is patterned, to form fin structure.For example, this can be carried out as follows.
Specifically, hard mask layer can be formed on the first semiconductor layer 1005.In this example, hard mask layer can wrap
Include oxide (for example, silica) layer 1007 and poly-si layer 1009.For example, oxide skin(coating) 1007 with a thickness of about 2~10nm,
Poly-si layer 1009 with a thickness of about 50~120nm.In this example, using pattern transfer technology, hard exposure mask is patterned into
Fin-shaped.For this purpose, the photoresist PR of composition (for example, by exposure, development) can be formed on hard mask layer.Here, photoresist
The strip that the patterned edge PR extends perpendicular to paper direction, and its width (dimension in figure in horizontal direction) can be generally corresponding to
Spacing between two fin structures.
Then, as shown in Fig. 2, using photoresist PR as mask, to poly-si layer 1009 (relative to oxide layer 1007) into
Row selective etch such as reactive ion etching (RIE).In this way, poly-si layer 1009 can be patterned into corresponding with photoresist PR
Strip.Then, as shown in Fig. 3 (a), photoresist PR is removed, and form side wall on the side wall of poly-si layer 1009
(spacer)1011.There are multiple means for this field to form side wall.For example, can be by such as atomic layer deposition (ALD) substantially
One layer of nitride (for example, silicon nitride) of conformal deposition, thickness are, for example, about 3~20nm, are then selected the nitride of deposit
Selecting property etching such as RIE (for example, carrying out along the direction for being approximately perpendicular to substrate surface), removes its lateral extension portions, so that perpendicular
Straight extension retains, to form side wall 1011.The side wall of 1011 overlying si layer 1009 of side wall.
Fig. 3 (b) shows the top view of structure shown in Fig. 3 (a).Note that although being not shown in Fig. 3 (b), in item
On the side wall of the upper and lower ends of shape poly-si layer 1009, there is also side walls 1011, so that side wall 1011 is around strip poly-si layer
1009 periphery forms closed pattern.
The mask of fin-shaped in order to obtain, as (Fig. 4 (a) is top view to Fig. 4 (a) and 4 (b), and 4 (b) be the AA ' along Fig. 4 (a)
The sectional view of line) shown in, the property of can choose removes poly-si layer 1009 (for example, passing through TMAH solution), then re-forms composition
Photoresist 1013.Photoresist 1013 can cover the middle part of side wall 1011, and expose the part of about 1011 two sides of side wall.With
The photoresist 1013 is mask, selective etch such as RIE is carried out to side wall 1011, so as to be originally used for the side of closed pattern
Wall 1011 is separated into two parts, as shown in Figure 5.Each section corresponds to fin structure to be formed, is in this example edge
The strip that vertical direction in figure extends.
It then, can be successively to oxide skin(coating) 1007, the first semiconductor layer as shown in fig. 6, being mask with side wall 1011
The 1005 and progress of sacrificial layer 1003 selective etch such as RIE.In this way, the pattern of side wall 1011 is transferred in the layer of lower section, obtain
To fin structure.Therefore, the width (dimension of horizontal direction in figure) of the first semiconductor layer 1005 is big with the width of side wall 1011
Cause identical (for example, about 3~20nm).The side wall (side wall of the left and right sides in figure) of first semiconductor layer 1005 can be (111)
Or (110) crystal face, these crystal faces are easily reduced growth defect.
Here, can also further selective etch substrate 1001.Therefore, at position corresponding with fin structure,
It can have protrusion on substrate 1001.The projection of fin structure on substrate is located substantially at the middle part of the protrusion.Due to etching
The protrusion of characteristic, sacrificial layer 1003 and substrate 1001 after etching can be in the shape become larger from top to bottom.Later, may be used
With selective removal side wall 1011 (acceptable further selective removal oxide skin(coating) 1007).
Although forming fin structure in pattern transfer technology utilized above, but the present disclosure is not limited thereto.For example, can be with
The photoresist that fin-shaped is formed directly on the first semiconductor layer 1005, and using photoresist as mask, selective etch the first half is led
Body layer 1005, sacrificial layer 1003 and substrate 1001, to form fin structure.Alternatively, can also directly be formed on hard mask layer
Hard exposure mask is patterned into fin-shaped using photoresist by the photoresist of fin-shaped, and utilizes the hard exposure mask of fin-shaped successively selective etch the
Semi-conductor layer 1005, sacrificial layer 1003 and substrate 1001, to form fin structure.
Here, showing two fin structures.But the present disclosure is not limited thereto, such as can be formed more or fewer
Fin structure.In addition, the layout of fin structure can need differently to design according to device.
After forming fin structure, support portion can be formed.For example, as shown in fig. 7, fin structure can be formed with
Substrate on, such as by ALD, substantially conformally, deposited oxide layer 1015 and nitride layer 1017.Oxide skin(coating)
1015 thickness can be about 1~10nm, and the thickness of nitride layer 1017 can be about 2~15nm.Later, such as bowing in Fig. 8
Shown in view, the photoresist 1019 of composition is formed in structure that can be shown in Fig. 7.The photoresist 1019 is patterned to covering fin
The middle part of shape structure, and the horizontal direction in figure extends.It is to be herein pointed out in a top view in fig. 8, only for convenience
For the sake of, do not show that the pattern that nitride layer 1017 rises and falls with fin structure on substrate, it is same in following top view.
Then, as Fig. 9 (a), 9 (b) and 9 (c) (Fig. 9 (a) is top view, Fig. 9 (b) be along Fig. 9 (a) A1A1 ' and
The sectional view of A2A2 ' line, Fig. 9 (c) they are the sectional views of the AA ' line along Fig. 9 (a)) shown in, it is mask with photoresist 1019, such as
Pass through RIE (relative to oxide skin(coating) 1015) selective removal nitride layer 1017.In this way, as shown in Fig. 9 (c), nitride layer
1017 stay in the middle part of fin structure, and extend on the surface of substrate 1001.In this way, nitride layer 1017 by fin structure with
Substrate 1001 physically connects, and therefore can support fin structure (especially as described below removal sacrificial layer 1003 it
Afterwards).Later, photoresist 1019 can be removed.
In this embodiment, the supporting layer of the laminated construction of oxide skin(coating) and nitride layer is formd, and by the supporting layer
It is patterned into support portion.But the present disclosure is not limited thereto.Supporting layer may include various suitable dielectric substances.It is gone then
Except in the embodiment of support portion, supporting layer can also include even semiconductor material or conductive material.
In addition, as shown in Figure 10 (corresponding to the sectional view in Fig. 9 (c)), it can also be for example by RIE (relative to oxidation
Nitride layer 1015) selective removal nitride layer 1017 tip portion.But nitride layer 1017 still some stay in first
On the side wall of semiconductor layer 1005, so as to the first semiconductor layer of rear support 1005.
Later, as shown in Figure 11 (a) and 11 (b) (corresponding respectively to the sectional view in Fig. 9 (b) and 9 (c)), can pass through
Such as RIE, (relative to the substrate 1001 of Si material and the sacrificial layer 1003 of the first semiconductor layer 1005 and sige material), choosing
Selecting property removes oxide skin(coating) 1015.As shown in Figure 11 (b), at the middle part of fin structure, oxide skin(coating) 1015 is by nitride layer
1017 coverings, and may be retained.Then, as Figure 12 (a) and 12 (b) (corresponds respectively to the section of Figure 11 (a) He 11 (b)
Figure) shown in, (substrate 1001 and the first semiconductor layer 1005 relative to Si material) selective etch such as wet process can be passed through
Corrosion removes sacrificial layer 1003.In this way, forming interval 1021 between the first semiconductor layer 1005 and substrate 1001 of fin-shaped.
In this example, sacrificial layer 1003 is entirely removed.But the present disclosure is not limited thereto.For example, sacrificial layer 1003 can
It is removed with the part only close to 1005 bottom of the first semiconductor layer.In this case, it equally may be implemented following around
The growth of 1005 periphery of semi-conductor layer.
Figure 13 shows the perspective view of structure shown in Figure 12 (a) and Figure 12 (b).As shown in figure 13, the first semiconductor layer
1005 1021 are separated by interval with substrate 1001, are roughly parallel to substrate surface and are extended, and through support portion 1015/1017 and by
Substrate 1001 supports.For example, the extending direction of the first semiconductor layer 1005 can be parallel when substrate surface is (110) crystal face
In the cross spider or (110) crystal face of (110) crystal face and (1-11) crystal face and the cross spider of (1-1-1) crystal face or (110) crystal face with
The cross spider of (- 111) crystal face, the side of the first semiconductor layer 1005 can be roughly parallel to (111) family of crystal planes；Or in substrate table
In the case that face is (112) crystal face, the extending direction of the first semiconductor layer 1005 can be parallel to (112) crystal face and (- 1-11)
The side of the cross spider of the cross spider of crystal face or (112) crystal face and (11-1) crystal face, the first semiconductor layer 1005 can also be substantially
It is parallel to (111) family of crystal planes.Alternatively, the extending direction of the first semiconductor layer 1005 can correspond to 110 direction > <, serving as a contrast
In the case that bottom surface is (100) crystal face, the side of the first semiconductor layer 1005 can be roughly parallel to (110) crystal face.These
Crystal face is easily reduced growth defect.
In Figure 13, for the sake of convenience, single first semiconductor layer 1005 and corresponding support portion are illustrated only, and
Remaining oxide skin(coating) 1015 is not showed that.
Support portion 1015/1017 includes lateral extension portions extended on the surface of substrate 1001 and along substantially vertical
In the vertical extension that the direction of substrate surface extends.In this example, vertical extension may include along substrate 1001
Protrusion surface extend part, along sacrificial layer 1003 (having been removed) surface extend part and along the first semiconductor
The part that the upright side walls of layer 1005 extend.In this way, the first semiconductor layer 1005 is physically connected to lining by support portion 1015/1017
Bottom 1001, so as to support the first semiconductor layer 1005.Support portion 1015/1017 can be in the phase of the first semiconductor layer 1005
To extending in the upright side walls of two sides (left and right sides in figure), so that the first semiconductor layer is clamped, to support more stablely
First semiconductor layer 1005.Certainly, in this example, support portion 1015/1017 is also in the first semiconductor layer 1005 towards reader
Extend in the end sidewalls of side.In the longitudinal extension of the first semiconductor layer 1005, the first semiconductor layer 1005 and branch
Support part 1015/1017 be connected part expanded range less than the first semiconductor layer 1005 longitudinal extent.Here, so-called
" longitudinal extension " refers to the length direction of the first semiconductor layer 1005 (perpendicular to the side of paper in Figure 12 (a) and Figure 12 (b)
To), it is substantially consistent with the length direction of the channel region formed later, that is, direction from source region to drain region or otherwise also
So.In this way, the first semiconductor layer 1005 forms the construction for being similar to overarm relative to substrate 1001, which passes through support portion
1015/1017 is anchored to substrate 1001.
In the above examples, support portion further includes oxide skin(coating) 1015 other than nitride layer 1017, but the disclosure
It is without being limited thereto.For example, oxide skin(coating) 1015 can not be formed in the operation above in conjunction with Fig. 7 description, and directly form nitridation
Nitride layer 1017.In this way, equally successor operation can be carried out in the way of combining Fig. 8-12 (b) description above.Certainly, support portion
It can be other dielectric substances or laminated construction.
In addition, the mask 1019 (referring to Fig. 8) for being used to composition support portion is not limited to above-mentioned shape.Generally, perpendicular to
On the direction of fin structure longitudinal extension, mask can extend beyond the range of fin structure above fin structure.This
Sample, the part that mask can be extended on substrate 1001 (except protrusion) surface with cover nitride layer 1017, this part are subsequent
(pedestal for serving as support portion) can be retained.On the other hand, in the longitudinal extension of fin structure, mask is in fin structure
Top can cover the only a part of the longitudinal extent of fin structure.In this way, similar overarm-anchoring structure can be formed
Configuration.
Later, a part (for example, the lower half as shown in Fig. 9 (a)) that the first semiconductor layer can be covered, first
Device area (for example, the upper half area as shown in Fig. 9 (a)) exposes the first semiconductor layer.
Specifically, as shown in Figure 14 (a) and 14 (b) (sectional views for corresponding respectively to Figure 12 (a) He 12 (b)), for example, it is logical
ALD is crossed, forms shielding layer in the structure shown in Figure 12 (a) and 12 (b).Here, shielding layer may include with substantially conformal
The oxide skin(coating) 1023 (thickness is, for example, about 2~5nm) and nitride layer 1025 that mode deposits (thickness is, for example, about 2~5nm).
In this way, it is completely obscured to be formed by structure on substrate before shielding layer general.
It is then possible to which the shielding layer is patterned into a part of the first semiconductor layer of masking and is exposed in the first device area
The first part of first semiconductor layer.
For example, as (Figure 15 (a) is top view to Figure 15 (a) -15 (d), and Figure 15 (b) is the section of the AA ' line along Figure 15 (a)
Figure, Figure 15 (c) is the sectional view of the A1A1 ' line along Figure 15 (a), and Figure 15 (d) is the sectional view of the A2A2 ' line along Figure 15 (a)) institute
Show, forms photoresist 1027 on shielding layer, and photoresist 1027 is patterned by covering first by photoetching (exposure, development etc.)
The lower half (corresponding to the second device area) of semiconductor layer, and the horizontal direction in figure extends.It is to be herein pointed out
In the top view of Figure 15 (a), for convenience only, the details of support portion position is not been shown in detail, this will not be hampered
Hinder the understanding present invention.It is same in following top view.
Then, as shown in Figure 16 (a) -16 (c) (sectional view for corresponding respectively to Figure 15 (b) -15 (d)), with photoresist
1027 be mask, such as removes nitride layer 1025 by RIE (relative to 1023 selective etch of oxide skin(coating)).Later, may be used
To remove photoresist 1027.In this way, in the first device area, nitride layer 1025 is gone as shown in Figure 16 (a) and 16 (b)
It removes；And in the second device area, as shown in Figure 16 (c), nitride layer 1025 is retained.Then, such as pass through RIE (phase
Nitride Selectivity is etched), remove oxide skin(coating) 1023.Later, photoresist 1027 can be removed.Then, such as Figure 17
(a) shown in -17 (c) (sectional view for corresponding respectively to Figure 16 (a) -16 (c)), in the first device area, shielding layer (1023,
1025) it is removed；And in the second device area, shielding layer (1023,1025) is retained.
Then, the first semiconductor layer exposes in the first device area, and shielded in the second device area.
Then, as shown in Figure 18 (a) -18 (c) (sectional view for corresponding respectively to Figure 17 (a) -17 (c)), in the first device
In region, can on the first semiconductor layer 1,005 two semiconductor layer 1029 of growth regulation.Here, the second semiconductor layer 1029 can be with
Including high mobility material, for example, Ge, SiGe or Group III-V compound semiconductor such as InSb, InGaSb, InAs, GaAs,
InGaAs, AlSb, InP, tri-nitride etc., thickness can be about 3~15nm.The compound semiconductor such as SiGe the case where
Under, ingredient (for example, Ge atomic percent) can with gradual change so that for example from the first semiconductor layer 1005 (here, Si)
Lattice constant, which differs less, to be become differing larger with the lattice constant of the first semiconductor layer 1005, to inhibit dislocation or defect
It generates.The side of second semiconductor layer 1029 can in substrate (111) family of crystal planes or (110) family of crystal planes it is substantially parallel.
In addition, as set forth above, it is possible to transition zone 1027 is first grown on the first semiconductor layer 1005, then again in transition zone
Two semiconductor layer 1029 of growth regulation on 1027.Transition zone 1027 may include various suitable semiconductor materials, such as Ge, SiGe
Or Group III-V compound semiconductor such as InSb, InGaSb, InAs, GaAs, InGaAs, AlSb, InP, tri-nitride etc., it is thick
Degree can be about 5nm-15nm.Transition zone 1027 may include the material identical or different with the second semiconductor layer 1029.
This growth can be selective growth, thus first semiconductor layer 1005 of the transition zone 1027 in semiconductor material
It is grown on the surface of (and substrate 1001), the second semiconductor layer 1029 is raw on the surface of the transition zone 1027 of semiconductor material
It is long.It can control the growth of transition zone 1027 and the second semiconductor layer 1029, so that it is not fully filled with the first semiconductor layer
Interval 1021 between 1005 and substrate 1001.Since the suspension of the first semiconductor layer 1005 constructs, during the growth process first
Stress in semiconductor layer 1005, transition zone 1027 and the second semiconductor layer 1029 can be able to relaxation.In this way, can inhibit or
It avoids generating defect in the first semiconductor layer 1005, transition zone 1027 or the second semiconductor layer 1029, this helps to improve device
Performance (for example, reduce OFF leakage current and promote on-state current).
In this example, the surface that the first semiconductor layer 1005 exposes is covered by transition zone and the second semiconductor layer.When
So, can also grow on the surface of substrate 1001 has transition zone 1027 and the second semiconductor layer 1029.
In this example, in the first device area, along the longitudinal extension of the first semiconductor layer, in addition to support portion institute
Except the longitudinal extent occupied, at remaining longitudinal extent, the first semiconductor layer of encapsulating completely of transition zone 1027
1005 periphery, and the periphery of the second semiconductor layer 1029 encapsulating transition zone 1027 completely.In this way, with the first semiconductor layer
On the vertical section of 1005 longitudinal extension (that is, section shown in Figure 18 (a)), transition zone 1027 forms closed pattern
(being rectangle in the example), and the second semiconductor layer 1029 forms closed pattern (being rectangle in the example).Certainly, the closure figure
Pattern of the case by the first semiconductor layer 1005 in the section is determined, and can be other shapes such as polygon.
Second semiconductor layer 1029 may then act as the fin of device.
Later, the second device area (half area as shown in Figure 15 (a)) can be carried out in the same way
Processing, to form the fin of the second device in the second device area.
Specifically, the first device area can be covered, and exposes the first semiconductor layer in the second device area.
For example, as (Figure 19 (a) is top view to Figure 19 (a) -19 (c), and Figure 19 (b) is the section of the AA ' line along Figure 19 (a)
Figure, Figure 19 (c) is the sectional view of the A2A2 ' line along Figure 19 (a)) shown in, such as by ALD, shown in Figure 18 (a) -18 (c)
Shielding layer is formed in structure.Here, shielding layer may include (the thickness example of oxide skin(coating) 1031 substantially conformally deposited
For example about 2~5nm) and nitride layer 1033 (thickness is, for example, about 2~5nm).In this way, shielding layer incites somebody to action before institute's shape on substrate
At structure it is completely obscured.
It is then possible to which the shielding layer is patterned into the first device area of masking and exposes the first half in the second device area and leads
The second part of body layer.
As shown in Figure 19 (a) -19 (c), photoresist 1035 is formed on shielding layer, and pass through photoetching (exposure, development etc.)
Photoresist 1035 is patterned into the upper half (corresponding to the first device area) of the first semiconductor layer of covering, and the level in figure
Direction extends.
Then, as shown in Figure 20 (a) and 20 (b) (sectional views for corresponding respectively to Figure 19 (b) He 19 (c)), with photoresist
1035 be mask, such as by RIE, successively selective etch nitride layer 1033 (relative to oxide skin(coating) 1031), oxide
1031 (relative to nitride layer 1025) of layer, nitride layer 1025 (relative to oxide skin(coating) 1023) and oxide skin(coating) 1023
(relative to nitride layer 1017).Later, photoresist 1035 can be removed.In this way, as shown in Figure 20 (b), in the second device region
In domain, shielding layer (1031,1033) is removed；And in the first device area, shielding layer (1031,1033) is retained, such as
Shown in Figure 20 (a).
Then, the first semiconductor layer exposes in the second device area, and shielded in the first device area.
It then,, can be the first half in the second device area as shown in Figure 21 the sectional view of Figure 20 (b) (correspond to)
Three semiconductor layer 1039 of growth regulation in conductor layer 1005.Here, third semiconductor layer 1039 may include high mobility material, example
Such as Ge, SiGe or Group III-V compound semiconductor such as InSb, InGaSb, InAs, GaAs, InGaAs, AlSb, InP, three races's nitrogen
Compound etc., thickness can be about 3~15nm.In the case where compound semiconductor such as SiGe, ingredient is (for example, Ge atom hundred
Point ratio) it can be with gradual change, so that for example becoming and the from differ less with the lattice constant of the first semiconductor layer 1005 (here, Si)
The lattice constant difference of semi-conductor layer 1005 is larger, to inhibit the generation of dislocation or defect.Third semiconductor layer 1039
Side can in substrate (111) family of crystal planes or (110) family of crystal planes it is substantially parallel.
In addition, as set forth above, it is possible to transition zone 1037 is first grown on the first semiconductor layer 1005, then again in transition zone
Three semiconductor layer 1039 of growth regulation on 1037.Transition zone 1037 may include various suitable semiconductor materials, such as Ge, SiGe
Or Group III-V compound semiconductor such as InSb, InGaSb, InAs, GaAs, InGaAs, AlSb, InP, tri-nitride etc., it is thick
Degree can be about 5nm-15nm.Transition zone 1037 may include the material identical or different with third semiconductor layer 1039.
This growth can be selective growth, thus first semiconductor layer 1005 of the transition zone 1037 in semiconductor material
It is grown on the surface of (and substrate 1001), third semiconductor layer 1039 is raw on the surface of the transition zone 1037 of semiconductor material
It is long.It can control the growth of transition zone 1037 and third semiconductor layer 1039, so that it is not fully filled with the first semiconductor layer
Interval 1021 between 1005 and substrate 1001.Since the suspension of the first semiconductor layer 1005 constructs, during the growth process first
Stress in semiconductor layer 1005, transition zone 1037 and third semiconductor layer 1039 can be able to relaxation.In this way, can inhibit or
It avoids generating defect in the first semiconductor layer 1005, transition zone 1037 or third semiconductor layer 1039, this helps to improve device
Performance (for example, reduce OFF leakage current and promote on-state current).
In this example, the surface that the first semiconductor layer 1005 exposes is covered by transition zone and third semiconductor layer.When
So, can also grow on the surface of substrate 1001 has transition zone 1037 and third semiconductor layer 1039.
In this example, in the second device area, along the longitudinal extension of the first semiconductor layer, in addition to support portion institute
Except the longitudinal extent occupied, at remaining longitudinal extent, the first semiconductor layer of encapsulating completely of transition zone 1037
1005 periphery, and the periphery of the encapsulating transition zone 1037 completely of third semiconductor layer 1039.In this way, with the first semiconductor layer
On the vertical section of 1005 longitudinal extension (that is, section shown in Figure 20 (a)), transition zone 1037 forms closed pattern
(being rectangle in the example), and third semiconductor layer 1039 forms closed pattern (being rectangle in the example).Certainly, the closure figure
Pattern of the case by the first semiconductor layer 1005 in the section is determined, and can be other shapes such as polygon.
Third semiconductor layer 1039 may then act as the fin of device.
Later, the shielding layer (1031,1033) in the first device area can be removed by selective etch such as RIE.Such as
(Figure 22 (a) is top view to Figure 22 (a) -22 (c), and Figure 22 (b) is the sectional view of the AA ' line along Figure 20 (a), and Figure 22 (c) is along figure
The sectional view of A2A2 ' line in 20 (a)) shown in, in removal process, in order to protect semiconductor layer (to be especially currently exposed to outer
Third semiconductor layer 1039), photoresist 1041 can be formed in the second device area to cover third semiconductor layer.It is going
After shielding layer, this photoresist 1041 can be removed.
In accordance with an embodiment of the present disclosure, transition zone 1027,1037 and the first semiconductor layer 1005 can be removed, leaves second
At least part of semiconductor layer 1029 and third semiconductor layer 1039 is (for example, its side is as shown in Figure 22 (b), 22 (c)
The lateral section of arranged on left and right sides) it is used as fin.
For this purpose, can be as shown in Figure 23 (a) and 23 (b) (sectional views for corresponding respectively to Figure 22 (b) He 22 (c)), it can be with
Dielectric layer 1043 is for example formed by deposit in the structure shown in Figure 22 (a) -22 (c) (after removal photoresist 1041),
And the dielectric layer 1043 is etched back, until exposing the second semiconductor layer 1029 and third semiconductor layer 1039.Before eatch-back,
Planarization process can be carried out to dielectric layer 1043 and for example chemically-mechanicapolish polish (CMP).Alternatively, planarization process can be with second
Semiconductor layer 1029 and third semiconductor layer 1039 are terminal, in this way without being further etched back.For example, dielectric layer 1043 can
To include oxide (for example, silica).
In this example, the thickness of transition zone 1027 and 1037 is roughly the same, and the second semiconductor layer 1029 and third half
The thickness of conductor layer 1039 is roughly the same.It therefore, can be to the first and second devices in the operation shown in Figure 23 (a) and 23 (b)
Part region is handled together.But the present disclosure is not limited thereto.For example, the size of transition zone 1027 and 1037 and/or the second half
Conductor layer 1029 and third semiconductor layer 1039 there may be differences.It in this case, can be respectively to the first and second devices
Part region is handled.
Then, it as shown in Figure 24 (a) and 24 (b) (sectional views for corresponding respectively to Figure 23 (a) He 23 (b)), can remove
The layer structure of first semiconductor layer, 1005 top.For example, can by RIE (may be selected that while can make transition zone 1027,
1037 and second semiconductor layer 1029, third semiconductor layer 1039 etch recipe), be etched back transition zone 1027,1037 and
Second semiconductor layer 1029, third semiconductor layer 1039, until exposing the first semiconductor layer 1005.In this way, in dielectric layer
In 1043, due to this eatch-back, and groove is formd.The mask layer of side wall form can be formed on the side wall of this groove
1045.For example, mask layer 1045 can be by substantially one layer of nitride layer of conformal deposition (thickness be, for example, about 3~15nm), so
RIE is carried out to the nitride layer afterwards and leaves its longitudinally extending portion to remove its lateral extension portions, thus in groove
Side wall 1045 is formed on wall.Here, can to cover the second semiconductor layer 1029, third semiconductor layer 1039 respective for side wall 1045
At least partially, without covering the first semiconductor layer 1005 and transition zone 1027,1037.This generation type of mask layer 1045
The side wall of mask layer 1045 is allowed to be self-aligned to the second semiconductor layer 1029, the respective side wall of third semiconductor layer 1039.
Then, it as shown in Figure 25 (a) and 25 (b) (sectional views for corresponding respectively to Figure 24 (a) He 24 (b)), can be etched back
(for example, passing through wet etching or vapor etch) dielectric layer 1043.Here, dielectric layer 1043 can be etched back as top surface
Close to but above the second semiconductor layer, the respective bottom surface of third semiconductor layer.For example, the top surface of dielectric layer 1043 is the second half
Between conductor layer, the respective bottom surface of third semiconductor layer and the bottom surface of corresponding transition zone 1027,1037.This is to reduce electricity
Difference in height on the top surface of dielectric layer 1043 is (for example, be located at the second semiconductor layer 1029, third semiconductor layer 1039 respectively lower section
The top surface of part and the top surface of rest part between difference in height), can then to obtain top surface substantially in sustained height
Separation layer.
Then, as (Figure 26 (c) is top view to Figure 26 (a) -26 (c), and Figure 26 (a) is the section of the AA ' line along Figure 26 (c)
Figure, Figure 26 (b) is the sectional view of the A2A2 ' line along Figure 26 (c)) shown in, can use mask layer 1045 to semiconductor layer (including
First semiconductor layer 1005, transition zone 1027,1037 and the second semiconductor layer 1029, third semiconductor layer 1039) it is selected
Selecting property etching such as RIE.In this way, the two sides up and down of the second semiconductor layer 1029 are fully opened, similarly third semiconductor layer
1039 two sides up and down are fully opened.It is then also possible to which further eatch-back is such as RIE dielectric layer 1043, to make it below the
Two semiconductor layers 1029, the respective bottom surface of third semiconductor layer 1039.Due on the top surface of dielectric layer 1043 as described above
Difference in height is decreased, thus further the top surface of eatch-back rear dielectric layer 1043 can be located substantially at identical height (in addition to
Respectively except the part of lower section, which can be with the second semiconductor layer for second semiconductor layer 1029, third semiconductor layer 1039
1029, the respective bottom surface of third semiconductor layer 1039 connects).The dielectric layer 1043 can serve as separation layer.It is then possible to go
Except mask layer 1045 (the case where being shown in Figure 26 (c) after removing the mask layer).
As shown in Figure 26 (c), the second semiconductor layer 1029 is in " Π " type, and third semiconductor layer 1039 is in " Π " type that falls,
They constitute close-shaped together.It note that in Figure 26 (c), for convenience only, do not show that the residual of support portion.It can
To cut off this close-shaped second and third semiconductor layer, to form isolated fin.For example, as shown in figure 27, it can be with
The second semiconductor layer 1029 and the respective middle part of third semiconductor layer 1039 are covered using mask (for example, photoresist) 1047, and
Expose its end (ends of two sides up and down in figure).It is then possible to the second semiconductor layer 1029 and third semiconductor layer 1039
Carry out selective etch such as RIE.It is gone in this way, the second semiconductor layer 1029 and third semiconductor layer 1039 are exposed to outer end
It removes, thus isolated fin, as shown in Figure 28 (a).Figure 28 (b) is the sectional view of the AA ' line along Figure 28 (a), Figure 28 (c)
It is the sectional view of the A2A2 ' line along Figure 28 (a).For a pair of of fin in left side in Figure 28 (b) or Figure 28 (c), they are along identical
The first semiconductor layer 1005 sidewall growth, therefore they generally run parallel to one another.As noted previously, as they are from phase
Same the first semiconductor layer 1005 growth, therefore they can be mirrored on crystal structure relative to the middle line between them
Symmetrically.A pair of of fin on right side is same.
In this respect it is to be noted that the second semiconductor layer 1029 and third semiconductor layer 1039 can not be cut off, but still
So retain the shape as shown in Figure 26 (c).In this case, based on left side a pair of fin-shaped at the source/drain region of device connect each other
Connect, based on right side a pair of fin-shaped at the source/drain region of device be connected to each other.
In addition, in combining operation shown in Figure 27, each other by the second semiconductor layer 1029 and third semiconductor layer 1039
Isolation.But the present disclosure is not limited thereto, they can also be remained attached to together according to circuit design.
After forming fin by above-mentioned processing, the grid intersected with fin can be formed and stacked, and form final semiconductor
Device (for example, FinFET).For example, this can be carried out as follows.
Specifically, as shown in Figure 29 (a) and 29 (b) (sectional views for corresponding respectively to Figure 28 (b) He 28 (c)), Ke Yi
It is sequentially formed on separation layer 1043 and sacrifices gate dielectric layer 1049 and sacrificial gate conductor layer 1051.For example, sacrificing gate dielectric layer 1049
It may include the oxide with a thickness of about 2~5nm (for example, SiO2Or GeO2), sacrificial gate conductor layer 1051 may include polycrystalline
Silicon.Planarization process such as chemically mechanical polishing (CMP) can be carried out to sacrificial gate conductor layer 1051.
Then, as (Figure 30 (a) is top view to Figure 30 (a) -30 (c), and Figure 30 (b) is the section of the AA ' line along Figure 30 (a)
Figure, Figure 30 (c) is the sectional view of the A2A2 ' line along Figure 30 (a)) shown in, gate dielectric layer can will be sacrificed for example, by photoetching
1049 and sacrificial gate conductor layer 1051 be patterned into sacrificial gate stacking.Here, show the sacrificial gate that intersects with fin 1029 stack with
And the sacrificial gate intersected with fin 1039 stacks.Depending on the layout that sacrificial gate stacks can be designed according to device.
It is patterned that Figure 30 (a) -30 (c) shows sacrificial gate conductor layer 1049, and sacrifice gate dielectric layer 1051 not yet by
The case where composition.It can be mask with the sacrificial gate conductor layer 1051 of composition, be patterned to gate dielectric layer 1049 is sacrificed.
After forming sacrificial gate and stacking, such as it can be stacked as mask with sacrificial gate, carry out haloing (halo) injection and prolong
Stretch area (extension) injection.Next, grid side wall (for example, nitride) can be formed on the side wall that sacrificial gate stacks.So
Afterwards, it can be stacked using sacrificial gate and grid side wall is mask, carry out source/drain (S/D) injection.Then, annealing, activation injection can be passed through
Ion, form source/drain in fin 1029,1039 to stack two sides (in the top view of Figure 30 (a) up and down two sides) in sacrificial gate
Area.In the case where CMOS, different injections can be carried out (for example, carrying out N-shaped note to fin 1029 to fin 1029 and 1039 respectively
Enter, p-type injection is carried out to fin 1039).When injecting to one of fin, another fin can be covered (for example, passing through photoetching
Glue).
Later, interlevel dielectric layer 1053 (for example, oxide) can be formed.Interlevel dielectric layer 1053 can be carried out
Planarization process such as CMP, CMP can stop at grid side wall, to expose sacrificial gate conductor layer 1051, such as Figure 31 (a) and 31 (b)
Shown (corresponding respectively to the sectional view of Figure 30 (b) He 30 (c), and for convenience's sake, grid side wall is not shown).Choosing can be passed through
Selecting property etching, removal sacrificial gate conductor layer 1051 and sacrifice gate dielectric layer 1049.Then, due to 1051 He of sacrificial gate conductor layer
Sacrifice gate dielectric layer 1049 and in the grid slot that is left on the inside of grid side wall, can fill gate dielectric layer (for example, high-K gate dielectric) and
Grid conductor layer (for example, metal gate conductor) is stacked with forming final grid.Here, (right respectively as shown in Figure 32 (a) and 32 (b)
Grid side wall should be not shown in Figure 31 (a) and 31 (b) sectional view, and for convenience's sake), for the first device, gate dielectric layer
1055 and grid conductor layer 1057 may include material suitable for n-type device；For the second device, gate dielectric layer 1059 and grid conductor
Layer 1061 may include the material suitable for p-type device.In the case where high-K gate dielectric/metal gate conductor, in gate dielectric layer and grid
Work function regulating course (not shown) can also be formed between conductor layer.
Those skilled in the art will know that various ways come with fin for basic making devices, herein for the work after formation fin
Skill repeats no more.
In this way, just having obtained the semiconductor devices of the embodiment.As shown in Figure 32 (a) and 32 (b), which can
To include the fin 1029,1039 being spaced with substrate 1001.In these fins, at least a pair of adjacent fin is (for example, left side in figure
A pair of of fin or right side a pair of of fin) can be arranged along the direction for being roughly parallel to substrate surface, be separated from each other substantially flat
Row extends, and is substantial mirror symmetry on crystal structure relative to the middle line between them.In addition, this can close fin
It is symmetrical in being approximately perpendicular to substrate surface and passing through the straight line on substrate in the middle part of complementary protuberance.
Each grid, which are stacked, constitutes corresponding device such as N-shaped or p-type FinFET with corresponding fin (1029,1039).According to device
Design, these devices can be connected (for example, being interconnected by metal) or be isolated.As shown, semiconductor devices can be with
Including the semiconductor layer 1029 or 1039 being spaced with substrate 1001, the fin of the device is served as.In addition, the device further includes isolation
Layer 1043 and the grid for intersect with fin (1029,1039) of being formed on separation layer 1041 stacking (1055,1057 or 1059,
1061)。
In this embodiment, support portion is not removed intentionally.But the present disclosure is not limited thereto.Support portion can also be chosen
Selecting property (at least partly) removal (for example, after forming grid and stacking), space then for example can be by it caused by removal
He fills at dielectric layer.
In the embodiment above, the different piece of the same seed layer formed by same fin structure is respectively used to p-type
Device and n-type device, but the present disclosure is not limited thereto.For example, the device of a seed type such as p-type can be formed based on same seed layer
Part, and the device of another type such as N-shaped can be formed based on another seed layer.Certainly, the device formed based on same seed layer
Not limited to, can be less or more in 2.
In the embodiment above, support portion is formd in the middle part of the first semiconductor layer, but the present disclosure is not limited thereto,
Support portion can be formed at for example any side end in other positions of the first semiconductor layer or both side ends.
In the embodiment above, it is described by taking FinFET as an example, but the present disclosure is not limited thereto.The technology of the disclosure can
To be suitable for various semiconductor devices, partly led in particular for using high mobility material such as Ge, SiGe, III-V compound
Semiconductor devices of body material etc., such as various photoelectric devices such as photodiode, laser diode (LD) etc..For example, can be with
Pn-junction is formed by carrying out corresponding doping to nano wire, to form diode.Those skilled in the art will know that various modes are come
Various semiconductor devices are manufactured based on nano wire.
In the embodiment above, in growth regulation two/third semiconductor layer, unfilled first semiconductor layer 1005 and substrate
Interval 1021 between 1001.But the present disclosure is not limited thereto.For example, replacing combining operation described in Figure 18 (a) above, such as
Shown in Figure 33, the growth of transition zone 1027 and the second semiconductor layer 1029 can control, so that from the first semiconductor layer 1005
1027 bottom surface of transition zone the second semiconductor layer 1029 grown downwards of growth and the transition zone grown from substrate 1001
The second semiconductor layer 1029 that 1027 top surfaces are grown up is bonded to each other, so that interval 1021 disappears.Similarly, instead of tying above
Closing operation described in Figure 21 can control the growth of transition zone 1037 and the second semiconductor layer 1039 as shown in figure 34, so that from
Third semiconductor layer 1039 that 1037 bottom surface of transition zone grown on first semiconductor layer 1005 is grown downwards and from substrate
The third semiconductor layer 1039 that 1037 top surface of transition zone grown on 1001 is grown up is bonded to each other, so that interval 1021 disappears
It loses.
Next, can be with separation layer 1043 between forming layer, and mask 1045 is formed, such as Figure 35 (a), 35 (b), 36 (a), 36
(b) shown in.For these operations, the description of above combination Figure 23 (a), 23 (b), 24 (a), 24 (b) may refer to.
Likewise it is possible to remove transition zone 1027,1037 and the first semiconductor layer 1005, the second semiconductor layer 1029 is left
At least part with third semiconductor layer 1039 is as fin.
For this purpose, mask layer 1045 can be can use to semiconductor layer (including the first half as shown in Figure 37 (a) and 37 (b)
Conductor layer 1005, transition zone 1027,1037 and the second semiconductor layer 1029, third semiconductor layer 1039) carry out selective quarter
Erosion such as RIE.In this way, the two sides up and down of the second semiconductor layer 1029 are fully opened, similarly third semiconductor layer 1039 is upper
Lower two sides are fully opened.It is this to etch at the surface that for example may proceed to substrate 1001 or in substrate 1001.
Later, separation layer can be formed.For example, can deposited oxide in the structure shown in Figure 37 (a) and 37 (b),
The oxide is sufficiently thick.It is then possible to carry out planarization process such as CMP to oxide, CMP can stop at mask layer 1045.
It is then possible to be etched back to oxide (including the dielectric layer 1043 formed before), so that the oxide after eatch-back is (still
Labeled as at least part for 1043) exposing semiconductor layer 1029,1039, for use as the fin of device, such as Figure 38 (a) and 38 (b)
It is shown.It is then possible to remove mask layer 1045.
It is generally desirable to second/third the semiconductor layer grown downwards and second/third semiconductor layer for growing up it
Between combination interface be not in device channel, to avoid leakage that may be present.Therefore, the top surface of separation layer 1043 can be high
In the combination interface.
Then, can operation as described above handled.In this way, obtaining device shown in Figure 39 (a) and 39 (b)
Part.The device is substantially the same with device shown in Figure 32 (a) and 32 (b), but fin 1029,1039 passes through corresponding semiconductor
Layer is connected to substrate 1001, to help to radiate.
It can be applied to various electronic equipments according to the semiconductor devices of the embodiment of the present disclosure.For example, multiple by integrating
Such semiconductor devices and other devices (for example, transistor etc. of other forms), can form integrated circuit (IC), and
Thus electronic equipment is constructed.Therefore, the disclosure additionally provides a kind of electronic equipment including above-mentioned semiconductor device.Electronic equipment
Can also include and the components such as the display screen of integrated circuit cooperation and the wireless transceiver cooperated with integrated circuit.This electricity
Sub- equipment such as smart phone, tablet computer (PC), personal digital assistant (PDA) etc..
In accordance with an embodiment of the present disclosure, a kind of manufacturing method of chip system (SoC) is additionally provided.This method may include
The method of above-mentioned manufacturing semiconductor devices.Specifically, a variety of devices can be integrated on chip, wherein at least some are according to this
Disclosed method manufacture.
In the above description, the technical details such as composition, the etching of each layer are not described in detail.But
It will be appreciated by those skilled in the art that can be by various technological means, come layer, the region etc. for forming required shape.In addition, being
Formation same structure, those skilled in the art can be devised by and process as described above not fully identical method.
In addition, although respectively describing each embodiment above, but it is not intended that the measure in each embodiment cannot be advantageous
Ground is used in combination.
Embodiment of the disclosure is described above.But the purpose that these embodiments are merely to illustrate that, and
It is not intended to limit the scope of the present disclosure.The scope of the present disclosure is limited by appended claims and its equivalent.This public affairs is not departed from
The range opened, those skilled in the art can make a variety of alternatives and modifications, these alternatives and modifications should all fall in the disclosure
Within the scope of.
Claims (35)
1. a kind of method of manufacturing semiconductor devices, comprising:
Be formed on the substrate the first fin structure and the second fin structure, the first fin structure be stacked on the second fin structure it
On；
The support portion to support the first fin structure is formed on the substrate；
The second fin structure is at least partly removed close to the part of the first fin structure bottom, so that the first fin structure is at least
A part is mutually separated with the second fin structure；
Using the first part in at least part of the first fin structure as seed layer growth regulation semi-conductor layer, and with first
Second part in at least part of fin structure is two semiconductor layer of seed layer growth regulation；
In at least partly longitudinal extent of the first fin structure, the first fin structure is removed, and in the first fin structure
The first semiconductor layer and the second semiconductor layer are cut off respectively away from one side of substrate and close to one side of substrate.
2. according to the method described in claim 1, wherein, in growth regulation semi-conductor layer and/or the second semiconductor layer, making
Gap between the corresponding portion and substrate of one fin structure is filled.
3. method according to claim 1 or 2, further includes: in the first semiconductor layer of cutting and the second semiconductor layer at least
End of one semiconductor layer in the longitudinal extension of the first fin structure, so that the semiconductor layer is divided into opposite to each other
Two parts.
4. according to the method described in claim 3, wherein, described two parts of the semiconductor layer edge is approximately perpendicular to lining
The direction of bottom surface extends.
5. method according to claim 1 or 2, wherein the first fin structure of removal and cutting first/second semiconductor layer
The step of include:
Dielectric layer is formed on the substrate, eatch-back is carried out to the dielectric layer until exposing first/second semiconductor layer；
First/second semiconductor layer is etched back, to expose the first fin structure；
Mask layer is formed on first/second semiconductor layer, is exposed with covering at least part of first/second semiconductor layer
First fin structure；And
Using the mask layer, the first fin structure of selective etch and first/second semiconductor layer.
6. according to the method described in claim 5, wherein, forming mask layer includes:
Side wall form is formed on the inner wall of the groove formed in the dielectric layer due to eatch-back first/second semiconductor layer
Mask layer.
7. method according to claim 1 or 2, further includes:
Transition zone is grown on the first fin structure, wherein first/second semiconductor layer is grown on the transition zone, and
Wherein, the step of the first fin structure of removal and cutting first/second semiconductor layer further include: described at least partly vertical
Into expanded range, transition zone is further removed.
8. according to the method described in claim 7, wherein, removing the first fin structure and cutting off first/second semiconductor layer
Step includes:
Dielectric layer is formed on the substrate, eatch-back is carried out to the dielectric layer until exposing first/second semiconductor layer；
First/second semiconductor layer and transition zone are etched back, to expose the first fin structure；
Mask layer is formed on first/second semiconductor layer, is exposed with covering at least part of first/second semiconductor layer
Transition zone and the first fin structure；And
Utilize the mask layer, the first fin structure of selective etch, transition zone and first/second semiconductor layer.
9. according to the method described in claim 8, wherein, forming mask layer includes:
Side is formed on the inner wall of the groove formed in the dielectric layer due to eatch-back first/second semiconductor layer and transition zone
The mask layer of wall form.
10. according to the method described in claim 1, wherein,
It removes the first fin structure and includes: the step of cutting off first/second semiconductor layer
Dielectric layer is formed on the substrate, eatch-back is carried out to the dielectric layer until exposing first/second semiconductor layer；
First/second semiconductor layer is etched back, to expose the first fin structure；
Mask layer is formed on first/second semiconductor layer, is exposed with covering at least part of first/second semiconductor layer
First fin structure；And
Using the mask layer, the first fin structure of selective etch and first/second semiconductor layer；
After forming mask layer and before selective etch, this method further include:
It is etched back dielectric layer, but its top surface is still higher than the bottom surface of first/second semiconductor layer.
11. according to the method described in claim 1, wherein, further includes:
Transition zone is grown on the first fin structure, wherein first/second semiconductor layer is grown on the transition zone, and
Wherein, the step of the first fin structure of removal and cutting first/second semiconductor layer further include: described at least partly vertical
Into expanded range, transition zone is further removed；
After forming mask layer and before selective etch, this method further include:
It is etched back dielectric layer, but its top surface is still higher than the bottom surface of first/second semiconductor layer.
12. method described in 0 or 11 according to claim 1, wherein be etched back dielectric layer and be lower than and the first/for its top surface
The bottom surface of the first fin structure or transition zone that two semiconductor layers are in contact.
13. according to the method described in claim 2, wherein,
It removes the first fin structure and includes: the step of cutting off first/second semiconductor layer
Dielectric layer is formed on the substrate, eatch-back is carried out to the dielectric layer until exposing first/second semiconductor layer；
First/second semiconductor layer is etched back, to expose the first fin structure；
Mask layer is formed on first/second semiconductor layer, is exposed with covering at least part of first/second semiconductor layer
First fin structure；And
Using the mask layer, the first fin structure of selective etch and first/second semiconductor layer；
Selective etch proceeds on the surface of substrate or proceeds in substrate.
14. according to the method described in claim 2, wherein, further includes:
Transition zone is grown on the first fin structure, wherein first/second semiconductor layer is grown on the transition zone, and
Wherein, the step of the first fin structure of removal and cutting first/second semiconductor layer further include: described at least partly vertical
Into expanded range, transition zone is further removed；
Wherein, selective etch proceeds on the surface of substrate or proceeds in substrate.
15. method according to claim 1 or 2, further includes:
Separation layer is formed on the substrate；And
The first grid stacking intersected with the first semiconductor layer of cutting and the second semiconductor with cutting are formed on separation layer
The second gate stack of layer intersection.
16. according to the method described in claim 1, wherein, the second fin structure includes sacrificial layer formed on a substrate, first
Fin structure includes the semiconductor layer being stacked on sacrificial layer.
17. according to the method for claim 16, wherein at least partly remove the second fin structure close to the first fin structure
The part of bottom includes: removal sacrificial layer.
18. according to the method described in claim 1, wherein, forming support portion includes:
Stratified material is formed on the substrate for being formed with the first and second fin structures, and by the way that the stratified material to be patterned into
Connect the surface of the first and second fin structures physically to form support portion.
19. according to the method for claim 18, wherein forming support portion includes:
Form stratified material on the substrate for being formed with the first and second fin structures, and by by the stratified material be patterned into from
Substrate surface extends to the surface of the first fin structure and therefore physically connect the first fin structure with substrate, to be formed
Support portion.
20. according to the method for claim 19, wherein form stratified material and include: to its composition
Forming stratified material makes it cover the first fin structure, the second fin structure and substrate surface, and forms mask to cover
A part of stratified material, wherein in the direction perpendicular to the first and second fin structure longitudinal extensions, mask is first
With the range for extending beyond the first and second fin structures above the second fin structure；And in the vertical of the first and second fin structures
To on extending direction, mask covers the longitudinal extent of the first and second fin structures above the first and second fin structures
Only a part；
Not shielded stratified material part is removed by selective etch；And
Remove mask.
21. according to the method for claim 20, wherein forming mask includes:
Mask is set to cover the first and second fin structures along the middle part of its longitudinal extension.
22. according to the method for claim 20, wherein after removing the mask, this method further include:
The tip portion of selective removal support portion, to expose top surface and the partial sidewall of the first fin structure.
23. according to the method described in claim 1, wherein, the side of the first semiconductor layer is (111) crystal face or (110) crystal face.
24. a kind of semiconductor devices, comprising:
Substrate；
At least two fin formed on a substrate, wherein at least a pair of adjacent fin-shaped at least two fin
Portion is along the direction arrangement for being roughly parallel to substrate surface, and be separated from each other substantially parallel extension, and relative between them
Line is substantial mirror symmetry on crystal structure, and each fin includes the first semiconductor layer and the along its longitudinal extension
Two semiconductor layers.
25. semiconductor devices according to claim 24, wherein the first semiconductor layer in fin is through identical material
Semiconductor layer is connected to substrate, and the second semiconductor layer in fin is connected to substrate through the semiconductor layer of identical material.
26. semiconductor devices according to claim 24, further includes:
Separation layer formed on a substrate, separation layer expose at least part of each fin；And
The grid intersected respectively with the first semiconductor layer of each fin and the second semiconductor layer formed on separation layer stack.
27. semiconductor devices according to claim 25, further includes:
Separation layer formed on a substrate, separation layer expose at least part of each fin；And
The grid intersected respectively with the first semiconductor layer of each fin and the second semiconductor layer formed on separation layer stack.
28. semiconductor devices according to claim 26, wherein fin is spaced with substrate, and separation layer is in fin-shaped
Connect below portion with fin, top surface is lower than the bottom surface of fin at remaining position.
29. semiconductor devices according to claim 27, wherein the top surface of separation layer is higher than fin and half below
Interface between conductor layer.
30. semiconductor devices according to claim 24, wherein the side wall of fin is (111) crystal face or (110) crystal face.
31. semiconductor devices according to claim 24, wherein have protrusion, the pair of adjacent fin-shaped on substrate
Portion is symmetrical about being approximately perpendicular to substrate surface and passing through the straight line in the middle part of the protrusion.
32. semiconductor devices according to claim 26, wherein be formed with material identical as the first semiconductor layer on substrate
Semiconductor layer and material identical as the second semiconductor layer semiconductor layer, the semiconductor layer is on substrate along fin
Longitudinal extension is arranged side by side, and separation layer is formed in the semiconductor layer.
33. the semiconductor devices according to claim 25 or 32, wherein transition semiconductor layers are formed on substrate, wherein
The semiconductor layer is formed on the transition semiconductor layers.
34. a kind of electronic equipment, integrated including being formed as the semiconductor devices as described in any one of claim 24~33
Circuit.
35. electronic equipment according to claim 34, further includes: with the integrated circuit cooperation display and with institute
State the wireless transceiver of integrated circuit cooperation.
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| US20050077553A1 (en) * | 2003-10-14 | 2005-04-14 | Kim Sung-Min | Methods of forming multi fin FETs using sacrificial fins and devices so formed |
| CN101142686A (en) * | 2005-01-28 | 2008-03-12 | Nxp股份有限公司 | Method of fabricating a FET |
| CN105609560A (en) * | 2015-12-07 | 2016-05-25 | 中国科学院微电子研究所 | Semiconductor device having high quality epitaxial layer and method of manufacturing the same |
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