CN105609506B - Separate type flash memory in grating structure - Google Patents
Separate type flash memory in grating structure Download PDFInfo
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- CN105609506B CN105609506B CN201610055047.7A CN201610055047A CN105609506B CN 105609506 B CN105609506 B CN 105609506B CN 201610055047 A CN201610055047 A CN 201610055047A CN 105609506 B CN105609506 B CN 105609506B
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- floating boom
- grid
- flash memory
- control gate
- separate type
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- 238000007667 floating Methods 0.000 claims abstract description 68
- 230000008878 coupling Effects 0.000 claims abstract description 13
- 238000010168 coupling process Methods 0.000 claims abstract description 13
- 238000005859 coupling reaction Methods 0.000 claims abstract description 13
- 239000000463 material Substances 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 9
- 230000005641 tunneling Effects 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- VDGJOQCBCPGFFD-UHFFFAOYSA-N oxygen(2-) silicon(4+) titanium(4+) Chemical group [Si+4].[O-2].[O-2].[Ti+4] VDGJOQCBCPGFFD-UHFFFAOYSA-N 0.000 claims 1
- 230000007423 decrease Effects 0.000 abstract description 5
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 239000004065 semiconductor Substances 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000008859 change Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 230000009471 action Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000004064 recycling Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Non-Volatile Memory (AREA)
Abstract
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of separate type flash memory in grating structure, the lower surface for being located at the control gate on the horizontal component of L-shaped wordline grid by setting unit makes control gate and floating boom have the longitudinal overlapping region in part less than the upper surface of floating boom, to increase the coupling area of control gate and floating boom, to improve the coefficient of coup of the control gate to floating boom, and then improve flash memory write efficiency；And the turning that erasing grid are closed on by the way that floating boom is arranged is fillet so that the phenomenon that capable of forming the higher tunnel oxide of thickness homogeneous quality in follow-up film forming, improve erasing decline；It is located on the floating boom of part so that erasing grid have part of horizontal overlapping region with floating boom, to increase the coupling area of erasing grid and floating boom, to improve the coefficient of coup of the erasing grid to floating boom by the way that the horizontal component of the erasing grid of T-shaped structure is arranged simultaneously.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of separate type flash memory in grating structures.
Background technology
Currently, in the flash memory of separate type grid (split gate) structure, (program) efficiency and erasing speed, which is written, is
Two important quality index.Control gate (Control gate) is to the coefficient of coup of floating boom (floating gate) to write-in
Speed plays a crucial role；Under the same operating conditions, the higher coefficient of coup can bring faster writing speed；
And the dielectric strength of the tunnel oxide between floating boom and erasing grid is most important on the decline influence for wiping performance.
Existing technique realizes coupling of the control gate to floating boom based on traditional capacitance structure, i.e. bottom crown on plane
Effect, required electricity when to floating boom offer source thermoelectron injection (Source-side hot electron injection)
Pressure.Coupling efficiency (coefficient) is limited to pole plate spacing, coupling area and intermediate medium dielectric constant, is keeping spacing and dielectric normal
In the case of number, it is difficult to improve the coefficient of coup.
In the flash memory of separate type grid structure, erasing is by polysilicon between floating boom and erasing grid to one promise of polysilicon fowler
De Haimu electronics tunneling effect (poly-to-poly Fowler-Nordheim electron tunneling) realizes, should
Physical phenomenon is happened at floating boom and wipes the turning (corner) of grid contact.When erasing (Erase) under electric field action, floating boom turns
Electronics tunneling effect (electron tunneling) occurs at angle, tunnel oxide will be passed through by wiping electronics every time, if
Oxide layer is intrinsic second-rate, then under forceful electric power field action, tunneling oxide can be damaged after repeatedly recycling, and wipes
Except speed can gradually slack-off (Erase degradation).Under current structural model, floating boom corner shape is sharper
It is sharp, it in the subsequent process, be easy to cause tunnel oxide quality of forming film and thickness evenness is poor, and can be formed in erasing
Strong electric damages oxide layer, causes the decline of erasing speed.These are all that those skilled in the art do not expect to see.
Invention content
In view of the above problems, the invention discloses a kind of separate type flash memory in grating structures, including：
Active area and drain region is arranged in substrate；
Grid are wiped, are set on the source region；
Grid dividing structure, the substrate being set between the source region and drain region, the grid dividing structure include floating boom,
Control gate and L-shaped wordline grid including a horizontal component and a vertical component, and the horizontal component of the L-shaped wordline grid
Upper surface be less than the floating boom upper surface；
Wherein, the control gate is set on the horizontal component of the floating boom and the L-shaped wordline grid, and part is located at
The lower surface of the control gate on the horizontal component of the L-shaped wordline grid makes the control less than the upper surface of the floating boom
Grid processed have the longitudinal overlapping region in part with the floating boom, to increase the coupling area of the control gate and the floating boom.
Above-mentioned separate type flash memory in grating structure, wherein thickness of the horizontal component of the L-shaped wordline grid than the control gate
It is 180~220 angstroms thin.
Above-mentioned separate type flash memory in grating structure, wherein the material of the L-shaped wordline grid is polysilicon or metal.
Above-mentioned separate type flash memory in grating structure, wherein the floating boom is cube structure, and the floating boom closes on the erasing
The turning of grid is set as fillet.
Above-mentioned separate type flash memory in grating structure, wherein be provided with tunnel oxygen between the grid dividing structure and the erasing grid
Change layer.
Above-mentioned separate type flash memory in grating structure, wherein be provided with gate medium between the L-shaped wordline grid and the substrate
Layer.
Above-mentioned separate type flash memory in grating structure, wherein the material of the gate dielectric layer is silica or high-k
Material.
Foregoing invention has the following advantages that or advantageous effect：
The invention discloses a kind of separate type flash memory in grating structures, and the horizontal component of L-shaped wordline grid is located at by setting unit
On the lower surface of control gate make control gate and floating boom that there is the longitudinal overlapping region in part less than the upper surface of floating boom, to increase
The coupling area for adding control gate and floating boom, to improve coefficient of coup CR (coupling ratio) of the control gate to floating boom,
And then improve flash memory write efficiency；And the turning that erasing grid are closed on by the way that floating boom is arranged is fillet so that in follow-up film forming
The phenomenon that higher tunnel oxide of thickness homogeneous quality can be formed, improve erasing decline.
Description of the drawings
Upon reading the detailed description of non-limiting embodiments with reference to the following drawings, the present invention and its feature, outer
Shape and advantage will become more apparent.Identical label indicates identical part in whole attached drawings.Not can according to than
Example draws attached drawing, it is preferred that emphasis is shows the purport of the present invention.
Fig. 1 is the structural schematic diagram of separate type flash memory in grating structure in the embodiment of the present invention one；
Fig. 2 is the structural schematic diagram of separate type flash memory in grating structure in the embodiment of the present invention two.
Specific implementation mode
The present invention is further illustrated with specific embodiment below in conjunction with the accompanying drawings, but not as the limit of the present invention
It is fixed.
Embodiment one：
As shown in Figure 1, the present embodiment is related to a kind of separate type flash memory in grating structure, which includes setting active area 22
With the substrate 1 in drain region 21, the erasing grid 7 being set on source region 22, it is set on the substrate 1 between source region 22 and drain region 21
Grid dividing structure, and the grid dividing structure includes floating boom 5, control gate 6 and the L including a horizontal component and a vertical component
Shape wordline grid 4, and the upper surface of the horizontal component of L-shaped wordline grid 4 is less than the upper surface of floating boom；Wherein, control gate 6 is set to floating
On the horizontal component of grid 5 and L-shaped wordline grid 4, and part is located under the control gate 6 on the horizontal component of L-shaped wordline grid 4
The upper surface that surface is less than floating boom 5 makes control gate 6 and floating boom 5 have part longitudinal overlapping region (i.e. 6 part of control gate longitudinal direction
Surround floating boom 5), to increase the coupling area of control gate 6 and floating boom 5, so as to improve coupled systemes of the control gate 6 to floating boom 5
Number, and then flash memory write efficiency can be improved, wherein L-shaped wordline grid, which are arranged, can reduce the thickness of 4 horizontal component of wordline grid
Degree, grid 6 and floating boom 5 form the longitudinal overlapping region Free up Memory in part in order to control.In embodiment, compared with traditional technology, control
Grid 6 and floating boom 5 processed are constant in the area of horizontal plane.
On this basis, further, the horizontal component of above-mentioned L-shaped wordline grid 4 is thinner than the thickness of control gate 6 by 180~220
Angstrom (such as 180 angstroms, 190 angstroms, 200 angstroms or 220 angstroms etc.).
In a preferred embodiment of the invention, the material of above-mentioned L-shaped wordline grid 4 is polysilicon or metal.
In a preferred embodiment of the invention, it is provided with gate dielectric layer between above-mentioned L-shaped wordline grid 4 and substrate 1
3。
On this basis, further, the material of gate dielectric layer 3 can be silica, or high-k
Material, so as to optimize threshold voltage (Vt) and significantly reduce selection grid (select gate, abbreviation SG) (the selection
Grid, that is, wordline grid) gate medium leakage current.
In a preferred embodiment of the invention, tunneling oxide layer is provided between above-mentioned grid dividing structure and erasing grid 7
8。
In a preferred embodiment of the invention, the shape of above-mentioned erasing grid 7 can be T shapes.
In a preferred embodiment of the invention, (it could also say that floating boom between above-mentioned grid dividing structure and erasing grid 7
Between 5 and the stacked structure formed of control gate 6 and erasing grid 7) it is provided with tunneling oxide layer 8.
In a preferred embodiment of the invention, the shape of above-mentioned floating boom 5 can be cube structure.
In addition, the present invention increases the coupling area of control gate 6 and floating boom 5, coupled systemes of the control gate to floating boom can be improved
Number, and then the principle for improving flash memory write efficiency is as follows：
1, increase the principle of the coefficient of coup：
Wherein ∈ is constant, and d is pole plate (control gate and floating boom) spacing, CFGFor floating gate capacitance, S is polar plate area, when ∈,
d、CFGWhen being constant, CR values can be increased by changing S.
2, increase the coefficient of coup to improve writing speed principle：
In the flash memory of separate type grid structure, (Source-side hot are injected by source thermoelectron when data are written
Electron injection) it realizes, voltage is must have on floating boom, it is in other external operating conditions identical,
The higher coefficient of coup can bring faster writing speed.
Embodiment two：
As shown in Fig. 2, the present embodiment is roughly the same with embodiment one, differs only in floating boom 5 in the present embodiment and close on wiping
Except the turning of grid 7 is set as fillet so that can form the higher tunnel oxide 8 of thickness homogeneous quality in follow-up film forming, change
The phenomenon that being apt to erasing decline；But round and smooth floating boom pattern makes floating boom 5 and the coupling area wiped between grid 7 become smaller, and makes
Reduce at the coefficient of coup between erasing grid 7 and floating boom 5；In order to make up this loss, meanwhile, it is arranged in the present embodiment and wipes grid
7 shape is the T-shaped structure for including horizontal component and vertical component, and the horizontal component of T-shaped structure is located on part floating boom 5
So that erasing grid 7 have part of horizontal overlapping region with floating boom 5, to increase the coupling area of erasing grid 7 and floating boom 5, to carry
The high coefficients of coup of the erasing grid 7 to floating boom 5.
In the present embodiment, erasing grid 7 with floating boom 5 there is part of horizontal overlapping region can cause control gate 6 and floating boom 5 again
Horizontal overlapping region reduce, and there is the longitudinal overlapping region in part since control gate 6 and floating boom 5 is arranged in the present embodiment,
It can keep the coefficient of coup of the control gate 6 to floating boom 5.
It should be appreciated by those skilled in the art that those skilled in the art are combining the prior art and above-described embodiment can be with
Realize change case, this will not be repeated here.Such change case does not affect the essence of the present invention, and it will not be described here.
Presently preferred embodiments of the present invention is described above.It is to be appreciated that the invention is not limited in above-mentioned
Particular implementation, wherein the equipment and structure be not described in detail to the greatest extent are construed as giving reality with the common mode in this field
It applies；Any technical person familiar with the field, without departing from the scope of the technical proposal of the invention, all using the disclosure above
Methods and technical content many possible changes and modifications are made to technical solution of the present invention, or be revised as equivalent variations etc.
Embodiment is imitated, this is not affected the essence of the present invention.Therefore, every content without departing from technical solution of the present invention, foundation
The technical spirit any simple modifications, equivalents, and modifications made to the above embodiment of the present invention, still fall within the present invention
In the range of technical solution protection.
Claims (7)
1. a kind of separate type flash memory in grating structure, which is characterized in that including：
Active area and drain region is arranged in substrate；
Grid are wiped, are set on the source region；
Grid dividing structure, the substrate being set between the source region and drain region, the grid dividing structure include floating boom, control
Grid and L-shaped wordline grid including a horizontal component and a vertical component, and the horizontal component of the L-shaped wordline grid is upper
Surface is less than the upper surface of the floating boom；
Wherein, the control gate is set on the horizontal component of the floating boom and the L-shaped wordline grid, and part is positioned at described
The lower surface of the control gate on the horizontal component of L-shaped wordline grid makes the control gate less than the upper surface of the floating boom
There is the longitudinal overlapping region in part with the floating boom, to increase the coupling area of the control gate and the floating boom.
2. separate type flash memory in grating structure as described in claim 1, which is characterized in that the horizontal component ratio of the L-shaped wordline grid
The thickness of the control gate is 180~220 angstroms thin.
3. separate type flash memory in grating structure as described in claim 1, which is characterized in that the material of the L-shaped wordline grid is polycrystalline
Silicon or metal.
4. separate type flash memory in grating structure as described in claim 1, which is characterized in that the floating boom is cube structure, and described
The turning that floating boom closes on the erasing grid is set as fillet.
5. separate type flash memory in grating structure as described in claim 1, which is characterized in that the grid dividing structure and the erasing grid it
Between be provided with tunneling oxide layer.
6. separate type flash memory in grating structure as described in claim 1, which is characterized in that the L-shaped wordline grid and the substrate it
Between be provided with gate dielectric layer.
7. separate type flash memory in grating structure as claimed in claim 6, which is characterized in that the material of the gate dielectric layer is titanium dioxide
Silicon or high dielectric constant material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610055047.7A CN105609506B (en) | 2016-01-27 | 2016-01-27 | Separate type flash memory in grating structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610055047.7A CN105609506B (en) | 2016-01-27 | 2016-01-27 | Separate type flash memory in grating structure |
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| CN105609506A CN105609506A (en) | 2016-05-25 |
| CN105609506B true CN105609506B (en) | 2018-09-21 |
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| CN201610055047.7A Active CN105609506B (en) | 2016-01-27 | 2016-01-27 | Separate type flash memory in grating structure |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111415937B (en) * | 2020-05-13 | 2023-04-25 | 上海华虹宏力半导体制造有限公司 | Memory and forming method thereof |
| CN113013255B (en) * | 2021-03-24 | 2024-05-03 | 上海华虹宏力半导体制造有限公司 | Split gate memory and manufacturing method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1096572A1 (en) * | 1999-10-25 | 2001-05-02 | Interuniversitair Microelektronica Centrum Vzw | Electrically programmable and erasable memory device and method of operating same |
| US6563167B2 (en) * | 2001-01-05 | 2003-05-13 | Silicon Storage Technology, Inc. | Semiconductor memory array of floating gate memory cells with floating gates having multiple sharp edges |
| CN102364689A (en) * | 2011-10-20 | 2012-02-29 | 北京大学 | Floating gate structure of flash memory device and manufacturing method for floating gate structure |
| CN104081532A (en) * | 2011-04-29 | 2014-10-01 | 硅存储技术公司 | A high endurance non-volatile memory cell and array |
| CN106298793A (en) * | 2016-09-30 | 2017-01-04 | 上海华虹宏力半导体制造有限公司 | Autoregistration grid flash memory device and manufacture method thereof |
-
2016
- 2016-01-27 CN CN201610055047.7A patent/CN105609506B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1096572A1 (en) * | 1999-10-25 | 2001-05-02 | Interuniversitair Microelektronica Centrum Vzw | Electrically programmable and erasable memory device and method of operating same |
| US6563167B2 (en) * | 2001-01-05 | 2003-05-13 | Silicon Storage Technology, Inc. | Semiconductor memory array of floating gate memory cells with floating gates having multiple sharp edges |
| CN104081532A (en) * | 2011-04-29 | 2014-10-01 | 硅存储技术公司 | A high endurance non-volatile memory cell and array |
| CN102364689A (en) * | 2011-10-20 | 2012-02-29 | 北京大学 | Floating gate structure of flash memory device and manufacturing method for floating gate structure |
| CN106298793A (en) * | 2016-09-30 | 2017-01-04 | 上海华虹宏力半导体制造有限公司 | Autoregistration grid flash memory device and manufacture method thereof |
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| CN105609506A (en) | 2016-05-25 |
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Address after: 430205 No.18, Gaoxin 4th Road, Donghu Development Zone, Wuhan City, Hubei Province Patentee after: Wuhan Xinxin Integrated Circuit Co.,Ltd. Country or region after: China Address before: 430205 No.18, Gaoxin 4th Road, Donghu Development Zone, Wuhan City, Hubei Province Patentee before: Wuhan Xinxin Semiconductor Manufacturing Co.,Ltd. Country or region before: China |