CN105609485B - Anti-fuse one-time programmable memory and implementation method - Google Patents
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- 230000015654 memory Effects 0.000 title claims abstract description 40
- 238000000034 method Methods 0.000 title claims description 27
- 239000004065 semiconductor Substances 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 238000005468 ion implantation Methods 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 9
- 238000007664 blowing Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 13
- 238000002513 implantation Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000004913 activation Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
- H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/18—Auxiliary circuits, e.g. for writing into memory
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
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Abstract
The invention provides an anti-fuse one-time programmable memory, which comprises: the selection unit and the at least two anti-fuse units are positioned in and on the surface of the semiconductor substrate; the semiconductor substrate comprises an active region, and the grid electrode of the selection unit vertically covers part of the active region; the grid electrodes of the at least two anti-fuse units are respectively covered on the other part of the active area; the selection unit shares the same active region with at least two anti-fuse units.
Description
Technical Field
The present invention relates to a memory and an operating method thereof, and more particularly, to an anti-fuse one-time programmable memory and an implementation method thereof.
Background
The non-volatile memory is a memory capable of continuously storing data in the memory after power is turned off, and may be divided into a Read Only Memory (ROM), a one time programmable memory (OTP memory), and a rewritable memory. In addition, as semiconductor memory technology matures, nonvolatile memory devices can be integrated into fabrication processes compatible with Complementary Metal Oxide Semiconductor (CMOS) devices.
For example, in the case of otp memories, they can be classified into fuse type (fuse type) and antifuse type (anti-fuse type). The fuse type otp memory is short-circuited in an unprogrammed state and is open-circuited after programming. On the contrary, the anti-fuse type otp memory is open before being programmed and short after being programmed. In addition, based on the characteristics of the MOS devices in the CMOS fabrication process technology, the antifuse-type otp memory is suitable for integration in the CMOS fabrication process technology.
Referring to appendix 1, FIG. 1 shows a conventional anti-fuse OTP memory, which includes two pipes, a selection unit 300 and an anti-fuse unit. Forming an implantation region 100 on a semiconductor substrate, forming an active region 200 in the implantation region 100, forming a gate region 310 of a selection tube in a partial region of the active region, the gate region 310 of the selection tube being formed with a via hole 320 adapted to be connected to a word line; another via 330 is also formed near the gate region 310 of the select transistor and connected to the bit line. Forming an anti-fuse unit in another partial area of the active area, wherein the anti-fuse unit comprises a gate 410 of the anti-fuse unit and a via 420, and the via 420 is suitable for being connected with a metal layer; the anti-fuse unit further comprises a via 430, and a via 440 connected to the metal layer; the existing anti-fuse one-time programmable memory has larger structural area and also improves the reliability.
Disclosure of Invention
In order to reduce the structural area of a device and improve the reliability of an anti-fuse one-time programmable memory structure, the invention provides an anti-fuse one-time programmable memory, which comprises: the selection unit and the at least two anti-fuse units are positioned in and on the surface of the semiconductor substrate; the semiconductor substrate comprises an active region, and the grid electrode of the selection unit vertically covers part of the active region; the grid electrodes of the at least two anti-fuse units are respectively covered on the other part of the active area; the selection unit and at least two anti-fuse units share the same active region, and the gate oxide layers of the selection unit and the anti-fuse units are formed through the same process step and have the same thickness.
Preferably, the active region is provided with a first via hole near the gate of the selection cell to electrically connect to a bit line; the grid electrode of the selection unit is provided with a second through hole so as to be electrically connected with the word line; the gates of the at least two anti-fuse units are respectively provided with corresponding third through holes so as to be electrically connected with the metal wire.
Preferably, the gates of the at least two anti-fuse cells are parallel and/or perpendicular to the gate of the selection cell, respectively.
Preferably, the method further comprises the following steps: the anti-fuse ion implantation area is positioned in the semiconductor substrate, is positioned in the lower area of the grid of the anti-fuse unit, and has a width larger than that of the active area; the anti-fuse ion implantation region extends out of the periphery of the active region.
The invention also provides a realization method of the anti-fuse one-time programmable memory, the anti-fuse one-time programmable memory comprises a selection unit and at least two anti-fuse units, wherein the selection unit and the at least two anti-fuse units are positioned in and on the surface of the semiconductor substrate; the semiconductor substrate comprises an active region, and the grid electrode of the selection unit vertically covers part of the active region; the grid electrodes of the at least two anti-fuse units are respectively covered on the other part of the active area; the selection unit and at least two anti-fuse units share the same active region; a first through hole is arranged near the grid of the selection unit to be electrically connected with the bit line; the grid electrode of the selection unit is provided with a second through hole so as to be electrically connected with the word line; the grid electrodes of the at least two anti-fuse units are respectively provided with corresponding third through holes so as to be electrically connected with the metal wire;
in the burning process, a first voltage is applied to a grid electrode of the anti-fuse unit, a second voltage is applied to a word line, and a third voltage is applied to a bit line; wherein the first voltage is greater than the second voltage and greater than the third voltage; the selection unit is opened, and the voltage difference between the grid electrode of the anti-fuse unit and the body end is as follows: first voltage-third voltage; blowing the anti-fuse unit;
in the reading process, a fourth voltage is applied to the grid electrode of the anti-fuse unit, a fifth voltage is applied to the word line, a sixth voltage is applied to the bit line, and a first voltage difference exists between the fifth voltage and the sixth voltage to enable the selection unit to be opened; the fourth voltage and the sixth voltage have a second voltage difference.
Preferably, in the burning process, the at least two antifuse units are in a logical or relationship, and only one antifuse unit is required to be burned successfully, so that the burning success rate is improved.
Preferably, the gates of the at least two anti-fuse cells are parallel and/or perpendicular to the gate of the selection cell, respectively.
Preferably, the method further comprises the following steps: the anti-fuse ion implantation area is positioned in the semiconductor substrate, is positioned in the lower area of the grid of the anti-fuse unit, and has a width larger than that of the active area; the anti-fuse ion implantation region extends out of the periphery of the active region.
In addition, the anti-fuse units are in a logic OR mode, when one anti-fuse unit is burnt, the burnt state can be read, and the integral stability is improved.
Drawings
FIG. 1 is a schematic diagram of a prior art antifuse OTP memory;
FIG. 2 is a diagram of an anti-fuse OTP memory according to a first embodiment of the invention;
FIG. 3 is an equivalent circuit diagram of an anti-fuse OTP memory according to an embodiment of the invention;
FIG. 4 is an equivalent circuit diagram of an antifuse array in accordance with an embodiment of the present invention;
FIG. 5 is a diagram illustrating an anti-fuse OTP memory according to a second embodiment of the invention.
FIG. 6 is a diagram of an anti-fuse OTP memory according to a third embodiment of the invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
The invention provides an anti-fuse one-time programmable memory selection unit, at least two anti-fuse units, which are positioned in and on a semiconductor substrate; the semiconductor substrate comprises an active region, and the grid electrode of the selection unit vertically covers part of the active region; the grid electrodes of the at least two anti-fuse units are respectively covered on the other part of the active area; the selection unit and at least two anti-fuse units share the same active region, and the gate oxide layers of the selection unit and the anti-fuse units are formed through the same process step and have the same thickness.
The present invention will be described in detail with reference to the following examples.
First embodiment
Please refer to fig. 2 and fig. 3; FIG. 2 is a diagram of an anti-fuse OTP memory according to a first embodiment of the invention; FIG. 3 is an equivalent circuit diagram of an anti-fuse OTP memory according to an embodiment of the invention;
providing a semiconductor substrate (not labeled), forming an implantation region 100 'in the semiconductor substrate, forming an active region 200' in the semiconductor substrate, wherein the gate 310 'of the selection unit 300' vertically covers a portion of the active region 200 ', and the extension direction of the gate 310' of the selection unit is a first direction. The gate electrode 310 'of the selection unit is formed with a second via hole 320' to be electrically connected to a word line; the active region 200 ' is provided with a first via 330 ' near the gate 310 ' of the selected cell to electrically connect to a bit line. The two anti-fuse units are respectively a first anti-fuse unit 400 ', a second anti-fuse unit 500', a gate 410 'of the first anti-fuse unit and a gate 510' of the second anti-fuse unit respectively cover the other part of the active region and extend along a second direction perpendicular to the first direction; the two anti-fuse units are respectively provided with third through holes 420 ' and 520 ' and connected with metal wires, the selection unit 300 ' shares the same active region 200 ' with the two anti-fuse units, a gate oxide layer (not labeled) of the selection unit 300 ' is further formed between the gate 310 ' of the selection unit 300 ' and the active region 200 ', and a gate oxide layer (not labeled) is further formed between the gates 410 ' and 510 ' of the anti-fuse units and the active region 200 '; the gate oxide layer of the selection unit 300' and the gate oxide layer of the anti-fuse unit are formed through the same process step and have the same thickness; in order to optimize the space of the wiring, the gates of the two anti-fuse cells are perpendicular to the gate of the selection cell.
Second embodiment
Please refer to fig. 5 and fig. 3; FIG. 5 is a diagram illustrating an anti-fuse OTP memory according to a second embodiment of the invention; FIG. 3 is an equivalent circuit diagram of an anti-fuse OTP memory according to an embodiment of the invention;
providing a semiconductor substrate (not labeled), forming an implantation region 100 'in the semiconductor substrate, forming an active region 200' in the semiconductor substrate, wherein the gate 310 'of the selection unit 300' vertically covers a portion of the active region 200 ', and the extension direction of the gate 310' of the selection unit is a first direction. The gate electrode 310 'of the selection unit is formed with a second via hole 320' to be electrically connected to a word line; the active region 200 ' is provided with a first via 330 ' near the gate 310 ' of the selected cell to electrically connect to a bit line. The two anti-fuse units are respectively a first anti-fuse unit 400 ', a second anti-fuse unit 500', a gate 410 'of the first anti-fuse unit and a gate 510' of the second anti-fuse unit respectively cover the other part of the active region and extend along a second direction perpendicular to the first direction; the two anti-fuse units are respectively provided with third through holes and connected with metal wires, and the selection unit 300 'and the two anti-fuse units share the same active region 200'; a gate oxide layer (not labeled) of the selection unit 300 ' is further formed between the gate 310 ' of the selection unit 300 ' and the active region 200 ', and a gate oxide layer (not labeled) is further formed between the gates 410 ' and 510 ' of the anti-fuse unit and the active region 200 '; the gate oxide layer of the selection unit 300' and the gate oxide layer of the anti-fuse unit are formed through the same process step and have the same thickness; in order to optimize the space of the wiring, the gates of the two anti-fuse cells are perpendicular to the gate of the selection cell.
The device further includes an anti-fuse ion implantation region 700 located at the semiconductor substrate, the anti-fuse ion implantation region 700 being located at a lower region of the gates of the first and second anti-fuse cells 400 ' and 500 ', and having a width greater than that of the active region 200 '; the antifuse ion implantation region 700 extends outside the periphery of the active region 200'.
Third embodiment
Please refer to fig. 6 and fig. 3; FIG. 6 is a diagram illustrating an anti-fuse OTP memory according to a third embodiment of the invention; FIG. 3 is an equivalent circuit diagram of an anti-fuse OTP memory according to an embodiment of the invention;
providing a semiconductor substrate (not labeled), forming an implantation region 100 'in the semiconductor substrate, forming an active region 200' in the semiconductor substrate, wherein the gate 310 'of the selection unit 300' vertically covers a portion of the active region 200 ', and the extension direction of the gate 310' of the selection unit is a first direction. The gate electrode 310 'of the selection unit is formed with a second via hole 320' to be electrically connected to a word line; the active region 200 ' is provided with a first via 330 ' near the gate 310 ' of the selected cell to electrically connect to a bit line. The four antifuse cells are the first antifuse cell 400 ', the second antifuse cell 500', the third antifuse cell 900 ', the fourth antifuse cell 1000', respectively; the gate 410 'of the first antifuse unit and the gate 510' of the second antifuse unit cover the other part of the active region respectively and extend in a second direction perpendicular to the first direction, and the extending directions of the gates of the third antifuse unit 900 'and the fourth antifuse unit 1000' are the first direction; the gates of the four anti-fuse cells are respectively formed with a third via hole connected to the metal layer, and the selection cell 300 'and the four anti-fuse cells share the same active region 200'. A gate oxide layer (not labeled) of the selection unit 300 ' is further formed between the gate 310 ' of the selection unit 300 ' and the active region 200 ', and gate oxide layers (not labeled) are further respectively formed between the gates of the four anti-fuse units and the active region 200 '; the gate oxide of the selection cell 300' and the gate oxides of the four anti-fuse cells are formed through the same process step and have the same thickness.
Alternatively, the anti-fuse ion implantation region in the second embodiment may be added on the basis of the third embodiment; in other embodiments, the antifuse cells may be arranged around the first antifuse cell, the second antifuse cell, the third antifuse cell, and the fourth antifuse cell in parallel. In the first, second, and third embodiments, the at least two antifuse units are in a logical or relationship, so that only one antifuse unit needs to be burned successfully, thereby improving the success rate of burning.
Fig. 4 is an equivalent circuit diagram of an antifuse array in accordance with an embodiment of the present invention, and in fig. 4, a dashed box 600 is a read or write antifuse cell, and data can be burned into only a selected cell by appropriate activation, and signals to be read only from the selected antifuse cell.
The invention also provides a realization method of the anti-fuse one-time programmable memory, which is characterized in that the anti-fuse one-time programmable memory comprises a selection unit and at least two anti-fuse units, wherein the selection unit and the at least two anti-fuse units are positioned in and on the surface of a semiconductor substrate; the semiconductor substrate comprises an active region, and the grid electrode of the selection unit vertically covers part of the active region; the grid electrodes of the at least two anti-fuse units are respectively covered on the other part of the active area; the selection unit and at least two anti-fuse units share the same active region; a first through hole is arranged near the grid of the selection unit to be electrically connected with the bit line; the grid electrode of the selection unit is provided with a second through hole so as to be electrically connected with the word line; the gates of the at least two anti-fuse units are respectively provided with corresponding third through holes so as to be electrically connected with the metal wire.
In the burning process, a first voltage is applied to a grid electrode of the anti-fuse unit, a second voltage is applied to a word line, and a third voltage is applied to a bit line; wherein the first voltage is greater than the second voltage and greater than the third voltage; the selection unit is opened, and the voltage difference between the grid electrode of the anti-fuse unit and the body end is as follows: first voltage-third voltage; blowing the anti-fuse unit;
in the reading process, a fourth voltage is applied to the grid electrode of the anti-fuse unit, a fifth voltage is applied to the word line, a sixth voltage is applied to the bit line, and a first voltage difference exists between the fifth voltage and the sixth voltage to enable the selection unit to be opened; a second voltage difference exists between the fourth voltage and the sixth voltage; the burnt and unburnt states can be distinguished by observing the current flow for the corresponding state. The at least two antifuse units are in a logic OR relationship, and only one antifuse unit is required to be burned successfully, so that the burning success rate is improved.
The gates of the at least two anti-fuse cells are parallel and/or perpendicular to the gate of the selection cell, respectively.
The anti-fuse ion implantation area is positioned in the semiconductor substrate, is positioned in the lower area of the grid of the anti-fuse unit, and has a width larger than that of the active area; the anti-fuse ion implantation region extends out of the periphery of the active region.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (4)
1. The method for realizing the anti-fuse one-time programmable memory is characterized in that the anti-fuse one-time programmable memory comprises a selection unit and at least two anti-fuse units, wherein the selection unit and the at least two anti-fuse units are positioned in and on a semiconductor substrate; the semiconductor substrate comprises an active region, and the grid electrode of the selection unit vertically covers part of the active region; the grid electrodes of the at least two anti-fuse units are respectively covered on the other part of the active area; the selection unit and at least two anti-fuse units share the same active region; a first via hole is disposed near the gate of the selection unit to be electrically connected to the bit line; the grid electrode of the selection unit is provided with a second through hole so as to be electrically connected with the word line; the grid electrodes of the at least two anti-fuse units are respectively provided with corresponding third through holes so as to be electrically connected with the metal wire;
in the burning process, a first voltage is applied to a grid electrode of the anti-fuse unit, a second voltage is applied to a word line, and a third voltage is applied to a bit line; wherein the first voltage is greater than the second voltage and greater than the third voltage; the selection unit is opened, and the voltage difference between the grid electrode of the anti-fuse unit and the body end is as follows: first voltage-third voltage; blowing the anti-fuse unit;
in the reading process, a fourth voltage is applied to the grid electrode of the anti-fuse unit, a fifth voltage is applied to the word line, a sixth voltage is applied to the bit line, and a first voltage difference exists between the fifth voltage and the sixth voltage to enable the selection unit to be opened; the fourth voltage and the sixth voltage have a second voltage difference.
2. The method of claim 1, wherein in the programming process, the at least two antifuse units are in a logical or relationship, and only one antifuse unit is required to be programmed successfully, so as to improve programming success rate.
3. The implementation method of the antifuse one-time programmable memory according to claim 1, wherein the gates of the at least two antifuse cells are respectively parallel and/or perpendicular to the gate of the selection cell.
4. The method of claim 1, wherein the antifuse otp memory further comprises: the anti-fuse ion implantation area is positioned in the semiconductor substrate, is positioned in the lower area of the grid of the anti-fuse unit, and has a width larger than that of the active area; the anti-fuse ion implantation region extends out of the periphery of the active region.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US8031506B2 (en) * | 2008-03-21 | 2011-10-04 | Broadcom Corporation | One-time programmable memory cell |
| CN104347637A (en) * | 2013-07-24 | 2015-02-11 | 力旺电子股份有限公司 | Anti-fuse single programmable storage cell and operation method of memory |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US8031506B2 (en) * | 2008-03-21 | 2011-10-04 | Broadcom Corporation | One-time programmable memory cell |
| CN104347637A (en) * | 2013-07-24 | 2015-02-11 | 力旺电子股份有限公司 | Anti-fuse single programmable storage cell and operation method of memory |
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