CN105590893A - Semiconductor device, manufacturing method thereof and electronic device - Google Patents
Semiconductor device, manufacturing method thereof and electronic device Download PDFInfo
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- CN105590893A CN105590893A CN201410559315.XA CN201410559315A CN105590893A CN 105590893 A CN105590893 A CN 105590893A CN 201410559315 A CN201410559315 A CN 201410559315A CN 105590893 A CN105590893 A CN 105590893A
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Abstract
The invention relates to a semiconductor device, a manufacturing method thereof and an electronic device. The method includes the following steps that: S1, a device wafer is provided, and silicon through holes are formed at the back surface of the device wafer, copper being adopted as a conductive material in the silicon through holes; step S2, back portion grinding is performed on the device wafer, so that the tops of the silicon through holes are exposed; and step S3, a replacement reaction is performed on the exposed tops of the silicon through holes, so that the copper at the tops of the silicon through holes can be replaced by silver, and a silver cover layer can be formed. With the method provided by the invention adopted, the TTV performance of the silicon through holes can be maintained, at the same time, metal diffusion can be eliminated, and therefore, the performance and yield of a device can be improved.
Description
Technical field
The present invention relates to semiconductor applications, particularly, the present invention relates to a kind of semiconductor devices and preparation method thereof, electronic installation.
Background technology
In E-consumer field, multifunctional equipment is more and more subject to liking of consumer, than the simple equipment of function, multifunctional equipment manufacturing process will be more complicated, such as need to be in circuit version the chip of integrated multiple difference in functionalitys, thereby there is 3D integrated circuit (integratedcircuit, IC) technology, 3D integrated circuit (integratedcircuit, IC) be defined as a kind of system-level integrated morphology, multiple chips are stacking in vertical plane direction, thus space saved.
Microelectronic packaging technology is faced with challenge and the opportunity that electronic product " high performance-price ratio, high reliability, multi-functional, miniaturization and low cost " development trend is brought. Four limit pin flat package (QFP), plastics four limit pin flat package (TQFP) are subject to the favor of industry always as the main flow packing forms of surface mounting technique (SMT), but in the time that encapsulating, mount, weld the VLSI of more I/O pin under the 0.3mm pin-pitch limit, they run into the difficulty that is difficult to overcome, especially the in the situation that of batch production, yield rate will decline to a great extent.
In semiconductor devices preparation and wafer level packaging process, conventionally use at present silicon through hole for connecting, and conventionally select rear silicon through hole (via-lastTSV) technique to encapsulate, not only technique is simple, and cost is low.
Integral thickness variable quantity (the totalthicknessvariation of copper post (Cupillar) require silicon through hole in the back exposure technique (TSVBacksideViaRevealProcess) of silicon through hole in, TTV) be less than 2um, to meet follow-up bonding, stacking needs.
Mostly grind by back the thickness that reduces described wafer at present, expose described silicon through hole, the method can ensure the requirement of copper post TTV, but expose described silicon through hole in the back exposure technique of described silicon through hole after, can there is serious side effect (Sideeffect) in the conductive material copper in described silicon through hole, for example there is serious copper diffusion (Cudiffuse), as shown in Fig. 1 c.
Therefore need the preparation method of current described semiconductor devices to be improved further, to eliminate the problems referred to above.
Summary of the invention
In summary of the invention part, introduced the concept of a series of reduced forms, this will further describe in detailed description of the invention part. Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection domain of attempting to determine technical scheme required for protection.
The present invention, in order to overcome current existing problems, provides a kind of preparation method of semiconductor devices, comprising:
Step S1: device wafers is provided, is formed with silicon through hole at the back side of described device wafers, the conductive material in wherein said silicon through hole is selected metallic copper;
Step S2: described device wafers is carried out to back grinding, to expose the top of described silicon through hole;
Step S3: displacement reaction is carried out at the top at the described silicon through hole exposing, so that the described metallic copper of described silicon via top is replaced into argent, forms silver-colored cover layer.
Alternatively, in described step S3, the tectal thickness of described silver is 10-100nm.
Alternatively, in described step S3, after forming described silver-colored cover layer, the thickness of described silicon through hole is constant.
Alternatively, in described step S3, select soluble silver salt and described metallic copper generation displacement reaction.
Alternatively, in described step S1, the front of described device wafers is also formed with slide glass wafer.
Alternatively, after described step S3, described method also comprises:
Step S4: the back side of device wafers described in etch-back, with silicon through hole described in exposed portions serve;
Step S5: dielectric layer, to cover the back side of described device wafers and the described silicon through hole exposing;
Step S6: described in planarization, dielectric layer is to described silver-colored cover layer.
Alternatively, in described step S4, the back side of device wafers is to below described silver-colored cover layer 4-6um described in etch-back.
Alternatively, described method also further comprises:
Step S7: retain described silver-colored cover layer, and carry out wafer bonding and/or stacking technique at the back side of described device wafers.
The invention provides a kind of semiconductor devices preparing based on said method.
The invention provides a kind of electronic installation, comprise above-mentioned semiconductor devices.
The present invention is in order to solve problems of the prior art, a kind of preparation method of semiconductor devices is provided, in described method in order to meet the requirement of TTV performance of silicon through hole, device wafers is carried out to back grinding to expose described silicon through hole, then in order to solve the problem of metallic copper diffusion, the described metallic copper exposing is carried out to autoregistration displacement reaction, so that the metallic copper of described silicon through-hole surfaces is replaced into the argent that diffusion coefficient is lower, to form argent cover layer, avoid the diffusion of metal, in addition, can also carry out the bonding of wafer and stacking described argent in the situation that retaining, further reduce the cost of device. described method can not only keep the TTV performance of silicon through hole, eliminates metal diffusion simultaneously, has improved performance and the yield of device.
Brief description of the drawings
Following accompanying drawing of the present invention is used for understanding the present invention in this as a part of the present invention. Shown in the drawings of embodiments of the invention and description thereof, be used for explaining device of the present invention and principle. In the accompanying drawings,
Fig. 1 a-1e is process schematic diagram prepared by semiconductor devices described in prior art;
Fig. 2 a-2d is process schematic diagram prepared by semiconductor devices described in an embodiment of the present invention;
Fig. 3 is the process chart of preparing described semiconductor devices in the embodiment of the invention.
Detailed description of the invention
In the following description, a large amount of concrete details have been provided to more thorough understanding of the invention is provided. But, it is obvious to the skilled person that the present invention can be implemented without one or more these details. In other example, for fear of obscuring with the present invention, be not described for technical characterictics more well known in the art.
Should be understood that, the present invention can be with multi-form enforcement, and should not be interpreted as the embodiment that is confined to propose here. On the contrary, provide these embodiment to expose thorough and complete, and scope of the present invention is fully passed to those skilled in the art. In the accompanying drawings, for clear, the size in Ceng He district and relative size may be exaggerated. Same reference numerals represents identical element from start to finish.
Be understood that, when element or layer be called as " ... on ", " with ... adjacent ", " being connected to " or " being coupled to " other element or when layer, its can be directly on other element or layer, with it adjacent, connect or be coupled to other element or layer, or can there is element or layer between two parties. On the contrary, when element be called as " directly exist ... on ", when " with ... direct neighbor ", " being directly connected to " or " being directly coupled to " other element or layer, there is not element or layer between two parties. Although it should be understood that and can use term first, second, third, etc. to describe various elements, parts, district, floor and/or part, these elements, parts, district, floor and/or part should not limited by these terms. These terms are only used for distinguishing an element, parts, district, floor or part and another element, parts, district, floor or part. Therefore, do not departing under the present invention's instruction, the first element discussed below, parts, district, floor or part can be expressed as the second element, parts, district, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... on ", " above " etc., thereby can be used for convenience of description the relation of element shown in description figure or feature and other element or feature here. It should be understood that except the orientation shown in figure, spatial relationship term intention also comprise use and operate in the different orientation of device. For example, if the device in accompanying drawing upset, then, be described as " below other element " or " under it " or " under it " element or feature will be oriented to other element or feature " on ". Therefore, exemplary term " ... below " and " ... under " can comprise upper and lower two orientations. Device can additionally be orientated (90-degree rotation or other orientation) and as used herein spatial description language correspondingly explained.
The object of term is only to describe specific embodiment and not as restriction of the present invention as used herein. In the time that this uses, " one " of singulative, " one " and " described/to be somebody's turn to do " also intention comprise plural form, unless the other mode of pointing out known in context. It is also to be understood that term " composition " and/or " comprising ", in the time using in this description, determine the existence of described feature, integer, step, operation, element and/or parts, but do not get rid of one or more other existence or the interpolations of feature, integer, step, operation, element, parts and/or group. In the time that this uses, term "and/or" comprises any and all combinations of relevant Listed Items.
In prior art, the back exposure technique (TSVBacksideViaRevealProcess) of silicon through hole is as shown in Fig. 1 a-1e, first device wafers 101 is provided, be formed with silicon through hole 103 at the back side of described device wafers, above described silicon through hole, be also formed with various cmos devices and interconnect architecture, then form slide glass wafer 102 in the front of described device, as shown in Figure 1a.
Then the described device wafers 101 of reversing, makes the back side of described device wafers upward, as shown in Figure 1 b.
Then, carry out the top of back grinding steps to described silicon through hole 103, device wafers described in etch-back, with silicon through hole 103 described in exposed portions serve, as shown in Fig. 1 c, although expose described silicon through hole and can meet the demand of TTV by described method, for subsequent technique is given security, but a lot of counter productives are also with, for example there is side effect (Sideeffect), comprise serious copper diffusion (Cudiffuse), as shown in the figure of Fig. 1 c left side, metallic copper in wherein said silicon through hole can spread to both sides, as shown in dashed rectangle, wherein right side is the SEM figure for preparing TSV by described method, described copper diffusion phenomena are very serious as can be seen from the figure.
Described method also comprises dielectric layer 104, as shown in Figure 1 d, finally also comprises the step of dielectric layer 104 described in planarization, as shown in Fig. 1 e.
Therefore, because copper diffusion phenomena in the back exposure technique of silicon through hole are very serious, in prior art, mostly solve this problem by forming copper diffusion barrier layer, but due to very high to the requirement of silicon through hole TTV in this technique, described method can not meet the requirement of TTV, therefore the problem that how to solve copper diffusion in the case of ensureing to meet the requirement of TTV becomes very difficult, and the yield of device and performance are significantly declined.
Therefore need described method to be further improved.
Embodiment 1
The present invention, in order to solve the problem of prior art existence, provides a kind of preparation method of new semiconductor devices, below in conjunction with Fig. 2 a-2d, described method is further described.
First, execution step 201, provides device wafers 202, is formed with silicon through hole 203 at the back side of described device wafers, and the conductive material in wherein said silicon through hole is selected metallic copper.
Particularly, as described in Fig. 2 a, in this step, on the front of described device wafers, be formed with various cmos devices. The various active devices that for example form in described device wafers, described active device includes but not limited to transistor, diode etc., in addition, on described active device, can also form various interconnection structures, described interconnection structure comprises some metal levels and the through hole between described some metal levels, and described interconnection structure is for forming electrical connection with described cmos device.
The front of wherein said device wafers refers to the one side that is formed with cmos device and pattern, the back side of described device wafers refers to the one side that does not form cmos device and pattern, in follow-up step, if specified otherwise not, the front and back of described device wafers is all with reference to this explanation.
The back side in described device wafers 202 is also formed with silicon through hole 203, for example, after forming various CMOS function elements in described device wafers, the back side of device wafers described in patterning, to form silicon via openings, at the interconnection structure that exposes described cmos device or described cmos device, then fill separation layer and conductive material layer, to form silicon through hole 203.
Or described silicon through hole formed before forming described cmos device in described device wafers.
Wherein, the formation method of described silicon through hole is not limited to a certain, can select method conventional in this area, and described silicon through hole forms the back side with described device wafers.
Execution step 202, forms slide glass wafer 201 in the front of described device wafers 202.
Particularly, as shown in Figure 2 a, in this step, provide slide glass wafer 201, and carry out bonding with the front of described device wafers.
In the present invention, described slide glass wafer 201 can be selected the material such as silicon, polysilicon, is not limited to a certain.
Particularly, in this step, can device wafers 202 and described slide glass wafer 201 be carried out to bonding by adhesive glue, can described device wafers 202 and described slide glass wafer 201 be carried out to bonding by the method for melting bonding in addition, be not limited to a certain, design according to specific needs, do not repeat them here.
Execution step 203, by described device wafers reversion, obtains pattern as shown in Figure 2 a.
After carrying out inversion step, described slide glass wafer 201 is positioned at bottom, and the bottom surface of described device wafers upwards.
Execution step 204, to the step of carrying out attenuate of described device wafers.
Particularly, as shown in Figure 2 a, at the bag of attenuate step described in this step, described device wafers is carried out to back grinding.
In this step, described Ginding process can be selected the conventional method in this area, is not limited to a certainly, does not repeat them here.
In this step by the grinding back surface of described device wafers to the top of described silicon through hole, to expose the top of described silicon through hole, to ensure to meet the requirement of described silicon through hole TTV performance.
After exposing the top of described silicon through hole; conventionally can there is side effect in the metallic copper in silicon through hole; for example there is serious copper diffusion; the method that forms copper diffusion barrier layer in prior art can not meet the requirement of silicon through hole TTV, and the requirement that therefore how to solve copper diffusion simultaneously and meet silicon through hole TTV becomes conflicting two sides.
For this reason, inventor has solved this difficult problem by the following method dexterously, after exposing described silicon through hole, performs step 205, carries out displacement reaction at the top of the described silicon through hole exposing, so that the metallic copper of described silicon via top is replaced into argent, form silver-colored cover layer 204.
Particularly, as shown in Figure 2 b, in this step, the copper of top surface is replaced argent by top at described silicon through hole after exposing described silicon through hole, to prevent the diffusion of metallic copper, in this process, do not increase the thickness of described metallic copper, can meet the requirement of silicon through hole (metallic copper) TTV, well solve the contradiction existing in prior art.
In this step, select soluble silver salt and described metallic copper generation displacement reaction, select in the present invention the method for autoregistration (Self-aligned) to form silver-colored cover layer, for example silver soluble salting liquid is dripped to the surface at the described metallic copper exposing, there is described displacement reaction, also can not react at the back side of described device wafers simultaneously.
Further, for example first use AgNO3Described displacement reaction occurs, and reaction equation is AgNO3+Cu＝Ag+Cu(NO3)2, but be not limited to AgNO3。
Alternatively, the tectal thickness of described silver is 10-100nm, can avoid occurring the diffusion of metal after forming described silver-colored cover layer.
The diffusion of table 1 different metal
| Material | Diffusion coefficient | Temperature |
| Cu | 1.6x10-9cm2/s | Room temperature |
| Ag | 1x10-18～1x10-16cm2/s | 50～300℃ |
| Al | 1x10-19～1x10-14cm2/s | 50～300℃ |
Can find by above-mentioned table 1, the diffusion coefficient of the argent of selecting is in the present invention close with metal A l, compare the reduction with at least 7 orders of magnitude with copper, therefore after forming described argent, can eliminate the diffusion of metal, described argent has good electric conductivity simultaneously, therefore in follow-up step, need not remove, can directly carry out the bonding of wafer and stacking, therefore further simplify this processing step.
Execution step 206, the back side of device wafers described in etch-back, with silicon through hole 203 described in exposed portions serve.
Particularly, as shown in Figure 2 c, in this step, select the back side with described silicon through hole with device wafers described in the method etch-back of larger etching selectivity, to prevent that described silicon through hole is caused to damage.
Can select in the present invention dry etching or wet etching, be not limited to a certainly, for example, select reaction ionic etching method, described reactive ion etching is selected CxFyGas, for example CF4、CHF3、C4F8Or C5F8, in a detailed description of the invention of the present invention, described etching can be selected CF4、CHF3, add in addition N2、CO2In one as etching atmosphere, wherein gas flow is CF410-200sccm，CHF310-200sccm，N2Or CO2Or O210-400sccm, described etching pressure is 30-150mTorr, etching period is 5-120s.
In this step, described in etch-back the back side of device wafers to below described silver-colored cover layer 4-6um, for example described in etch-back the back side of device wafers to below described silver-colored cover layer 5um.
Execution step 207, dielectric layer 205, to cover the back side of described device wafers and the described silicon through hole exposing.
Particularly, as shown in Figure 2 d, changing in step, described dielectric layer 205 can use for example SiO2, fluorocarbon (CF), carbon doped silicon oxide (SiOC) or carbonitride of silicium (SiCN) etc. Or, also can use film having formed SiCN film etc. on fluorocarbon (CF).
Cover the back side and the described silicon through hole 203 of described device wafers completely at dielectric layer described in this step.
Execution step 208, dielectric layer is to described silver-colored cover layer described in planarization.
Particularly, as shown in Figure 2 d, in this step, can realize surperficial planarization with flattening method conventional in field of semiconductor manufacture. The limiting examples of this flattening method comprises mechanical planarization method and chemically mechanical polishing flattening method.
Further, described method also further comprises: retain described silver-colored cover layer, and carry out the bonding of wafer and/or stacking technique at the back side of described device wafers.
So far, completed the introduction of the described semiconductor gas device of preparation of the embodiment of the present invention. After above-mentioned steps, can also comprise other correlation step, repeat no more herein. And except above-mentioned steps, the preparation method of the present embodiment can also comprise other steps among above-mentioned each step or between different steps, these steps all can realize by various technique of the prior art, repeat no more herein.
The present invention is in order to solve problems of the prior art, a kind of preparation method of semiconductor devices is provided, in described method in order to meet the requirement of TTV performance of silicon through hole, device wafers is carried out to back grinding to expose described silicon through hole, then in order to solve the problem of metallic copper diffusion, the described metallic copper exposing is carried out to autoregistration displacement reaction, so that the metallic copper of described silicon through-hole surfaces is replaced into the argent that diffusion coefficient is lower, to form argent cover layer, avoid the diffusion of metal, in addition, can also carry out the bonding of wafer and stacking described argent in the situation that retaining, further reduce the cost of device. described method can not only keep the TTV performance of silicon through hole, eliminates metal diffusion simultaneously, has improved performance and the yield of device.
Fig. 3 is the present invention one preparation technology's flow chart of semiconductor devices described in embodiment particularly, specifically comprises the following steps:
Step S1: device wafers is provided, is formed with silicon through hole at the back side of described device wafers, the conductive material in wherein said silicon through hole is selected metallic copper;
Step S2: described device wafers is carried out to back grinding, to expose the top of described silicon through hole;
Step S3: displacement reaction is carried out at the top at the described silicon through hole exposing, so that the described metallic copper of described silicon via top is replaced into argent, forms silver-colored cover layer.
Embodiment 2
The present invention also provides a kind of semiconductor devices, and described semiconductor devices is selected the method preparation described in embodiment 1. The semiconductor devices price preparing by method described in the embodiment of the present invention 1 is lower, and has higher yield and output.
Embodiment 3
The present invention also provides a kind of electronic installation, comprises the semiconductor devices described in embodiment 2. Wherein, semiconductor devices is the semiconductor devices described in embodiment 2, or the semiconductor devices obtaining according to the preparation method described in embodiment 1.
The electronic installation of the present embodiment, can be any electronic product or the equipment such as mobile phone, panel computer, notebook computer, net book, game machine, television set, VCD, DVD, navigator, camera, video camera, recording pen, MP3, MP4, PSP, also can be any intermediate products that comprise described semiconductor devices. The electronic installation of the embodiment of the present invention, owing to having used above-mentioned semiconductor devices, thereby has better performance.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment is the object for giving an example and illustrating just, but not is intended to the present invention to be limited in described scope of embodiments. In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection. Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (10)
1. a preparation method for semiconductor devices, comprising:
Step S1: device wafers is provided, is formed with silicon through hole, Qi Zhongsuo at the back side of described device wafersThe conductive material of stating in silicon through hole is selected metallic copper;
Step S2: described device wafers is carried out to back grinding, to expose the top of described silicon through hole;
Step S3: displacement reaction is carried out at the top at the described silicon through hole exposing, to push up described silicon through holeThe described metallic copper of portion is replaced into argent, forms silver-colored cover layer.
2. method according to claim 1, is characterized in that, in described step S3, described inThe tectal thickness of silver is 10-100nm.
3. method according to claim 1, is characterized in that, in described step S3, formsAfter described silver-colored cover layer, the thickness of described silicon through hole is constant.
4. method according to claim 1, is characterized in that, in described step S3, selectsSoluble silver salt and described metallic copper generation displacement reaction.
5. method according to claim 1, is characterized in that, in described step S1, described inThe front of device wafers is also formed with slide glass wafer.
6. method according to claim 1, is characterized in that, after described step S3, and instituteThe method of stating also comprises:
Step S4: the back side of device wafers described in etch-back, with silicon through hole described in exposed portions serve;
Step S5: dielectric layer, to cover the back side of described device wafers and the described silicon through hole exposing;
Step S6: described in planarization, dielectric layer is to described silver-colored cover layer.
7. method according to claim 6, is characterized in that, in described step S4, eat-backsCarve the back side of described device wafers to below described silver-colored cover layer 4-6um.
8. method according to claim 6, is characterized in that, described method also further comprises:
Step S7: retain described silver-colored cover layer, and carry out at the back side of described device wafers wafer bonding and/ or stacking technique.
9. the semiconductor devices preparing based on the described method of one of claim 1 to 8.
10. an electronic installation, comprises semiconductor devices claimed in claim 9.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102208362A (en) * | 2011-05-04 | 2011-10-05 | 中国科学院微电子研究所 | Preparation method of Through-Silicon-Via back coupling end |
| CN103219303A (en) * | 2013-03-28 | 2013-07-24 | 江苏物联网研究发展中心 | Packaging structure and method of TSV (Through Silicon Vias) back leakage hole |
| CN103390580A (en) * | 2013-08-20 | 2013-11-13 | 华进半导体封装先导技术研发中心有限公司 | Back exposing method of TSV (through silicon via) |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102208362A (en) * | 2011-05-04 | 2011-10-05 | 中国科学院微电子研究所 | Preparation method of Through-Silicon-Via back coupling end |
| CN103219303A (en) * | 2013-03-28 | 2013-07-24 | 江苏物联网研究发展中心 | Packaging structure and method of TSV (Through Silicon Vias) back leakage hole |
| CN103390580A (en) * | 2013-08-20 | 2013-11-13 | 华进半导体封装先导技术研发中心有限公司 | Back exposing method of TSV (through silicon via) |
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