CN105530004A - Method and device for acquiring pulse-width modulation PWM control time-delay time - Google Patents
Method and device for acquiring pulse-width modulation PWM control time-delay time Download PDFInfo
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Abstract
The invention discloses a method and a device for acquiring pulse-width modulation PWM control time-delay time. The method comprises steps that, a first PWM signal and a second PWM signal are received, and control on a PWM counter is carried out according to the first PWM signal; sampling interruption is generated according to the second PWM signal; a performing time is generated according a zero crossing time of the PWM counter, and an attribute value is generated according to a counting direction of the PWM counter; the counter starts according to sampling interruption, the first time-delay time is calculated according to a counting value of the counter; a second time-delay time is calculated according to the counting time of the PWM counter, the largest counting value of the PWM counter and the counting period; the PWM control time-delay time is generated according to the first time-delay time and the second time-delay time. Through the method, the non-strict synchronization relationship among the sampling time, the process processing and the PWM counter can be permitted, the accurate PWM control time-delay time can be acquired, and flexibility is improved.
Description
Technical field
The present invention relates to control technology field, particularly relate to acquisition methods and device that a kind of PWM controls delay time.
Background technology
Based on PWM (Pulse-WidthModulation, pulse width modulation) in the engineering that controls (as inverter, frequency converter etc.), need the time (PWM controls time delay) clearly knowing that " sampling instant " arrives between " performing the moment ", and go to compensate this delay time by certain algorithm, thus obtain better real-time control performance.
As shown in Figure 1, in the detection method of correlation technique, usually that sampling instant, processing procedure is synchronous with PWM.cnt, thus clear and definite control delay time can be obtained.Like this, Tdly is exactly that PWM controls time delay, namely equals the PWM cycle.Figure 1 shows that the synchronous sequence in correlation technique, wherein, Texe is the processing procedure time, and Tdly is that PWM controls time delay, equals Tpwm.The execution moment refers to the controlled quentity controlled variable that those have been written into PWM comparand register, starts by PWM module process, and produce pwm signal on corresponding pin.Normally, the execution moment is fixed on PWM counter (PWM.cnt) zero passage place.Processing procedure refers to from " calculate " to " writing controlled quentity controlled variable to PWM comparand register " whole process.
Obviously, if sampling instant, process process, do not have strict synchronized relation between this three of PWM counter, so said method directly accurately cannot obtain Tdly.
Summary of the invention
The present invention is intended to solve one of technical problem in correlation technique at least to a certain extent.For this reason, one object of the present invention is to propose the acquisition methods that a kind of pulse width modulation (PWM) controls delay time, the method can allow do not have strict synchronized relation between sampling instant, process process, this three of PWM counter, also accurately can obtain PWM and control delay time, improve flexibility.
Second object of the present invention is to propose the acquisition device that a kind of pulse width modulation (PWM) controls delay time.
To achieve these goals, the PWM of first aspect present invention embodiment controls the acquisition methods of delay time, comprises the following steps: receive the first pwm signal and the second pwm signal, and controls PWM counter according to described first pwm signal; Sampling interrupt is generated according to described second pwm signal; Generate according to the zero-acrross ing moment of described PWM counter and perform the moment, and generate property value according to the counting direction of described PWM counter; Start counter according to described Sampling interrupt, and calculate the first delay time according to the count value of described counter and count cycle; The second delay time is calculated according to the count value of described PWM counter and the maximum count value of described PWM counter and count cycle; And generate described PWM control delay time according to described first delay time and described second delay time.
The acquisition methods of delay time is controlled according to the PWM of the embodiment of the present invention, can allow there is no strict synchronized relation between sampling instant, process process, this three of PWM counter, the method also accurately can obtain PWM and control delay time, improves flexibility.
To achieve these goals, the PWM of second aspect present invention embodiment controls the acquisition device of delay time, comprising: receiver module, for receiving the first pwm signal and the second pwm signal, and controlling PWM counter according to described first pwm signal; Interrupt generation module, for generating Sampling interrupt according to described second pwm signal; Attribute value generation module, performs the moment for generating according to the zero-acrross ing moment of described PWM counter, and generates property value according to the counting direction of described PWM counter; First computing module, for starting counter according to described Sampling interrupt, and calculates the first delay time according to the count value of described counter and count cycle; Second computing module, for calculating the second delay time according to the count value of described PWM counter and the maximum count value of described PWM counter and count cycle; And delay time computing module, control delay time for generating described PWM according to described first delay time and described second delay time.
The acquisition device of delay time is controlled according to the PWM of the embodiment of the present invention, can allow there is no strict synchronized relation between sampling instant, process process, this three of PWM counter, this device also accurately can obtain PWM and control delay time, improves flexibility.
Accompanying drawing explanation
Fig. 1 is the time diagram in a certain moment in the dsp chip running in correlation technique;
Fig. 2 is that PWM controls the flow chart of the acquisition methods of delay time according to an embodiment of the invention;
Fig. 3 is the time diagram in a certain moment in dsp chip running according to an embodiment of the invention;
Fig. 4 is the flow chart arranging state flag bit according to an embodiment of the invention;
Fig. 5 generates the flow chart that PWM controls delay time according to an embodiment of the invention;
Fig. 6 is that PWM controls the structural representation of the acquisition device of delay time according to an embodiment of the invention;
Fig. 7 is that PWM controls the structural representation of the acquisition device of delay time in accordance with another embodiment of the present invention.
Embodiment
Be described below in detail embodiments of the invention, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has element that is identical or similar functions from start to finish.Be exemplary below by the embodiment be described with reference to the drawings, be intended to for explaining the present invention, and can not limitation of the present invention be interpreted as.
Below with reference to the accompanying drawings 2-Fig. 7 describes acquisition methods and the device of the PWM control delay time of the embodiment of the present invention.
Fig. 2 is that PWM controls the flow chart of the acquisition methods of delay time according to an embodiment of the invention.As shown in Figure 2, the PWM of the embodiment of the present invention controls the acquisition methods of delay time, comprises the following steps:
S101, receives the first pwm signal and the second pwm signal, and controls PWM counter according to the first pwm signal.
Be example with PMSM (PermanentMagnetSynchronousMotor) Control Engineering based on FOC (Field-OrientedControl is magnetic field steering control) algorithm below.Wherein, DSP (DigitalSignalProcessor digital signal processor) chip selects the TMS320F28335 of TI company.
Particularly, use EPWM1, EPWM2, EPWM3 of dsp chip to produce synchronous pwm signal (i.e. the first pwm signal, the EPWMA namely in Fig. 3), its PWM frequency is with working conditions change.The EPWM4 of dsp chip is used to trigger ADC (Analog-to-DigitalConverter, an analog-digital converter) sampling every 100us, i.e. the second pwm signal (EPWMB namely in Fig. 3).
More specifically, receive the first pwm signal and the second pwm signal, and control PWM counter according to the first pwm signal, such as, control PWM counter is opened.
S102, generates Sampling interrupt according to the second pwm signal.
Particularly, generate Sampling interrupt according to the second pwm signal, namely EPWM4 allows to produce ADC and to have sampled interruption (ADC_ISR, namely sampling instant).
S103, generates according to the zero-acrross ing moment of PWM counter and performs the moment, and generate property value according to the counting direction of PWM counter.
Particularly, as shown in Figure 3, the zero-acrross ing moment that the moment is set in PWM counter is performed.Property value is designated as DIR, when PWM counter upwards counts, makes DIR=1, when PWM counter counts downward, make DIR=0.In addition, the maximum count value (summit) of PWM counter is set to TBPRD.The count cycle of PWM counter is Tp (such as, the count value of PWM counter changed to for 2 times used from 1).
Be illustrated in figure 3 asynchronous time diagram, wherein, Ta is the time interval that " sampling instant " arrives " processing procedure start time "; Texe is " time of implementation of processing procedure " interval; Tw is the time interval that " PWM comparand register writes the moment " arrives " performing the moment "; Tb is the time interval arriving " processing procedure start time " " performing the moment ".Perform the moment, refer to the controlled quentity controlled variable that those have been written into PWM comparand register, start by PWMM resume module, and produce pwm signal on corresponding pin.Normally, this moment is fixed on the zero passage place of PWM counter (PWM.cnt).Processing procedure, refers to from " calculate " to " writing controlled quentity controlled variable to PWM comparand register " whole process.Wherein, the CpuTimer0 module of dsp chip is used to produce an Interruption every 100us, and the processing procedure of the middle execution of disconnected function (TIMER_ISR) wherein.
In addition, enable interrupt nesting function, and the priority arranging ADC_ISR is greater than TIMER_ISR.
S104, starts counter according to Sampling interrupt, and calculates the first delay time according to the count value of counter and count cycle.
In an embodiment of the present invention, the first delay time is the time of sampling instant to processing procedure start time.
Particularly, the CpuTimer1 module in use dsp chip is as timing module (HwTimer), i.e. counter, for calculating the first delay time.Wherein, the count cycle of counter is Tc.
More specifically, start to perform the moment in processing procedure, preserve the current count value of counter, then calculate the first delay time according to the current count value of counter.
In one embodiment of the invention, by following formulae discovery first delay time: Ta=HwTimer.Cnt*Tc, wherein, Ta is the first delay time, and HwTimer.Cnt is the count value of counter, and Tc is the count cycle of counter.
S105, calculates the second delay time according to the count value of PWM counter and the maximum count value of PWM counter and count cycle.
In an embodiment of the present invention, the second delay time is that processing procedure start time is to the time performing the moment.
Particularly, by following formulae discovery second delay time:
Tb=(DIR*TBPRD+TBPRD – PWM.Cnt) * Tp, wherein, Tb is the second delay time, and DIR is property value, and the value of DIR is 0 or 1, wherein, DIR=1 represents that PWM counter upwards counts, and DIR=0 represents PWM counter counts downward, and TBPRD is the maximum count value of PWM counter, PWM.Cnt is the count value of PWM counter, and Tp is the count cycle of PWM counter.
S106, generates PWM according to the first delay time and the second delay time and controls delay time.
In one embodiment of the invention, generate PWM according to the first delay time and the second delay time and control delay time, specifically comprise:
S1, judge whether the second delay time is less than or equal to the time of implementation of processing procedure;
S2, if then the value of the second delay time to be added the periodic quantity of the counting waves of PWM counter, continues to perform S1;
S3, if not, then PWM controls delay time and equals the first delay time and the second delay time sum.
Particularly, first judge whether the second delay time Tb is less than or equal to Texe (time of implementation of processing procedure), if not, then PWM controls delay time Tdly=Ta+Tb; If so, then make Tb=Tb+Tpwm, then continue to judge whether Tb is less than or equal to Texe, if so, continue to make Tb=Tb+Tpwm, until Tb>Texe, then obtain Tdly according to Tdly=Ta+Tb.Wherein, as shown in Figure 3, Tpwm is the periodic quantity of the counting waves of PWM counter.
The PWM of the embodiment of the present invention controls the acquisition methods of delay time, can allow do not have strict synchronized relation between sampling instant, process process, this three of PWM counter, and the method also accurately can obtain PWM and control delay time, improves flexibility.
In one embodiment of the invention, in order to ensure correct execution sequence, introducing a state flag bit (StFlg is initialized as 0), after generating Sampling interrupt according to the second pwm signal, also comprising: reading state flag bit; Judge whether state flag bit is zero; If state flag bit is zero, then by counter zero setting, and status indicator position is revised as 1.
Particularly, as shown in Figure 4, first wait for that ADC_ISR (i.e. Sampling interrupt) produces, now first judge whether state flag bit is 0; If state flag bit is zero, then makes HwTimer.Cnt (count value of counter) be zero, and state flag bit is revised as 1.
In one embodiment of the invention, after generating PWM according to the first delay time and the second delay time and controlling delay time, also comprise: by Status Flag position zero.
Particularly, as shown in Figure 5, in process process, first judge whether Status Flag is 1; If so, then calculate the first delay time Ta according to current HwTimer.Cnt, namely calculate Ta by formula " Ta=HwTimer.Cnt*Tc ".Next, Tb is calculated first according to formula " Tb=(DIR*TBPRD+TBPRD – PWM.Cnt) * Tp ".If Tb<=Texe, then repeatedly perform Tb=Tb+Tpwm, until Tb>Texe.Then, obtain Tdly according to " Tdly=Ta+Tb ", finally, state flag bit is set to 0.
In order to realize above-described embodiment, the present invention also proposes the acquisition device that a kind of PWM controls delay time.
Fig. 6 is that PWM controls the structural representation of the acquisition device of delay time according to an embodiment of the invention.As shown in Figure 6, the PWM of the embodiment of the present invention controls the acquisition device of delay time, comprising: receiver module 100, interruption generation module 200, attribute value generation module 300, first computing module 400, second computing module 500 and delay time computing module 600.
Wherein, receiver module 100 for receiving the first pwm signal and the second pwm signal, and controls PWM counter according to the first pwm signal.
Below for the PMSM Control Engineering based on FOC algorithm.Wherein, dsp chip selects the TMS320F28335 of TI company.
Particularly, use EPWM1, EPWM2, EPWM3 of dsp chip to produce synchronous pwm signal (i.e. the first pwm signal, the EPWMA namely in Fig. 3), its PWM frequency is with working conditions change.The EPWM4 of dsp chip is used to trigger ADC (Analog-to-DigitalConverter, an analog-digital converter) sampling every 100us, i.e. the second pwm signal.
More specifically, receiver module 100 receives the first pwm signal and the second pwm signal, and controls PWM counter according to the first pwm signal, and such as, control PWM counter is opened.
Interrupt generation module 200 for generating Sampling interrupt according to the second pwm signal.
Particularly, interrupt generation module 200 and generate Sampling interrupt according to the second pwm signal, namely EPWM4 allows to produce ADC and to have sampled interruption (ADC_ISR, namely sampling instant).
Attribute value generation module 300 performs the moment for generating according to the zero-acrross ing moment of PWM counter, and generates property value according to the counting direction of PWM counter.
Particularly, as shown in Figure 3, the zero-acrross ing moment that the moment is set in PWM counter is performed.Property value is designated as DIR, when PWM counter upwards counts, makes DIR=1, when PWM counter counts downward, make DIR=0.In addition, the maximum count value (summit) of PWM counter is set to TBPRD.The count cycle of PWM counter is Tp.
Be illustrated in figure 3 asynchronous time diagram, wherein, Ta is the time interval that " sampling instant " arrives " processing procedure start time "; Texe is " time of implementation of processing procedure " interval; Tw is the time interval that " PWM comparand register writes the moment " arrives " performing the moment "; Tb is the time interval arriving " processing procedure start time " " performing the moment ".Perform the moment, refer to the controlled quentity controlled variable that those have been written into PWM comparand register, start by PWMM resume module, and produce pwm signal on corresponding pin.Normally, this moment is fixed on the zero passage place of PWM counter (PWM.cnt).Processing procedure, refers to from " calculate " to " writing controlled quentity controlled variable to PWM comparand register " whole process.Wherein, the CpuTimer0 module of dsp chip is used to produce an Interruption every 100us, and the processing procedure of the middle execution of disconnected function (TIMER_ISR) wherein.
In addition, enable interrupt nesting function, and the priority arranging ADC_ISR is greater than TIMER_ISR.
First computing module 400 for starting counter according to Sampling interrupt, and calculates the first delay time according to the count value of counter and count cycle.
In an embodiment of the present invention, the first delay time is the time of sampling instant to processing procedure start time.
Particularly, the CpuTimer1 module in use dsp chip is as timing module (HwTimer), i.e. counter, for calculating the first delay time.Wherein, the count cycle of counter is Tc.
More specifically, start to perform the moment in processing procedure, preserve the current count value of counter, then the first computing module 400 calculates the first delay time according to the current count value of counter.
In one embodiment of the invention, the first computing module 400 is by following formulae discovery first delay time: Ta=HwTimer.Cnt*Tc, and wherein, Ta is the first delay time, and HwTimer.Cnt is the count value of counter, and Tc is the count cycle of counter.
Second computing module 500 is for calculating the second delay time according to the count value of PWM counter and the maximum count value of PWM counter and count cycle.
In an embodiment of the present invention, the second delay time is that processing procedure start time is to the time performing the moment.
In one embodiment of the invention, the second computing module 500 is by following formulae discovery second delay time:
Tb=(DIR*TBPRD+TBPRD – PWM.Cnt) * Tp, wherein, Tb is the second delay time, and DIR is property value, and the value of DIR is 0 or 1, wherein, DIR=1 represents that PWM counter upwards counts, and DIR=0 represents PWM counter counts downward, and TBPRD is the maximum count value of PWM counter, PWM.Cnt is the count value of PWM counter, and Tp is the count cycle of PWM counter.
Delay time computing module 600 controls delay time for generating PWM according to the first delay time and the second delay time.
In one embodiment of the invention, delay time computing module 600 specifically for: judge whether the second delay time is less than or equal to the time of implementation of processing procedure, if not, then PWM control delay time equals the first delay time and the second delay time sum, if, then the value of the second delay time is added the periodic quantity of the counting waves of PWM counter, until the second delay time is greater than the time of implementation of processing procedure.
Particularly, first delay time computing module 600 judges whether the second delay time Tb is less than or equal to Texe (time of implementation of processing procedure), and if not, then PWM controls delay time Tdly=Ta+Tb; If so, then make Tb=Tb+Tpwm, then continue to judge whether Tb is less than or equal to Texe, if so, continue to make Tb=Tb+Tpwm, until Tb>Texe, then obtain Tdly according to Tdly=Ta+Tb.
The PWM of the embodiment of the present invention controls the acquisition device of delay time, can allow do not have strict synchronized relation between sampling instant, process process, this three of PWM counter, and this device also accurately can obtain PWM and control delay time, improves flexibility.
In one embodiment of the invention, in order to ensure correct execution sequence, introduce a state flag bit (StFlg, be initialized as 0), as shown in Figure 7, PWM controls the acquisition device of delay time, also comprises: read module 700, judge module 800 and modified module 900.
Wherein, read module 700 is for reading state flag bit after interruption generation module 200 is according to the second pwm signal generation Sampling interrupt; Judge module 800 is for judging whether state flag bit is zero; Modified module 900 for when state flag bit is zero by counter zero setting, and status indicator position is revised as 1.
Particularly, first wait for that ADC_ISR (i.e. Sampling interrupt) produces, now read module 700 first reading state flag bit, judge module 800 judges whether state flag bit is 0; If state flag bit is zero, modified module 900 makes HwTimer.Cnt (count value of counter) be zero, and state flag bit is revised as 1.
In one embodiment of the invention, modified module 900 also for: to generate after PWM controls delay time according to the first delay time and the second delay time, by Status Flag position zero at delay time computing module 600.
In the description of this specification, specific features, structure, material or feature that the description of reference term " embodiment ", " some embodiments ", " example ", " concrete example " or " some examples " etc. means to describe in conjunction with this embodiment or example are contained at least one embodiment of the present invention or example.In this manual, to the schematic representation of above-mentioned term not must for be identical embodiment or example.And the specific features of description, structure, material or feature can combine in one or more embodiment in office or example in an appropriate manner.In addition, when not conflicting, the feature of the different embodiment described in this specification or example and different embodiment or example can carry out combining and combining by those skilled in the art.
In addition, term " first ", " second " only for describing object, and can not be interpreted as instruction or hint relative importance or imply the quantity indicating indicated technical characteristic.Thus, be limited with " first ", the feature of " second " can express or impliedly comprise at least one this feature.In describing the invention, the implication of " multiple " is at least two, such as two, three etc., unless otherwise expressly limited specifically.
Describe and can be understood in flow chart or in this any process otherwise described or method, represent and comprise one or more for realizing the module of the code of the executable instruction of the step of specific logical function or process, fragment or part, and the scope of the preferred embodiment of the present invention comprises other realization, wherein can not according to order that is shown or that discuss, comprise according to involved function by the mode while of basic or by contrary order, carry out n-back test, this should understand by embodiments of the invention person of ordinary skill in the field.
In flow charts represent or in this logic otherwise described and/or step, such as, the sequencing list of the executable instruction for realizing logic function can be considered to, may be embodied in any computer-readable medium, for instruction execution system, device or equipment (as computer based system, comprise the system of processor or other can from instruction execution system, device or equipment instruction fetch and perform the system of instruction) use, or to use in conjunction with these instruction execution systems, device or equipment.With regard to this specification, " computer-readable medium " can be anyly can to comprise, store, communicate, propagate or transmission procedure for instruction execution system, device or equipment or the device that uses in conjunction with these instruction execution systems, device or equipment.The example more specifically (non-exhaustive list) of computer-readable medium comprises following: the electrical connection section (electronic installation) with one or more wiring, portable computer diskette box (magnetic device), random access memory (RAM), read-only memory (ROM), erasablely edit read-only memory (EPROM or flash memory), fiber device, and portable optic disk read-only memory (CDROM).In addition, computer-readable medium can be even paper or other suitable media that can print described program thereon, because can such as by carrying out optical scanner to paper or other media, then carry out editing, decipher or carry out process with other suitable methods if desired and electronically obtain described program, be then stored in computer storage.
Should be appreciated that each several part of the present invention can realize with hardware, software, firmware or their combination.In the above-described embodiment, multiple step or method can with to store in memory and the software performed by suitable instruction execution system or firmware realize.Such as, if realized with hardware, the same in another embodiment, can realize by any one in following technology well known in the art or their combination: the discrete logic with the logic gates for realizing logic function to data-signal, there is the application-specific integrated circuit (ASIC) of suitable combinational logic gate circuit, programmable gate array (PGA), field programmable gate array (FPGA) etc.
Those skilled in the art are appreciated that realizing all or part of step that above-described embodiment method carries is that the hardware that can carry out instruction relevant by program completes, described program can be stored in a kind of computer-readable recording medium, this program perform time, step comprising embodiment of the method one or a combination set of.
In addition, each functional unit in each embodiment of the present invention can be integrated in a processing module, also can be that the independent physics of unit exists, also can be integrated in a module by two or more unit.Above-mentioned integrated module both can adopt the form of hardware to realize, and the form of software function module also can be adopted to realize.If described integrated module using the form of software function module realize and as independently production marketing or use time, also can be stored in a computer read/write memory medium.
The above-mentioned storage medium mentioned can be read-only memory, disk or CD etc.Although illustrate and describe embodiments of the invention above, be understandable that, above-described embodiment is exemplary, can not be interpreted as limitation of the present invention, and those of ordinary skill in the art can change above-described embodiment within the scope of the invention, revises, replace and modification.
Claims (14)
1. pulse width modulation (PWM) controls an acquisition methods for delay time, it is characterized in that, comprises the following steps:
Receive the first pwm signal and the second pwm signal, and according to described first pwm signal, PWM counter is controlled;
Sampling interrupt is generated according to described second pwm signal;
Generate according to the zero-acrross ing moment of described PWM counter and perform the moment, and generate property value according to the counting direction of described PWM counter;
Start counter according to described Sampling interrupt, and calculate the first delay time according to the count value of described counter and count cycle;
The second delay time is calculated according to the count value of described PWM counter and the maximum count value of described PWM counter and count cycle; And
Generate described PWM according to described first delay time and described second delay time and control delay time.
2. PWM as claimed in claim 1 controls the acquisition methods of delay time, it is characterized in that, wherein, described first delay time is the time of sampling instant to processing procedure start time, and described second delay time is the time of described processing procedure start time to the described execution moment.
3. PWM as claimed in claim 2 controls the acquisition methods of delay time, it is characterized in that, by the first delay time described in following formulae discovery:
Ta＝HwTimer.Cnt*Tc，
Wherein, Ta is described first delay time, and HwTimer.Cnt is the count value of described counter, and Tc is the count cycle of described counter.
4. PWM as claimed in claim 2 controls the acquisition methods of delay time, it is characterized in that, by the second delay time described in following formulae discovery:
Tb＝(DIR*TBPRD+TBPRD–PWM.Cnt)*Tp，
Wherein, Tb is described second delay time, DIR is described property value, the value of DIR is 0 or 1, and wherein, DIR=1 represents that described PWM counter upwards counts, DIR=0 represents described PWM counter counts downward, TBPRD is the maximum count value of described PWM counter, and PWM.Cnt is the count value of described PWM counter, and Tp is the count cycle of described PWM counter.
5. PWM as claimed in claim 2 controls the acquisition methods of delay time, it is characterized in that, describedly generates described PWM according to described first delay time and described second delay time and controls delay time, specifically comprises:
S1, judge whether described second delay time is less than or equal to the time of implementation of described processing procedure;
S2, if then the value of described second delay time to be added the periodic quantity of the counting waves of described PWM counter, continues to perform S1;
S3, if not, then described PWM controls delay time and equals described first delay time and described second delay time sum.
6. PWM as claimed in claim 1 controls the acquisition methods of delay time, it is characterized in that, described generate Sampling interrupt according to described second pwm signal after, also comprise:
Reading state flag bit;
Judge whether described state flag bit is zero;
If described state flag bit is zero, then by described counter zero setting, and described status indicator position is revised as 1.
7. PWM as claimed in claim 6 controls the acquisition methods of delay time, it is characterized in that, to generate after described PWM controls delay time, also comprise described according to described first delay time and described second delay time:
By described Status Flag position zero.
8. pulse width modulation (PWM) controls an acquisition device for delay time, it is characterized in that, comprising:
Receiver module, for receiving the first pwm signal and the second pwm signal, and controls PWM counter according to described first pwm signal;
Interrupt generation module, for generating Sampling interrupt according to described second pwm signal;
Attribute value generation module, performs the moment for generating according to the zero-acrross ing moment of described PWM counter, and generates property value according to the counting direction of described PWM counter;
First computing module, for starting counter according to described Sampling interrupt, and calculates the first delay time according to the count value of described counter and count cycle;
Second computing module, for calculating the second delay time according to the count value of described PWM counter and the maximum count value of described PWM counter and count cycle; And
Delay time computing module, controls delay time for generating described PWM according to described first delay time and described second delay time.
9. PWM as claimed in claim 8 controls the acquisition device of delay time, it is characterized in that, wherein, described first delay time is the time of sampling instant to processing procedure start time, and described second delay time is the time of described processing procedure start time to the described execution moment.
10. PWM as claimed in claim 9 controls the acquisition device of delay time, it is characterized in that, the first computing module is by the first delay time described in following formulae discovery:
Ta＝HwTimer.Cnt*Tc，
Wherein, Ta is described first delay time, and HwTimer.Cnt is the count value of described counter, and Tc is the count cycle of described counter.
11. PWM as claimed in claim 9 control the acquisition device of delay time, it is characterized in that, the second computing module is by the second delay time described in following formulae discovery:
Tb＝(DIR*TBPRD+TBPRD–PWM.Cnt)*Tp，
Wherein, Tb is described second delay time, DIR is described property value, the value of DIR is 0 or 1, and wherein, DIR=1 represents that described PWM counter upwards counts, DIR=0 represents described PWM counter counts downward, TBPRD is the maximum count value of described PWM counter, and PWM.Cnt is the count value of described PWM counter, and Tp is the count cycle of described PWM counter.
12. PWM as claimed in claim 9 control the acquisition device of delay time, it is characterized in that, described delay time computing module, specifically for:
Judge whether described second delay time is less than or equal to the time of implementation of described processing procedure, if not, then described PWM control delay time equals described first delay time and described second delay time sum, if, then the value of described second delay time is added the periodic quantity of the counting waves of described PWM counter, until described second delay time is greater than the time of implementation of described processing procedure.
13. PWM as claimed in claim 8 control the acquisition device of delay time, it is characterized in that, also comprise:
Read module, for reading state flag bit after described interruption generation module is according to described second pwm signal generation Sampling interrupt;
Judge module, for judging whether described state flag bit is zero;
Modified module, for when described state flag bit is zero by described counter zero setting, and described status indicator position is revised as 1.
14. PWM as claimed in claim 13 control the acquisition device of delay times, it is characterized in that, described modified module, also for:
After described delay time computing module generates described PWM control delay time according to described first delay time and described second delay time, by described Status Flag position zero.
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| CN201410513299.0A CN105530004B (en) | 2014-09-29 | 2014-09-29 | The acquisition methods and device of pulse width modulation (PWM) control delay time |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112286846A (en) * | 2019-07-25 | 2021-01-29 | 珠海格力电器股份有限公司 | Method and equipment for processing interrupt event |
| CN112904771A (en) * | 2021-01-19 | 2021-06-04 | 厦门欧万精密科技有限公司 | DSP hardware sampling delay compensation method and device based on PWM synchronization mechanism |
| CN113206657A (en) * | 2021-03-24 | 2021-08-03 | 珠海泰为电子有限公司 | PWM signal generation method and device of PFC circuit, storage medium and electronic equipment |
| CN113568339A (en) * | 2021-07-15 | 2021-10-29 | 许继电气股份有限公司 | Converter fixed time delay control method and device |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5793234A (en) * | 1995-05-22 | 1998-08-11 | Lg Semicon Co., Ltd. | Pulse width modulation circuit |
| CN1205465A (en) * | 1997-03-25 | 1999-01-20 | 日本电气株式会社 | Pulse width modulation control which data transfer is inhibited by overflow signal |
| US20080278209A1 (en) * | 2007-05-09 | 2008-11-13 | Samsung Electronics Co., Ltd. | Method of pulse width modulation signal processing and device including signal processing for pulse width modulation |
| US20090296805A1 (en) * | 2008-05-28 | 2009-12-03 | Nec Electronics Corporation | Pulse width modulation controller and pulse waveform control method |
| CN101796712A (en) * | 2007-09-25 | 2010-08-04 | 株式会社大亨 | Pwm signal generator, and inverter equipped with this PWM signal generator |
| CN102792591A (en) * | 2009-05-29 | 2012-11-21 | 动力威胜有限公司 | Pulse width modulation synchronization of switched mode power converters |
-
2014
- 2014-09-29 CN CN201410513299.0A patent/CN105530004B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5793234A (en) * | 1995-05-22 | 1998-08-11 | Lg Semicon Co., Ltd. | Pulse width modulation circuit |
| CN1205465A (en) * | 1997-03-25 | 1999-01-20 | 日本电气株式会社 | Pulse width modulation control which data transfer is inhibited by overflow signal |
| US20080278209A1 (en) * | 2007-05-09 | 2008-11-13 | Samsung Electronics Co., Ltd. | Method of pulse width modulation signal processing and device including signal processing for pulse width modulation |
| CN101796712A (en) * | 2007-09-25 | 2010-08-04 | 株式会社大亨 | Pwm signal generator, and inverter equipped with this PWM signal generator |
| US20090296805A1 (en) * | 2008-05-28 | 2009-12-03 | Nec Electronics Corporation | Pulse width modulation controller and pulse waveform control method |
| CN102792591A (en) * | 2009-05-29 | 2012-11-21 | 动力威胜有限公司 | Pulse width modulation synchronization of switched mode power converters |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112286846A (en) * | 2019-07-25 | 2021-01-29 | 珠海格力电器股份有限公司 | Method and equipment for processing interrupt event |
| CN112904771A (en) * | 2021-01-19 | 2021-06-04 | 厦门欧万精密科技有限公司 | DSP hardware sampling delay compensation method and device based on PWM synchronization mechanism |
| CN113206657A (en) * | 2021-03-24 | 2021-08-03 | 珠海泰为电子有限公司 | PWM signal generation method and device of PFC circuit, storage medium and electronic equipment |
| CN113206657B (en) * | 2021-03-24 | 2022-09-16 | 珠海泰为电子有限公司 | PWM signal generation method and device of PFC circuit, storage medium and electronic equipment |
| CN113568339A (en) * | 2021-07-15 | 2021-10-29 | 许继电气股份有限公司 | Converter fixed time delay control method and device |
| CN113568339B (en) * | 2021-07-15 | 2023-03-21 | 许继电气股份有限公司 | Converter fixed time delay control method and device |
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