CN112904771A - DSP hardware sampling delay compensation method and device based on PWM synchronization mechanism - Google Patents
DSP hardware sampling delay compensation method and device based on PWM synchronization mechanism Download PDFInfo
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Abstract
The invention discloses a DSP hardware sampling delay compensation method based on a PWM synchronization mechanism, which comprises the following steps: calculating the delay time of a hardware sampling circuit; configuring to enable the SOCB to trigger the ADC sampling operation according to the PWM module; determining a set value of a CMPB register; triggering ADC (analog to digital converter) to collect when the count of the PWM counter is equal to the set value of the CMPB register; and the phase compensation of fixed time is carried out on the ADC sampling trigger moment through the synchronous setting of the PWM module. The invention can eliminate the inherent time delay in the hardware sampling circuit by artificially delaying the triggering sampling time, especially the sampling quantity such as inductance current with special requirements on the sampling time, thereby ensuring the sampling precision and improving the stability of the digital control system.
Description
Technical Field
The invention relates to the field of power supply sampling, in particular to a DSP hardware sampling delay compensation method and device based on a PWM synchronization mechanism.
Background
In a digital control system, signal sampling is a very important link, and the accuracy, stability and precision of sampling affect the index of an output waveform, thereby affecting the stability of the whole control system. In an actual digital control system, an actual analog signal needs to be integrated into a digital signal which can be identified by a DSP through a hardware sampling circuit, and the sampled digital signal and the actual analog signal have inevitable delay due to factors such as errors of power electronic devices, PCB layout and the like, so that the compensation or calibration of the hardware sampling delay becomes necessary for the DSP digital sampling system.
The existing compensation method generally adopts the steps of accumulating and calculating sampling variables of software after a sampling circuit is powered on for a period of time and is stable, and then performing zero offset compensation on the sampling quantity, but the compensation mode cannot compensate the sampling quantity from the source, and the deviation caused by hardware delay of the sampling circuit has not only the deviation on the amplitude value but also the deviation on the phase position.
Particularly for a precise power supply, under the condition of extremely small load, the proportion of sampling deviation caused by sampling delay in an actual signal is not negligible, and great influence is caused on the stability of a digital control system and the user experience effect.
In view of the above, how to effectively improve the sampling accuracy is a technical problem to be solved in the art.
Disclosure of Invention
The invention aims to provide a DSP sampling delay compensation method based on a PWM synchronization mechanism, and aims to solve the technical problem that the deviation of a sampling signal and an actual signal in the existing hardware sampling is large.
In order to solve the problems, the invention is realized by the following technical scheme:
a DSP hardware sampling delay compensation method based on a PWM synchronization mechanism comprises the following steps: calculating the delay time of a hardware sampling circuit; configuring the SOCB to trigger an ADC sampling operation according to the PWM module; triggering ADC sampling when the count of the PWM counter is equal to the set value of the CMPB register; determining a set value of a CMPB register; and the phase compensation of fixed time is carried out on the ADC sampling trigger moment through the synchronous setting of the PWM module.
Further, the setting value of the CMPB register is calculated according to the delay time and the clock frequency of the control chip of the sampling object.
Further, the set value of the CMPB register is the hardware sampling delay time divided by the PWM clock period; and calculating the hardware sampling delay time according to the used hardware sampling circuit.
Further, the method for implementing fixed-time phase compensation of the ADC sampling trigger time by synchronous setting of the PWM modules includes the steps of: the clocks TBCLK of each PWM are completely synchronous; synchronizing the phases of all paths of PWM; the timing at which the ADC samples the trigger signal is phase compensated for a fixed time by the setting of the CMPB register of PWM 1.
Further, the clock TBCLK of each PWM is completely synchronized and is set by a TIME-BASE sub-module in each EPWM module.
Further, the method for realizing the phase synchronization of each path of PWM comprises the following steps: configuring whether different PWM peripheral modules enable synchronous signal receiving processing or not; configuring synchronous signal input sources of different PWM peripheral modules; and configuring the phase change of different PWM peripheral modules when the PWM peripheral modules receive the synchronous signals.
Furthermore, the complete synchronization and the phase synchronization of the clock TBCLK of each PWM are realized by adopting a TMS320F2803x control chip.
Further, the input source of the synchronization signal of the PWM peripheral module is the EPWMxSYNCO synchronization output signal of the previous PWM module.
Further, the synchronous output signal is that the counter value of the PWM module is equal to CMPB.
An electronic device based on digital control, comprising: an ADC sampling module for ADC sampling of the electronic device; the PWM module is used for configuring the SOCB to trigger ADC sampling, configuring the PWM counter to trigger ADC sampling when the countdown is equal to the set value of the CMPB register, and configuring to realize each path of PWM clock and phase synchronization; the setting value of the CMPB register is the hardware sampling delay time divided by the PWM clock period; and the hardware sampling delay time length is calculated according to a hardware sampling circuit used by the ADC sampling module.
Compared with the prior art, the technical scheme and the beneficial effects of the invention are as follows:
(1) the invention can eliminate the inherent time delay in the hardware sampling circuit by artificially delaying the triggering sampling time, especially the sampling quantity such as inductance current with special requirements on the sampling time, thereby ensuring the sampling precision and improving the stability of the digital control system.
(2) The set value of the CMPB register of the PWM is calculated according to the delay time of the hardware sampling circuit, so that the compensation of sampling delay is more accurate.
(3) The invention realizes the clock counting consistency of all PWM modules through the PWM synchronization mechanism, greatly improves the flexibility and the applicability of the algorithm under the condition that a specific PWM channel is occupied, reasonably utilizes the prior art to realize the phase compensation of fixed time for the moment of sampling the trigger signal in a hardware sampling circuit, and improves the sampling accuracy and the sampling continuity.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
FIG. 1 is a circuit diagram of AD hardware sampling according to the present invention;
FIG. 2 is a timing diagram of the AD sampling of the present invention;
fig. 3 is a timing diagram illustrating phase compensation for AD sampling according to the present invention.
FIG. 4 is a synchronization flow chart of the PWM module according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
A DSP hardware sampling delay compensation method based on a PWM synchronization mechanism calculates delay time of hardware sampling circuits, and the sampling delay time is different for different sampling circuits. The PWM module is configured to enable the SOCB to trigger the ADC sample operation, and to enable the generation of the SOCB pulse to trigger the ADC sample when the PWM counter is at a countdown and equal to a set value of CMPB, according to the setting of the event trigger selection register. Therefore, delay sampling can be realized by properly selecting the setting value of the CMPB, so that phase compensation is carried out.
The CMPB of the PWM can be calculated according to the hardware sampling delay time and the clock frequency of the control chip of the sampling object, and the set value of the CMPB of the PWM is the hardware sampling delay time divided by the PWM clock period. And setting a proper value for a CMPB register of the PWM to realize time-delay sampling.
Because PWM has other applications, such as full-bridge inversion control topology of the driver chip, the duty ratio of four-way PWM to drive the chip is in real-time change, and cannot be used to perform fixed-time phase compensation at the moment when the ADC samples the trigger signal. Therefore, through a PWM synchronization mechanism, clock counters of all modules of PWM are completely synchronized, and the sampling trigger time of the ADC can be controlled through the setting of a CMPB register of the PWM1, so that the phase compensation of the delay of a hardware sampling circuit is realized.
The ACP ac power supply of this company will be described in more detail below as an example.
Referring to fig. 1, in an inductor current hardware sampling circuit of an ACP ac power supply, hardware sampling delay is calculated as follows:
hall current sensor sampling time delay T1 ═ 2.5us
First-order RC filtering delay: t2 ═ R2 ═ C1 ═ 1.5 ═ 103*2.2nF＝3.3us
The total delay is: t1+ T2 ═ 5.8us
And in consideration of the time delay of power electronic devices of other sampling circuits, the total time delay of the hardware sampling circuit of the inductive current is compensated to be 6 us.
Referring to fig. 2, the ACP ac power supply employs a fixed-frequency sampling mechanism based on PWM triggering, that is, an ADC sampling trigger signal is sent out by a PWM peripheral module in each switching period, and the ADC performs one round of sampling to form a sample-hold operation until a sampling time comes. In the current sampling mechanism of DSP: the output mode of PWM is bilateral symmetry type, when time base count TBTR is time base period TBPRD, produce a trigger signal that enables ePWM xSOCB, enable ADC sampling operation, after a round of ADC sampling is accomplished, trigger ADC interrupt, its sampling time sequence is as shown in figure 2.
Referring to fig. 3, in an ACP ac power supply, the EPWM module is configured to enable the SOCB triggered ADC sampling operation, and when the PWM counter is at a down count and equal to the value of CMPB, the SOCB pulse is generated to trigger the ADC sampling, so that delayed sampling can be achieved by selecting the appropriate CMPB. In an ACP alternating current power supply, a TMS320F2803x control chip is adopted, the PWM clock frequency is 60MHZ, the sampling delay time is 6us according to hardware, and the corresponding CMPB of PWM is the hardware sampling delay time length 6 x 10(-6)Division by the inverse 1/(60 x 10) of the PWM clock frequency6) That is, the hardware sampling delay time duration 6us is divided by the PWM clock cycle, so as to obtain the CMPB of PWM 360. The value of a count comparison value register CMPB of the PWM is set to 360, and when hardware sampling is carried out, the sampling trigger time of the ADC is artificially changed, so that phase compensation is carried out on a sampling waveform and an actual waveform.
Because the ACP ac power supply needs to adopt full-bridge inversion, 4 paths of PWM driving signals are needed, and two peripheral modules of PWM2 and PWM3 are respectively occupied, that is, four paths of PWM outputs, namely CMPA and CMPB of PWM2 and CMPA and CMPB of PWM3, change in real time according to the change of duty ratio, and therefore phase compensation for fixed time cannot be performed at the moment of sampling trigger signals of the ADC. Therefore, the method is realized by adopting a PWM synchronization mechanism of a TMS320F2803x control chip, clock synchronization setting is carried out through a TIME-BASE submodule in each EPWM module, and then phase synchronization of each PWM is configured. Setting a synchronization function through a PHSEN register; selecting which signal is used as a synchronous signal through a SYNCOSEL register; the phase change at the time of receiving the synchronization signal is set by the TBPHS register.
The synchronous input signal of each EPWM module can have three types: 1. EPWMxSYNCL, 2, software forced sync pulse, 3, digital compare event sync pulse. Configuring different PWM peripheral modules to enable synchronous signal receiving processing through an EPwmxRegs.TBCTL.bit.PHSEN register, namely each PWM module can receive or ignore the synchronous input signal through configuration, and if TBCTL [ PHSEN ] ═ 0, the EPWM module does not receive the synchronous signal of the previous EPWM module; if TBCTL [ PHSEN ] of the EPWM module is 1, when the EPWM module receives a synchronization signal, the content (phase difference) of TBPHS is automatically loaded into a TBCTR register to achieve the effect of synchronization with the previous EPWM module, the synchronization signal input source of the EPWM module is an EPWMxSYNCO synchronization output signal of the previous EPWM module, and the synchronization output signal is a set value of the EPWM module, wherein the counter value of the EPWM module is equal to CMPB.
The PHSEN register in TBCTL is used to enable this PWM (X) to be output with the sync signal of the previous PWM (X-1). Through the EPwmxRegs TBCTL.bit.SYNCOSEL register, the synchronous signal setting of different PWM peripheral modules is configured, namely the SYNCOSEL register in the TBCTL is used for outputting the synchronous output signal as a synchronous signal input source to the next PWM (X + 1). And through setting of an EPwmxRegs.TBPHS.half.TBPHS time-base phase register, the phase change of different PWM peripheral modules when receiving the synchronous signal is configured. Therefore, different register configuration values are reasonably selected, so that the PWM1 is used as a synchronous input signal of the PWM2, the PWM2 is used as a synchronous input signal of the PWM3, and finally, clock counters of all modules of all the PWMs are completely synchronous, so that the set value of the CMPB register of the PWM1 is set, the CMPB register of the PWM1 can perform fixed-time phase compensation on ADC sampling trigger time, and delay brought by a hardware sampling circuit is solved.
The embodiment of the invention also provides an electronic device based on digital control, which comprises an ADC sampling module and a PWM module, wherein the ADC sampling module is used for carrying out ADC sampling on the electronic device, the PWM module is used for configuring to enable the SOCB to trigger the ADC sampling, configuring to trigger the ADC sampling when the decrement of the PWM counter is equal to the set value of the CMPB register, and configuring to realize the synchronization of each path of PWM clock and phase, so that the CMPB register of the PWM1 can carry out phase compensation of fixed time on the ADC sampling trigger time. The set value of the CMPB register is the hardware sampling delay time divided by the PWM clock period, and the hardware sampling delay time is calculated according to a hardware sampling circuit used by the ADC sampling module. The digital control-based electronic device disclosed by the invention has the beneficial effects of the Digital Signal Processor (DSP) hardware sampling delay compensation method based on the PWM synchronization mechanism, can be an alternating current power supply, a direct current power supply, an electronic load and other digital control-related electronic devices, and all the electronic devices need sampling and PWM drive control, so the sampling delay compensation method can be adopted.
While the above description shows and describes the preferred embodiments of the present invention, it is to be understood that the invention is not limited to the forms disclosed herein, but is not to be construed as excluding other embodiments and is capable of use in various other combinations, modifications, and environments and is capable of changes within the scope of the inventive concept as expressed herein, commensurate with the above teachings, or the skill or knowledge of the relevant art. And that modifications and variations may be effected by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A DSP hardware sampling delay compensation method based on a PWM synchronization mechanism is characterized by comprising the following steps:
calculating the delay time of a hardware sampling circuit;
configuring to enable the SOCB to trigger the ADC sampling operation according to the PWM module;
determining a set value of a CMPB register;
triggering ADC sampling when the count of the PWM counter is equal to the set value of the CMPB register;
and the phase compensation of fixed time is carried out on the ADC sampling trigger moment through the synchronous setting of the PWM module.
2. The DSP hardware sampling delay compensation method based on the PWM synchronization mechanism according to claim 1, wherein: and the set value of the CMPB register is calculated according to the delay time and the clock frequency of the control chip of the sampling object.
3. The DSP hardware sampling delay compensation method based on the PWM synchronization mechanism according to claim 1, wherein: the set value of the CMPB register is the hardware sampling delay time length divided by the PWM clock period; and calculating the hardware sampling delay time according to the used hardware sampling circuit.
4. The DSP hardware sampling delay compensation method based on the PWM synchronization mechanism according to claim 3, wherein: the method for realizing the phase compensation of the ADC sampling trigger time for fixed time through the synchronous setting of the PWM module comprises the following steps:
the clocks TBCLK of each PWM are completely synchronous;
synchronizing the phases of all paths of PWM;
the timing at which the ADC samples the trigger signal is phase compensated for a fixed time by the setting of the CMPB register of PWM 1.
5. The DSP hardware sampling delay compensation method based on the PWM synchronization mechanism according to claim 4, wherein: the clock TBCLK of each PWM is completely synchronized and set by a TIME-BASE submodule in each PWM module.
6. The DSP hardware sampling delay compensation method based on the PWM synchronization mechanism according to claim 4, wherein: the method for realizing the phase synchronization of each path of PWM comprises the following steps:
configuring whether different PWM peripheral modules enable synchronous signal receiving processing or not;
configuring synchronous signal input sources of different PWM peripheral modules;
and configuring the phase change of different PWM peripheral modules when the PWM peripheral modules receive the synchronous signals.
7. The DSP hardware sampling delay compensation method based on the PWM synchronization mechanism according to claim 6, wherein: the complete synchronization and the phase synchronization of the clock TBCLK of each path of PWM are realized by adopting a TMS320F2803x control chip.
8. The DSP hardware sampling delay compensation method based on the PWM synchronization mechanism according to claim 7, wherein: and the synchronous signal input source of the PWM peripheral module is the PWMxSYNCO synchronous output signal of the last PWM module.
9. The method according to claim 8, wherein the method for compensating the sampling delay of the DSP hardware based on the PWM synchronization mechanism comprises: the synchronous output signal is that the counter value of the PWM module is equal to CMPB.
10. An electronic device based on digital control, comprising:
an ADC sampling module for ADC sampling of the electronic device;
the PWM module is used for configuring the SOCB to trigger ADC sampling, configuring the PWM counter to trigger ADC sampling when the countdown is equal to the set value of the CMPB register, and configuring to realize each path of PWM clock and phase synchronization;
the setting value of the CMPB register is the hardware sampling delay time divided by the PWM clock period; and the hardware sampling delay time length is calculated according to a hardware sampling circuit used by the ADC sampling module.
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| CN114609997A (en) * | 2022-03-07 | 2022-06-10 | 南京国电南自维美德自动化有限公司 | Method for realizing process control station analog input change rate protection |
| CN116557283A (en) * | 2023-07-10 | 2023-08-08 | 深圳艾为电气技术有限公司 | Current sampling precision control method and device for electric compressor controller |
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