CN105529364A - 用于esd保护的pldmos - Google Patents
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Abstract
本发明公开了一种用于ESD保护的PLDMOS,包括:P型外延层,沟道区,漂移区;漂移区包括P阱;在P阱和沟道区之间的所述P型外延层表面形成有第一局部场氧化层,第一局部场氧化层的第一侧边缘和P阱对准;在沟道区的表面上形成有由栅介质层和多晶硅栅;源区由形成于沟道区表面;漏区形成于P阱表面且和第一局部场氧化层的第一侧边缘对准接触;漂移区还包括形成于P阱表面的第二P型区,第二P型区的掺杂浓度小于漏区的掺杂浓度,第二P型区将漏区完全包围且横向延伸到所述第一局部场氧化层的第一侧边缘的鸟嘴结构的正下方。本发明能提高所述PLDMOS的抗ESD的能力。
Description
技术领域
本发明涉及一种半导体集成电路,特别是涉及一种用于ESD保护的P型横向扩散金属氧化物半导体(PLDMOS)。
背景技术
半导体集成电路中,静电释放(ESD)会对器件产生破坏作用,所以在集成电路的输入输出端需要设置ESD防护电路进行静电保护,现有用于ESD保护电路的器件包括横向扩散金属氧化物半导体(LDMOS)。其中,PLDMOS的寄生PNP器件主要是通过空穴来导通的,而空穴的迁移率远低于电子,因此其电流放大系数远小于NLDMOS即N型LDMOS寄生的NPN器件,导致常规PLDMOS的ESD保护能力极低;同时,因为PLDMOS的在ESD应力下工作原理更接近于反偏二极管,因此维持电压(Vh)较高,也导致了同样导通宽度的PLDMOS的功耗远比NLDMOS要大,限制了器件的抗ESD能力。现有做高压ESD保护用的LDMOS器件基本都是基于NLDMOS来设计。而NLDMOS有极强的回滞效应(snapback)即NLDMOS在触发电压触发后电流会增加但是电压会减小,最后电压减少到保持电压(Vh),Vh往往比工作电压低很多,带来较大的闩锁效应(latchup)风险。
如图1是所示,是现有用于ESD保护的PLDMOS结构示意图;现有用于ESD保护的PLDMOS包括:
P型外延层103,形成于半导体衬底如硅衬底101的表面,在P型外延层103的底部形成有N型埋层102。
在P型外延层103的表面中形成有局部场氧化层104。
沟道区105,由形成于所述P型外延层103中的N阱组成。
漂移区,由形成于所述P型外延层103中的P阱106组成;所述P阱106和所述沟道区105之间具有横向距离,且在所述P阱106和所述沟道区105之间的所述P型外延层103表面形成有一个局部场氧化层104,令该局部场氧化层104为第一局部场氧化层并单独用标记104a标出。所述第一局部场氧化层104a的第一侧边缘和所述P阱106对准,所述第一局部场氧化层104a的第二侧边缘和所述沟道区105之间具有横向距离。
在所述沟道区105的表面上形成有由栅介质层107和多晶硅栅108,所述多晶硅栅108的第一侧还横向延伸到所述第一局部场氧化层104a的表面上。
源区109,由形成于所述沟道区105表面中P+区组成,所述源区109和所述多晶硅栅108的第二侧自对准。
漏区110,由形成于所述P阱106表面中的P+区组成,所述漏区110和所述第一局部场氧化层104a的第一侧边缘对准接触。
在所述沟道区105表面中形成有由N+区组成的沟道电极引出区11。
源极通过接触孔和所述源区109接触,栅极通过接触孔和所述多晶硅栅108接触,漏极通过接触孔和所述漏区110接触。在ESD保护中,所述源极和所述栅极连接在一起作为阳极,所述漏极作为阴极。当ESD发生时,主要是通过由所述源区109,所述N阱即沟道区105,所述P型外延层103,所述P阱106以及所述P阱中P+区110形成的PNP来实现ESD触发并放电实现ESD保护。
图1所示的现有结构中,所述P阱106和所述漏区110都和所述第一局部场氧化层104a的第一侧边缘对准,而所述第一局部场氧化层104a的第一侧边缘具有鸟嘴结构,使得所述漏区110和所述P型外延层103之间容易在所述第一局部场氧化层104a的第一侧边缘的鸟嘴结构位置处电流集中引起ESD电流密度过大,从而使PLDMOS的抗ESD的能力降低。
发明内容
本发明所要解决的技术问题是提供一种用于ESD保护的PLDMOS,能提高所述PLDMOS的抗ESD的能力。
为解决上述技术问题,本发明提供的用于ESD保护的PLDMOS包括:
P型外延层。
沟道区,由形成于所述P型外延层中的N阱组成。
漂移区,所述漂移区的组成部分包括形成于所述P型外延层中的P阱;所述P阱和所述沟道区之间具有横向距离,且在所述P阱和所述沟道区之间的所述P型外延层表面形成有第一局部场氧化层,所述第一局部场氧化层的第一侧边缘和所述P阱对准,所述第一局部场氧化层的第二侧边缘和所述沟道区之间具有横向距离。
在所述沟道区的表面上形成有由栅介质层和多晶硅栅,所述多晶硅栅的第一侧还横向延伸到所述第一局部场氧化层的表面上。
源区,由形成于所述沟道区表面中P+区组成,所述源区和所述多晶硅栅的第二侧自对准。
漏区,由形成于所述P阱表面中的P+区组成,所述漏区和所述第一局部场氧化层的第一侧边缘对准接触。
所述漂移区的组成部分还包括形成于所述P阱表面的第二P型区,所述第二P型区的深度小于所述P阱的深度;所述第二P型区的掺杂浓度小于所述漏区的掺杂浓度,所述第二P型区的深度大于所述漏区的深度、所述第二P型区将所述漏区完全包围,所述第二P型区横向延伸到所述第一局部场氧化层的第一侧边缘的鸟嘴结构的正下方。
通过所述第二P型区的设置来减少所述漏区通过所述第一局部场氧化层的第一侧边缘的鸟嘴结构的电流密度来提高所述PLDMOS的抗ESD的能力。
进一步的改进是,所述第二P型区横向延伸到所述第一局部场氧化层的第一侧边缘的鸟嘴结构的正下方的边缘和所述漏区的边缘间的横向距离为0.2微米~1微米。
进一步的改进是,所述第二P型区在所述P阱形成后采用离子注入形成。
进一步的改进是,所述第二P型区采用P阱工艺形成。
进一步的改进是,所述P型外延层形成于半导体衬底表面,在所述P型外延层底部形成有N型埋层。
进一步的改进是,在所述沟道区表面中形成有由N+区组成的沟道电极引出区。
进一步的改进是,在所述源区和所属沟道电极引出区之间隔离有第二局部场氧化层。
进一步的改进是,层间膜覆盖在形成有所述源区、所述多晶硅栅和所述漏区的所述P型外延层表面;在所述层间膜中形成有穿过所述层间膜的接触孔;在所述层间膜的正面形成有正面金属层,所述正面金属层图形化形成源极、漏极和栅极,所述源极通过接触孔和所述源区接触,所述栅极通过接触孔和所述多晶硅栅接触,所述漏极通过接触孔和所述漏区接触。
进一步的改进是,在ESD保护中,所述源极和所述栅极连接在一起作为阳极,所述漏极作为阴极。
进一步的改进是,所述栅介质层为栅氧化层。
本发明通过在PLDMOS的漂移区P阱表面形成第二P型区,通过第二P型区将漏区完全包围并横向延伸到所述第一局部场氧化层的第一侧边缘的鸟嘴结构的正下方,通过将第二P型区的掺杂浓度小于漏区的掺杂浓度,能够避免在ESD发生时重掺杂的漏区通过鸟嘴和P型外延层之间产生ESD电流集中,从而能提高PLDMOS的抗ESD的能力。
附图说明
下面结合附图和具体实施方式对本发明作进一步详细的说明:
图1是现有用于ESD保护的PLDMOS结构示意图;
图2是本发明实施例用于ESD保护的PLDMOS结构示意图;
图3A是现有用于ESD保护的PLDMOS结构IV曲线和漏电流曲线;
图3B是本发明实施例用于ESD保护的PLDMOS结构IV曲线和漏电流曲线。
具体实施方式
如图2所示,是本发明实施例用于ESD保护的PLDMOS结构示意图;本发明实施例用于ESD保护的PLDMOS包括:
P型外延层3。所述P型外延层3形成于半导体衬底如硅衬底1表面,在所述P型外延层3底部形成有N型埋层2。
沟道区5,由形成于所述P型外延层3中的N阱组成。
漂移区,所述漂移区的组成部分包括形成于所述P型外延层3中的P阱6;所述P阱6和所述沟道区5之间具有横向距离,且在所述P阱6和所述沟道区5之间的所述P型外延层3表面形成有第一局部场氧化层4a,所述第一局部场氧化层4a的第一侧边缘和所述P阱6对准,所述第一局部场氧化层4a的第二侧边缘和所述沟道区5之间具有横向距离。
在所述沟道区5的表面上形成有由栅介质层7和多晶硅栅8,所述多晶硅栅8的第一侧还横向延伸到所述第一局部场氧化层4a的表面上。
源区9,由形成于所述沟道区5表面中P+区组成,所述源区9和所述多晶硅栅8的第二侧自对准。
漏区10,由形成于所述P阱6表面中的P+区组成,所述漏区10和所述第一局部场氧化层4a的第一侧边缘对准接触。
所述漂移区的组成部分还包括形成于所述P阱6表面的第二P型区12,所述第二P型区12的深度小于所述P阱6的深度;所述第二P型区12的掺杂浓度小于所述漏区10的掺杂浓度,所述第二P型区12的深度大于所述漏区10的深度、所述第二P型区12将所述漏区10完全包围,所述第二P型区12横向延伸到所述第一局部场氧化层4a的第一侧边缘的鸟嘴结构的正下方。
通过所述第二P型区12的设置来减少所述漏区10通过所述第一局部场氧化层4a的第一侧边缘的鸟嘴结构产生的漏电、降低所述PLDMOS的功耗和提高所述PLDMOS的抗ESD的能力;通过所述漂移区的P阱6、所述第二P型区12和所述P型外延层3和所述沟道区5组成的反偏二极管来提高PLDMOS在ESD保护中的维持电压。
较佳为,所述第二P型区12横向延伸到所述第一局部场氧化层4a的第一侧边缘的鸟嘴结构的正下方的边缘和所述漏区10的边缘间的横向距离为0.2微米~1微米。
所述第二P型区12在所述P阱6形成后采用离子注入形成或者所述第二P型区12采用P阱工艺形成,该P阱工艺可以和所述P阱6的工艺相同或类似。
在所述沟道区5表面中形成有由N+区组成的沟道电极引出区11。
在所述源区9和所属沟道电极引出区11之间隔离有第二局部场氧化层4。
层间膜覆盖在形成有所述源区9、所述多晶硅栅8和所述漏区10的所述P型外延层3表面;在所述层间膜中形成有穿过所述层间膜的接触孔;在所述层间膜的正面形成有正面金属层,所述正面金属层图形化形成源极、漏极和栅极,所述源极通过接触孔和所述源区9接触,所述栅极通过接触孔和所述多晶硅栅8接触,所述漏极通过接触孔和所述漏区10接触。
在ESD保护中,所述源极和所述栅极连接在一起作为阳极,所述漏极作为阴极。
如图3A所示,是现有用于ESD保护的PLDMOS结构的TLP曲线;曲线201是图1所示的PLDMOS的源漏电压和源漏电流之间的IV曲线,曲线202对应于每一次TLP测试后PLDMOS的源漏的漏电流(leakage)的大小,可以看出,在201a处漏电流急剧变大,表面PLDMOS已经出现二次击穿,对应的It2即ESD泄放电流只有0.1A。
作为比较,如图3B所示,是本发明实施例用于ESD保护的PLDMOS结构的TLP曲线。曲线301是图2所示的PLDMOS的源漏电压和源漏电流之间的IV曲线,可以看出,在标记301a对应的位置处存在一触发电压,经过触发电压后,PLDMOS进入泄放ESD电流工作模式,直到301b处出现明显的二次击穿;比较图3A的标记201a和图3B的标记301b所示位置可知,本发明实施例的泄放ESD能力从0.1A提高到了0.85A。
以上通过具体实施例对本发明进行了详细的说明,但这些并非构成对本发明的限制。在不脱离本发明原理的情况下,本领域的技术人员还可做出许多变形和改进,这些也应视为本发明的保护范围。
Claims (10)
1.一种用于ESD保护的PLDMOS,其特征在于,包括:
P型外延层;
沟道区,由形成于所述P型外延层中的N阱组成;
漂移区,所述漂移区的组成部分包括形成于所述P型外延层中的P阱;所述P阱和所述沟道区之间具有横向距离,且在所述P阱和所述沟道区之间的所述P型外延层表面形成有第一局部场氧化层,所述第一局部场氧化层的第一侧边缘和所述P阱对准,所述第一局部场氧化层的第二侧边缘和所述沟道区之间具有横向距离;
在所述沟道区的表面上形成有由栅介质层和多晶硅栅,所述多晶硅栅的第一侧还横向延伸到所述第一局部场氧化层的表面上;
源区,由形成于所述沟道区表面中P+区组成,所述源区和所述多晶硅栅的第二侧自对准;
漏区,由形成于所述P阱表面中的P+区组成,所述漏区和所述第一局部场氧化层的第一侧边缘对准接触;
所述漂移区的组成部分还包括形成于所述P阱表面的第二P型区,所述第二P型区的深度小于所述P阱的深度;所述第二P型区的掺杂浓度小于所述漏区的掺杂浓度,所述第二P型区的深度大于所述漏区的深度、所述第二P型区将所述漏区完全包围,所述第二P型区横向延伸到所述第一局部场氧化层的第一侧边缘的鸟嘴结构的正下方;
通过所述第二P型区的设置来减少所述漏区通过所述第一局部场氧化层的第一侧边缘的鸟嘴结构的电流密度来提高所述PLDMOS的抗ESD的能力。
2.如权利要求1所述用于ESD保护的PLDMOS,其特征在于:所述第二P型区横向延伸到所述第一局部场氧化层的第一侧边缘的鸟嘴结构的正下方的边缘和所述漏区的边缘间的横向距离为0.2微米~1微米。
3.如权利要求1所述用于ESD保护的PLDMOS,其特征在于:所述第二P型区在所述P阱形成后采用离子注入形成。
4.如权利要求3所述用于ESD保护的PLDMOS,其特征在于:所述第二P型区采用P阱工艺形成。
5.如权利要求1所述用于ESD保护的PLDMOS,其特征在于:所述P型外延层形成于半导体衬底表面,在所述P型外延层底部形成有N型埋层。
6.如权利要求1所述用于ESD保护的PLDMOS,其特征在于:在所述沟道区表面中形成有由N+区组成的沟道电极引出区。
7.如权利要求6所述用于ESD保护的PLDMOS,其特征在于:在所述源区和所属沟道电极引出区之间隔离有第二局部场氧化层。
8.如权利要求1所述用于ESD保护的PLDMOS,其特征在于:层间膜覆盖在形成有所述源区、所述多晶硅栅和所述漏区的所述P型外延层表面;在所述层间膜中形成有穿过所述层间膜的接触孔;在所述层间膜的正面形成有正面金属层,所述正面金属层图形化形成源极、漏极和栅极,所述源极通过接触孔和所述源区接触,所述栅极通过接触孔和所述多晶硅栅接触,所述漏极通过接触孔和所述漏区接触。
9.如权利要求8所述用于ESD保护的PLDMOS,其特征在于:在ESD保护中,所述源极和所述栅极连接在一起作为阳极,所述漏极作为阴极。
10.如权利要求1所述用于ESD保护的PLDMOS,其特征在于:所述栅介质层为栅氧化层。
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