CN105529051A - ROM unit, reading method and apparatus thereof - Google Patents
ROM unit, reading method and apparatus thereof Download PDFInfo
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- CN105529051A CN105529051A CN201410513640.2A CN201410513640A CN105529051A CN 105529051 A CN105529051 A CN 105529051A CN 201410513640 A CN201410513640 A CN 201410513640A CN 105529051 A CN105529051 A CN 105529051A
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- bit line
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Abstract
The invention relates to a ROM unit, a reading method and an apparatus thereof. The ROM unit comprises at least two read-only storage unit groups, the read-only storage unit groups comprise a first transistor and a second transistor, the grid ends of the first transistor and the second transistor are respectively connected with a first word line and a second word line, the first transistor and the second transistor share a same source end and a same drain terminal, and the drain terminal is adapted to vacancy or is respectively connected with a first bit line, a second bit line or a third bit line according to information stored in the read-only storage unit groups. The above scheme can increase storage density of the ROM unit.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to a kind of ROM cell and read method thereof and device.
Background technology
ROM (read-only memory) (Read-OnlyMemory, ROM) is a kind of solid state semiconductor memory that can only read prior stored data.Its characteristic is just cannot again by it change or deletion once store data, usually be used in the electronics or computer system not needing often to change data, and data can not lose ROM stored data because of power-off, finish writing in advance before generally loading complete machine, can only read in whole working, and can be rewritten rapidly, easily unlike random access memory.ROM stored data is stablized, and after power-off, stored data also can not change; Its structure is comparatively simple, reads more convenient, is thus usually used in storing various fixed routine and data.
In prior art, ROM cell, owing to sharing source, also exists the problem that storage density is low.
Summary of the invention
What the embodiment of the present invention solved is the problem of the storage density how improving ROM cell.
For solving the problem, embodiments provide a kind of ROM cell, described ROM cell comprises:
At least two read-only memory unit groups, described read-only memory unit group comprises the first transistor, transistor seconds, described the first transistor is connected with the first wordline and the second wordline respectively with the grid end of transistor seconds, described the first transistor and transistor seconds share same source and same drain terminal, and described drain terminal is suitable for the information according to storing in described read-only memory unit group, vacant or be connected with the first bit line, described second bit line or the 3rd bit line respectively.
Alternatively, described drain terminal is suitable for the information according to storing in described read-only memory unit, vacant or be connected with described first bit line, described second bit line or the 3rd bit line respectively, comprising:
When the information that described drain terminal is suitable for storing in described read-only memory unit group is 00, be connected with described second bit line;
When the information that described drain terminal is suitable for storing in described read-only memory unit group is 01, be connected with described first bit line;
When the information that described drain terminal is suitable for storing in described read-only memory unit group is 10, be connected with described 3rd bit line;
When the information that described drain terminal is suitable for storing in described read-only memory unit group is 11, vacant.
Alternatively, described the first transistor, transistor seconds are metal-oxide half field effect transistor.
The embodiment of the present invention additionally provides a kind of read method of ROM cell, and described method comprises:
When reading the information stored in the first transistor in read-only memory unit group, read the information of described first bit line and the second bit line simultaneously; When described first bit line and described second bit line are high level state, the information stored in the described the first transistor read is 1; When having at least a bit lines to be low level state in described first bit line and described second bit line, the information stored in the described the first transistor read is 0;
When reading the information stored in transistor seconds in read-only memory unit group, read the information of described second bit line and the 3rd bit line simultaneously; When described second bit line and described 3rd bit line are high level state, the information stored in the described transistor seconds read is 1; When having at least a bit lines to be low level in described second bit line and described 3rd bit line, the information stored in the described transistor seconds read is 0.
The embodiment of the present invention additionally provides a kind of reading device of ROM cell, and described device comprises:
First reading unit, is suitable for, when reading the information stored in the first transistor in read-only memory unit group, reading the information of described first bit line and the second bit line simultaneously; When described first bit line and described second bit line are high level state, the information stored in described the first transistor is 1; When having at least a bit lines to be low level state in described first bit line and described second bit line, the information stored in described the first transistor is 0;
Second reading unit, is suitable for, when reading the information stored in transistor seconds in read-only memory unit group, reading the information of described second bit line and the 3rd bit line simultaneously; When described second bit line and described 3rd bit line are high level state, the information stored in the described transistor seconds read is 1; When having at least a bit lines to be low level in described second bit line and described 3rd bit line, the information stored in the described transistor seconds read is 0.
Compared with prior art, technical scheme of the present invention has following advantage:
By arranging three bit lines for ROM cell, make in read-only memory unit group that the first transistor and transistor seconds can when shared same sources and drain terminal, by described drain terminal is connected from different bit lines, separate with the information realizing storing in the first transistor and transistor seconds, therefore, the longitudinal size of described ROM cell can be reduced, improve the storage density of ROM cell.
Accompanying drawing explanation
Fig. 1 is the structural representation of a kind of ROM cell of the prior art;
Fig. 2 is the structural representation of another kind of ROM cell of the prior art;
Fig. 3 is the structural representation of a kind of ROM cell in the embodiment of the present invention;
Fig. 4 is the schematic diagram sharing drain terminal in a kind of ROM cell in the embodiment of the present invention between read-only memory unit group;
Fig. 5 is the structure printing domain of a kind of ROM cell in the embodiment of the present invention;
Fig. 6 is the process flow diagram of the read method of a kind of ROM cell in the embodiment of the present invention;
Fig. 7 is the structural representation of the reading device of a kind of ROM cell in the embodiment of the present invention.
Embodiment
Refer to shown in Fig. 1 and Fig. 2, in prior art, ROM cell can comprise: the first transistor 11 and transistor seconds 12, wherein, adopt back-to-back connected mode between the first transistor 11 and transistor seconds 12, the first transistor 11 is connected with ground wire (VSS) by same source with transistor seconds 12.The transistor connected mode of this shared source, can reduce the storage area shared by ROM cell.
In order to realize sharing same source between the first transistor 11 and transistor seconds 12, in prior art, between the first transistor 11 and transistor seconds 12, structural relation mainly contains the following two kinds mode:
A kind of mode is disconnected the active area of described the first transistor 11 and transistor seconds 12, forms isolated area.
Another kind of mode is linked together the active area of described the first transistor 11 and transistor seconds 12, and increase the polysilicon that one deck is connected with VSS on the active area, to form the third transistor 13 of an off state simultaneously.Because described third transistor 13 is off state, isolated area can be formed between the first transistor 11 and transistor seconds 12, make to be independent of each other between the information that stores in the first transistor 11 and transistor seconds 12.
Although share same source between the first transistor 11 and transistor seconds 12, the area shared by ROM cell can be saved to a certain extent, but, due to the existence of described third transistor, and do not store any information in third transistor, therefore, ROM cell of the prior art still also exists the low problem of storage density.
For solving the above-mentioned problems in the prior art, the technical scheme that the embodiment of the present invention adopts, by arranging three bit lines for ROM cell, can reduce the longitudinal size of described ROM cell, improves the storage density of ROM cell.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
Fig. 3 shows the structural representation of a kind of ROM cell in the embodiment of the present invention.ROM cell as shown in Figure 3, at least can comprise:
Read-only memory unit group 301 and read-only memory unit group 302, described read-only memory unit group 301 and read-only memory unit group 302 have identical structure, can comprise the first transistor, transistor seconds respectively.Wherein, the first transistor is connected with the first wordline WL1 and the second wordline WL2 respectively with the grid end of transistor seconds, described the first transistor and transistor seconds share same source and same drain terminal, and described drain terminal is suitable for the information according to storing in described read-only memory unit group 301, vacant or be connected with the first bit line BL1, described second bit line BL2 or the 3rd bit line BL3 respectively.
In concrete enforcement, described drain terminal is according to the information stored in described read-only memory unit, and vacant or the first bit line BL1, described second bit line BL2 or the 3rd bit line BL3, can comprise:
When the information stored in described read-only memory unit group is 00, also namely the first wordline WL1 is programmed for 0, and when the second wordline WL2 is programmed for 0, described drain terminal can be connected with described second bit line BL2 by programming hole.
When the information stored in described read-only memory unit group is 01, also namely the first wordline WL1 is programmed for 0, and when the second wordline WL2 is programmed for 1, described drain terminal can be connected with described first bit line BL1 by programming hole.
When the information stored in described read-only memory unit group is 10, also namely the first wordline WL1 is programmed for 1, and when the second wordline WL2 is programmed for 0, described drain terminal can be connected with described 3rd bit line BL3 by programming hole.
When the information stored in described read-only memory unit group is 11, when also namely the first wordline WL1 and the second wordline WL2 is all programmed for 1, described drain terminal is vacant, is not all connected with the first bit line BL1, described second bit line BL2 and the 3rd bit line BL3.
Shown in Figure 4, when the information stored in adjacent read-only memory unit group 401 with read-only memory unit group 402 is identical, the respective public drain terminal of read-only memory unit group 401 and read-only memory unit group 402 is by when being connected (please refer to dotted line frame region 403 shown) with identical bit line by programming hole, such as be connected with the first bit line BL1 simultaneously, now, the public drain terminal of the public drain terminal of read-only memory unit 401 and read-only memory unit 402 can be combined (please refer to shown in dotted line frame region 404).Like this, the first transistor in read-only memory unit group 401 and read-only memory unit 402 and transistor seconds can share drain terminal, the common drain terminal of read-only memory unit group 401 and read-only memory unit 402 also can share, thus can reduce the size of ROM cell further, and then the information storage density of ROM cell can be improved.
Shown in Figure 5, pentagram in figure represents the programming hole on public drain terminal, when the information stored in the read-only memory unit group of three in ROM cell is 001001, the programming hole being positioned at the public drain terminal of described first read-only memory unit group on Article 2 bit line BL2 is connected with described second bit line BL2 respectively, the programming hole being positioned at the public drain terminal of described second read-only memory unit group on described Article 3 bit line BL3 is connected with described 3rd bit line BL3 respectively, the programming hole being positioned at the public drain terminal of described 3rd read-only memory unit group on Article 1 bit line BL1 is connected with described second bit line BL2 respectively.Due to every 2 programming holes between in bit line direction across 2 wordline WL and sources (VSS), thus can meet the designing requirement of more advanced technologies.
In concrete enforcement, described the first transistor, transistor seconds can be metal-oxide half field effect transistor, also can be the transistor of other types.
Fig. 6 shows the process flow diagram of the read method of a kind of ROM cell in the embodiment of the present invention.The read method of ROM cell as shown in Figure 6, can comprise:
In concrete enforcement, because ROM cell has three bit lines, wherein when reading the information stored in each read-only memory unit, following mode can be adopted to read:
Step S601: when reading the information stored in the first transistor in read-only memory unit group, simultaneously read the information of described first bit line and the second bit line.
When described first bit line and described second bit line are high level state, the information stored in the described the first transistor read is 1; When having at least a bit lines to be low level state in described first bit line and described second bit line, the information stored in the described the first transistor read is 0.
Step S602: when reading the information stored in transistor seconds in read-only memory unit group, simultaneously read the information of described second bit line and the 3rd bit line.
When described second bit line and described 3rd bit line are high level state, the information stored in the described transistor seconds read is 1; When having at least a bit lines to be low level in described second bit line and described 3rd bit line, the information stored in the described transistor seconds read is 0.
Fig. 7 shows the structural representation of the reading device of a kind of ROM cell in the embodiment of the present invention.The reading device of ROM cell as shown in Figure 7, can comprise the first reading unit 701 and the second reading unit 702, wherein:
First reading unit 701, is suitable for, when reading the information stored in the first transistor in read-only memory unit group, reading the information of described first bit line and the second bit line simultaneously; When described first bit line and described second bit line are high level state, the information stored in described the first transistor is 1; When having at least a bit lines to be low level state in described first bit line and described second bit line, the information stored in described the first transistor is 0.
Second reading unit 702, is suitable for, when reading the information stored in transistor seconds in read-only memory unit group, reading the information of described second bit line and the 3rd bit line simultaneously; When described second bit line and described 3rd bit line are high level state, the information stored in the described transistor seconds read is 1; When having at least a bit lines to be low level in described second bit line and described 3rd bit line, the information stored in the described transistor seconds read is 0.
One of ordinary skill in the art will appreciate that all or part of step in the various methods of above-described embodiment is that the hardware that can carry out instruction relevant by program has come, this program can be stored in computer-readable recording medium, and storage medium can comprise: ROM, RAM, disk or CD etc.
Done detailed introduction to the method and system of the embodiment of the present invention above, the present invention is not limited to this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (5)
1. a ROM cell, it is characterized in that, comprise at least two read-only memory unit groups, described read-only memory unit group comprises the first transistor, transistor seconds, described the first transistor is connected with the first wordline and the second wordline respectively with the grid end of transistor seconds, described the first transistor and transistor seconds share same source and same drain terminal, and described drain terminal is suitable for the information according to storing in described read-only memory unit group, vacant or be connected with the first bit line, described second bit line or the 3rd bit line respectively.
2. ROM cell according to claim 1, is characterized in that, described drain terminal is suitable for the information according to storing in described read-only memory unit, vacant or be connected with described first bit line, described second bit line or the 3rd bit line respectively, comprising:
When the information that described drain terminal is suitable for storing in described read-only memory unit group is 00, be connected with described second bit line;
When the information that described drain terminal is suitable for storing in described read-only memory unit group is 01, be connected with described first bit line;
When the information that described drain terminal is suitable for storing in described read-only memory unit group is 10, be connected with described 3rd bit line;
When the information that described drain terminal is suitable for storing in described read-only memory unit group is 11, vacant.
3. ROM cell according to claim 1, is characterized in that, described the first transistor, transistor seconds are metal-oxide half field effect transistor.
4. a read method for ROM cell, is characterized in that, comprising:
When reading the information stored in the first transistor in read-only memory unit group, read the information of described first bit line and the second bit line simultaneously; When described first bit line and described second bit line are high level state, the information stored in the described the first transistor read is 1; When having at least a bit lines to be low level state in described first bit line and described second bit line, the information stored in the described the first transistor read is 0;
When reading the information stored in transistor seconds in read-only memory unit group, read the information of described second bit line and the 3rd bit line simultaneously; When described second bit line and described 3rd bit line are high level state, the information stored in the described transistor seconds read is 1; When having at least a bit lines to be low level in described second bit line and described 3rd bit line, the information stored in the described transistor seconds read is 0.
5. a reading device for ROM cell, is characterized in that, comprising:
First reading unit, is suitable for, when reading the information stored in the first transistor in read-only memory unit group, reading the information of described first bit line and the second bit line simultaneously; When described first bit line and described second bit line are high level state, the information stored in described the first transistor is 1; When having at least a bit lines to be low level state in described first bit line and described second bit line, the information stored in described the first transistor is 0;
Second reading unit, is suitable for, when reading the information stored in transistor seconds in read-only memory unit group, reading the information of described second bit line and the 3rd bit line simultaneously; When described second bit line and described 3rd bit line are high level state, the information stored in the described transistor seconds read is 1; When having at least a bit lines to be low level in described second bit line and described 3rd bit line, the information stored in the described transistor seconds read is 0.
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| CN201410513640.2A CN105529051B (en) | 2014-09-29 | 2014-09-29 | ROM unit and reading method and device thereof |
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| CN201410513640.2A CN105529051B (en) | 2014-09-29 | 2014-09-29 | ROM unit and reading method and device thereof |
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| CN102005247A (en) * | 2009-08-28 | 2011-04-06 | Arm有限公司 | Read only memory cell for storing a multiple bit value |
| US20110211382A1 (en) * | 2010-02-28 | 2011-09-01 | Freescale Semiconductor, Inc. | High density and low variability read only memory |
| CN103093823A (en) * | 2013-01-21 | 2013-05-08 | 苏州兆芯半导体科技有限公司 | ROM (Read Only Memory) and layout thereof |
| US20130170277A1 (en) * | 2010-04-01 | 2013-07-04 | Broadcom Corporation | Encoded Read-Only Memory (ROM) Bitcell, Array, and Architecture |
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2014
- 2014-09-29 CN CN201410513640.2A patent/CN105529051B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102005247A (en) * | 2009-08-28 | 2011-04-06 | Arm有限公司 | Read only memory cell for storing a multiple bit value |
| US20110211382A1 (en) * | 2010-02-28 | 2011-09-01 | Freescale Semiconductor, Inc. | High density and low variability read only memory |
| US20130170277A1 (en) * | 2010-04-01 | 2013-07-04 | Broadcom Corporation | Encoded Read-Only Memory (ROM) Bitcell, Array, and Architecture |
| CN103093823A (en) * | 2013-01-21 | 2013-05-08 | 苏州兆芯半导体科技有限公司 | ROM (Read Only Memory) and layout thereof |
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Effective date of registration: 20201222 Address after: Room 501, block C, Yingying building, 99 Tuanjie Road, yanchuangyuan, high tech Development Zone, Nanjing, Jiangsu, 211800 Patentee after: ZHANXUN SEMICONDUCTOR (NANJING) Co.,Ltd. Address before: 201203 Shanghai Pudong New Area Pudong Zhangjiang hi tech park, 2288 Chong Nong Road, exhibition center, 1 building. Patentee before: SPREADTRUM COMMUNICATIONS (SHANGHAI) Co.,Ltd. |
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