CN105788643B - ROM cell and its read method and device, memory - Google Patents
ROM cell and its read method and device, memory Download PDFInfo
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- CN105788643B CN105788643B CN201410821883.2A CN201410821883A CN105788643B CN 105788643 B CN105788643 B CN 105788643B CN 201410821883 A CN201410821883 A CN 201410821883A CN 105788643 B CN105788643 B CN 105788643B
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Abstract
A kind of ROM cell and its read method and device, memory, the ROM cell includes: at least one column MOSFET, each column MOSFET includes more than two MOSFET successively coupled, each MOSFET is respectively provided with grid end, the first active area and the second active area, and the adjacent active area of two adjacent MOSFET shares, wherein, the first active area of the MOSFET is suitable for the information stored in the MOSFET according to the same row previous row adjacent with the MOSFET, selects to connect with ground wire, the first bit line, the second bit line or third bit line；The second active area of the MOSFET is suitable for according to the connection relationship between the first active area and ground wire of the MOSFET, the first bit line, the second bit line or third bit line, and the information stored in the MOSFET, it selects to connect with the ground wire, first bit line, second bit line or the third bit line.Above-mentioned scheme can reduce the longitudinal size of the ROM cell, improve the storage density of ROM cell.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of ROM cell and its read method and device, storage
Device.
Background technique
Memory (Read-Only Memory, ROM) is that a kind of solid-state semiconductor that can only read prior stored data is deposited
Reservoir.Its characteristic be once storing data can not again by change or delete, be generally used for being not required to often changing the electricity of data
In son or computer system, and data will not lose ROM stored data because power supply is closed, and generally be loaded into before complete machine in advance
It finishes writing, can only be read in whole working, can rapidly, easily be rewritten like that rather than random access memory.ROM
Stored data is stablized, and stored data will not change after power-off；Its structure is simpler, and reading is more convenient, thus is usually used in storing
Various fixed routines and data.
In the prior art, the source of the MOSFET in ROM cell can share, and still, ask there is storage density is low
Topic.
Summary of the invention
The problem of what the embodiment of the present invention solved is how to improve the storage density of ROM cell.
To solve the above problems, the embodiment of the invention provides a kind of ROM cell, the ROM cell includes:
At least one column MOSFET, each column MOSFET includes more than two MOSFET, each MOSFET successively coupled
It is respectively provided with grid end, the first active area and the second active area, and the adjacent active area of two adjacent MOSFET shares,
In,
The first active area of the MOSFET is suitable for the MOSFET according to the same row previous row adjacent with the MOSFET
The information of middle storage selects to connect with ground wire, the first bit line, the second bit line or third bit line；
The second active area of the MOSFET be suitable for according to the first active area of the MOSFET and ground wire, the first bit line,
The information stored in connection relationship and the MOSFET between second bit line or third bit line, with the ground wire, described
First bit line, second bit line or third bit line selection connection.
Optionally, the first active area of the MOSFET is suitable for depositing in the basis previous MOSFET adjacent with the MOSFET
The information of storage selects to connect with ground wire, the first bit line, the second bit line or third bit line, comprising:
When the first active area of the MOSFET of the same row previous row, the second active area are connect with the ground wire,
The first active area of the MOSFET is suitable for connecting with the ground wire；
When the first active area of the MOSFET of the same row previous row, the second active area respectively with the ground wire, described
When first bit line connects, the first active area of the MOSFET is suitable for connecting with the ground wire；
When the first active area of the MOSFET of the same row previous row, the second active area respectively with the ground wire, described
When second bit line is separately connected, the first active area of the MOSFET is suitable for connecting with second bit line；
When the first active area of the MOSFET of the same row previous row, the second active area respectively with the ground wire, described
When third bit line is separately connected, the first active area of the MOSFET is suitable for connecting with the third bit line；
When the first active area of the MOSFET of the same row previous row, the second active area respectively with first bit line,
When the ground wire is separately connected, the first active area of the MOSFET is suitable for connecting with the ground wire；
When the first active area, the second active area of the MOSFET of the same row previous row are connect with first bit line
When, the first active area of the MOSFET is suitable for connecting with first bit line；
When the first active area of the MOSFET of the same row previous row, the second active area respectively with first bit line,
When second bit line is separately connected, the first active area of the MOSFET is suitable for connecting with second bit line；
When the first active area of the MOSFET of the same row previous row, the second active area respectively with first bit line,
When the third bit line is separately connected, the first active area of the MOSFET is suitable for connecting with the third bit line；
When the first active area of the MOSFET of the same row previous row, the second active area respectively with second bit line,
When the ground wire is separately connected, the first active area of the MOSFET is suitable for connecting with the ground wire；
When the first active area of the MOSFET of the same row previous row, the second active area respectively with second bit line,
When first bit line is separately connected, the first active area of the MOSFET is suitable for connecting with first bit line；
When the first active area, the second active area of the MOSFET of the same row previous row are connect with second bit line
When, the first active area of the MOSFET is suitable for connecting with the ground wire；
When the first active area of the MOSFET of the same row previous row, the second active area respectively with second bit line,
When the third bit line is separately connected, the first active area of the MOSFET is suitable for connecting with the third bit line；
When the first active area of the MOSFET of the same row previous row, the second active area respectively with the third bit line,
When the ground wire is separately connected, the first active area of the MOSFET is suitable for connecting with the ground wire；
When the first active area of the MOSFET of the same row previous row, the second active area respectively with the third bit line,
When first bit line is separately connected, the first active area of the MOSFET is suitable for connecting with first bit line；
When the first active area of the MOSFET of the same row previous row, the second active area respectively with the third bit line,
When second bit line is separately connected, the first active area of the MOSFET is suitable for connecting with second bit line；
When the first active area, the second active area of the MOSFET of the same row previous row are connect with the third bit line
When, the first active area of the MOSFET is suitable for connecting with the third bit line.
Optionally, the second active area of the MOSFET is suitable for according to the first active area of the MOSFET and ground wire, the
The information stored in connection relationship and the MOSFET between one bit line, the second bit line or third bit line, with described
Line, first bit line, second bit line or third bit line connection, comprising:
The information that the second active area of the MOSFET is suitable for storing in the MOSFET is 00, and the MOSFET
When first active area is connect with the ground wire, it is connect with second bit line；
The information that the second active area of the MOSFET is suitable for storing in the MOSFET is 00, and the MOSFET
When first active area is connect with first bit line, it is connect with the third bit line；
The information that the second active area of the MOSFET is suitable for storing in the MOSFET is 00, and the MOSFET
When first active area is connect with first bit line, it is connect with the ground wire；
The information that the second active area of the MOSFET is suitable for storing in the MOSFET is 00, and the MOSFET
When first active area is connect with the third, it is connect with first bit line；
The information that the second active area of the MOSFET is suitable for storing in the MOSFET is 01, and the MOSFET
When first active area is connect with the ground wire, it is connect with the third bit line；
The information that the second active area of the MOSFET is suitable for storing in the MOSFET is 01, and the MOSFET
When first active area is connect with first bit line, it is connect with the third bit line；
The information that the second active area of the MOSFET is suitable for storing in the MOSFET is 01, and the MOSFET
When first active area is connect with second bit line, it is connect with first bit line；
The information that the second active area of the MOSFET is suitable for storing in the MOSFET is 01, and the MOSFET
When first active area is connect with the third bit line, it is connect with the ground wire；
The information that the second active area of the MOSFET is suitable for storing in the MOSFET is 10, and the MOSFET
When first active area is connect with the ground wire, it is connect with first bit line；
The information that the second active area of the MOSFET is suitable for storing in the MOSFET is 10, and the MOSFET
When first active area is connect with first bit line, it is connect with the ground wire；
The information that the second active area of the MOSFET is suitable for storing in the MOSFET is 10, and the MOSFET
When first active area is connect with second bit line, it is connect with the third bit line；
The information that the second active area of the MOSFET is suitable for storing in the MOSFET is 10, and the MOSFET
When first active area is connect with the third bit line, it is connect with second bit line；
The information that the second active area of the MOSFET is suitable for storing in the MOSFET is 11, and the MOSFET
When first active area is connect with the ground wire, it is connect with the ground wire；
The information that the second active area of the MOSFET is suitable for storing in the MOSFET is 11, and the MOSFET
When first active area is connect with first bit line, it is connect with first bit line；
The information that the second active area of the MOSFET is suitable for storing in the MOSFET is 11, and the MOSFET
When first active area is connect with second bit line, first it is connect with the second；
The information that the second active area of the MOSFET is suitable for storing in the MOSFET is 11, and the MOSFET
When first active area is connect with the third bit line, it is connect with the third bit line.
The embodiment of the invention also provides a kind of memory, the above-mentioned ROM cell of the memory.
The embodiment of the invention also provides a kind of read methods of ROM cell, which is characterized in that the ROM cell includes
The information of two bits, respectively the first bit are stored in the MOSFET that two or more successively couples, each MOSFET
Position and the second bit, comprising:
When reading the information of first bit, first bit line and second bit line are pre-charged supreme
Level, and the third bit line is precharged to low level, while reading the information of first bit line and second bit line,
When there are when high level to low level access, then read described first compares in first bit line and second bit line
The information of special position storage is 0；When there is no from high level to low level access in first bit line and second bit line
When, the information of read first bit is 1；
When reading the information of second bit, second bit line and the third bit line are pre-charged supreme
Level, and first bit line is precharged to low level, while reading the information of second bit line and the third bit line,
When there are when high level to low level access, then read described second compares in second bit line and the third bit line
The information of special position storage is 0；When there is no from high level to low level access in second bit line and the third bit line
When, the information of read second bit is 1.
The embodiment of the invention also provides a kind of reading device of ROM cell, what the ROM cell at least one arranged
MOSFET, and include more than two sequentially connected MOSFET in same row, two bits are stored in each MOSFET
The information of position, respectively the first bit and the second bit, described device include:
First reading unit, suitable for when reading the information of first bit, by first bit line and described the
Two bit lines are precharged to high level, and the third bit line is precharged to low level, at the same read first bit line and
The information of second bit line, when in first bit line and second bit line there are when high level to low level access,
Then the information of the read first bit storage is 0；When in first bit line and second bit line there is no from
When high level to low level access, the information of read first bit is 1；
Second reading unit, suitable for when reading the information of second bit, by second bit line and described the
Three bit lines are precharged to high level, and first bit line is precharged to low level, at the same read second bit line and
The information of the third bit line, when in second line and the third bit line there are when high level to low level access, then
The information of the read second bit storage is 0；When second bit line is not present with the third bit line from height
When level to low level access, the information of read first bit is 1.
Compared with prior art, technical solution of the present invention has the advantage that
By the way that a ground wire and three bit lines, and two not gone together in same row in the ROM cell are arranged for ROM cell
Same active area is shared between a adjacent MOSFET, and the first active area of each MOSFET is suitable for previous according to same row
The second active area of capable MOSFET is determined, and the second active area of the MOSFET is first active suitable for the MOSFET's
The letter stored in connection relationship and the MOSFET between area and ground wire, the first bit line, the second bit line or third bit line
Breath, connect with the ground wire, first bit line, second bit line or the third bit line, may be implemented each
Can be mutually indepedent between the information that can store the information of two bits in MOSFET, and stored in MOSFET, it therefore, can
To reduce the longitudinal size of the ROM cell, the storage density of ROM cell is improved.
Detailed description of the invention
Fig. 1 is a kind of structural schematic diagram of ROM cell in the prior art；
Fig. 2 is the structural schematic diagram of another ROM cell in the prior art；
Fig. 3 is the flow chart of the read method of one of embodiment of the present invention ROM cell；
Fig. 4 is the structural schematic diagram of the reading device of one of embodiment of the present invention ROM cell；
Fig. 5 is the structural schematic diagram of one of embodiment of the present invention ROM cell；
Fig. 6 is the printing structure domain of another ROM cell in the embodiment of the present invention.
Specific embodiment
Referring to Figure 1 and shown in Fig. 2, ROM cell may include: MOSFET11 and MOSFET12 in the prior art, wherein
Same source and ground are passed through using back-to-back connection type, MOSFET11 and MOSFET12 between MOSFET11 and MOSFET12
Line (VSS) connection.The transistor connection type of this shared source, it is possible to reduce the occupied storage area of ROM cell.
Same source is shared between MOSFET11 and MOSFET12 in order to realize, in the prior art, MOSFET11 with
Structural relation mainly has following two ways between MOSFET12:
A kind of mode is to disconnect the active area of the MOSFET11 and MOSFET12, forms isolated area.
Another way is that the active area of the MOSFET11 and MOSFET12 links together, and simultaneously in active area
One layer of polysilicon being connect with VSS of upper increase, to form the MOSFET13 of an off state.Since the MOSFET13 is shutdown
State can form isolated area between MOSFET11 and MOSFET12, so that the letter stored in MOSFET11 and MOSFET12
It is independent of each other between breath.
Although sharing same source between MOSFET11 and MOSFET12, ROM cell institute can be saved to a certain extent
The area of occupancy still due to the presence of the MOSFET13, and is not stored with any information in MOSFET13, therefore,
ROM cell in the prior art remains the low problem of storage density.
For solve the above-mentioned problems in the prior art, technical solution used in the embodiment of the present invention by for ROM it is mono-
Member three bit lines of setting, can reduce the longitudinal size of the ROM cell, improve the storage density of ROM cell.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
In order to enable the description of the technical solution in the embodiment of the present invention is simpler understandable, it below will be first to the present invention
The read method of one of embodiment ROM cell does detailed introduction.
It in specific implementation, may include the MOSFET of a column or more, same row in ROM cell in the embodiment of the present invention
The adjacent active regions of two adjacent MOSFET share in MOSFET, it may be assumed that the second active area of the MOSFET of same row previous row
The first active area with the MOSFET of current line is same active area.
Wherein, the information there are two bit, the i.e. letter of the first bit and the second bit are stored in each MOSFET
Breath, wherein the first bit is low level, and the second bit is a high position.When the information stored in reading MOSFET, it can distinguish
The information for reading corresponding two bit lines, specifically refers to Fig. 3 and shows.
Fig. 3 has gone out the flow chart of the read method of one of embodiment of the present invention ROM cell.The ROM cell shown such as Fig. 3
Read method, may include:
Step S301: when reading the information of first bit, first bit line and second bit line is equal
It is precharged to high level, and the third bit line is precharged to low level, while reading first bit line and described second
The information of bit line, when there are when high level to low level access, then being read in first bit line and second bit line
First bit storage information be 0；When in first bit line and second bit line there is no from high level to
When low level access, the information of read first bit is 1.
In specific implementation, each MOSFET in ROM cell can store the information of two bits simultaneously.Wherein,
When reading the information of the first bit, first by two bit lines to be read in three bit lines of ROM cell, i.e. the first bit line
BL0 and the second bit line BL1 are precharged to high level state, and the second bit line BL1 not read is precharged to low level shape
State.
Then, while the information of the first bit corresponding first bit line BL0 and the second bit line BL1 is read, wherein due to
First bit line BL0 and the second bit line BL1 have been precharged to high level, when in the first bit line BL0 and the second bit line BL1 at least
It one when being pulled down to low level, that is to say there are when high level to low level current path, read first bit
Information be 0；Conversely, when the first bit line BL0 of reading and the second bit line BL1 keep high level state, namely be not present
When high level to low level current path, the information of read first bit is 1.
Step S302: when reading the information of second bit, second bit line and the third bit line is equal
It is precharged to high level, and first bit line is precharged to low level, while reading second bit line and the third
The information of bit line, when there are when high level to low level access, then being read in second bit line and the third bit line
Second bit storage information be 0；When in second bit line and the third bit line there is no from high level to
When low level access, the information of read second bit is 1.
In specific implementation, when having read the information of the first bit, it is corresponding the second bit can then to be read
Information.Firstly, i.e. the second bit line BL1 and third bit line BL2 is equal by two bit lines to be read in three bit lines of ROM cell
It is precharged to high level state, and the first bit line BL0 not read is precharged to low level state.
Then, while the information of the second bit corresponding second bit line BL1 and third bit line BL2 is read, wherein due to
Second bit line BL1 and third bit line BL2 have been precharged to high level, when in the second bit line BL1 and third bit line BL2 at least
It one when being pulled down to low level, that is to say there are when high level to low level current path, read second bit
Information be 0；Conversely, when the second bit line BL1 of reading and third bit line BL2 keep high level state, namely be not present
When high level to low level current path, the information of read second bit is 1.
Fig. 4 shows the structural schematic diagram of the reading device of one of embodiment of the present invention ROM cell.As shown in Figure 4
ROM cell reading device 400, may include the first reading unit 401 and the second reading unit 402, in which:
First reading unit 401, suitable for when reading the information of first bit, by first bit line and described
Second bit line is precharged to high level, and the third bit line is precharged to low level, while reading first bit line
With the information of second bit line, when there are high level to low level access in first bit line and second bit line
When, then the information of the read first bit storage is 0；It is not present when in first bit line and second bit line
When from high level to low level access, the information of read first bit is.
Second reading unit 402, suitable for when reading the information of second bit, by second bit line and described
Third bit line is precharged to high level, and first bit line is precharged to low level, while reading second bit line
With the information of the third bit line, when in second line and the third bit line there are when high level to low level access,
Then the information of the read second bit storage is 0；When in second bit line and the third bit line there is no from
When high level to low level access, the information of read first bit is 1.
Fig. 5 shows the structural schematic diagram of one of embodiment of the present invention ROM cell.ROM cell as shown in Figure 5,
May include:
At least one column MOSFET, each column MOSFET includes more than two MOSFET, each MOSFET successively coupled
It is respectively provided with grid end, the first active area and the second active area, and the adjacent active area between MOSFET adjacent in same row
It shares.
For example, shown in Figure 5, the first wordline WL0 therein corresponds to MOSFET501, and the second wordline WL1 is corresponding
MOSFET502, third wordline WL2 correspond to MOSFET503, and MOSFET501, MOSFET502 and MOSFET503 are in same row
Three MOSFET, MOSFET502MOSFET503, wherein MOSFET502 is adjacent with MOSFET501 and MOSFET503 respectively.
So, the adjacent active area between adjacent MOSFET shares, i.e. the second active area of MOSFET501 and MOSFET502's
First active area is same active area, and the first active area of the second active area of MOSFET502 and MOSFET503 have to be same
Source region.
Due to active area having the same between two MOSFET adjacent in same row, then, when in same row
When the information stored in MOSFET determines, the first active area and ground wire VSS, the first bit line BL0, the second bit line of current MOSFET
The connection relationship of BL1 or third bit line BL2 are also decided simultaneously, i.e., the first active area of the described MOSFET502 is suitable for root
The information stored in MOSFET501 according to the same row previous row adjacent with the MOSFET502, with ground wire VSS, the first bit line
BL0, the second bit line BL1 or the BL2 connection of third bit line.
When the first active area and ground wire VSS, the first bit line BL0, the second bit line BL1 or third bit line of current MOSFET
After the connection relationship of BL2 is decided, the second active area of the MOSFET is and ground wire VSS, the first bit line BL0, second
Bit line BL1 is still connect with third bit line BL2, then can again by the first active area of identified MOSFET and ground wire VSS,
The information stored in first bit line BL0, the connection relationship of the second bit line BL1 or third bit line BL2 and the MOSFET is i.e.
It can be determined.
Please shown in referring also to Fig. 4 and Fig. 5, below by taking MOSFET501 and MOSFET502 adjacent in same row as an example,
It is specific introduce the first active area for how determining MOSFET502 and the second active area respectively with ground wire VSS, the first bit line BL0, the
Connection relationship between two bit line BL1 or third bit line BL2.
When the information stored in MOSFET501 is 00, then, the first active area and the second active area of MOSFET501
Connection relationship between ground wire VSS, the first bit line BL0, the second bit line BL1 or third bit line BL2 can have following four:
(1) the first active area of MOSFET501 is connect with ground wire VSS, and the second active area is connect with the second bit line BL1；
(2) the first active area of MOSFET501 is connect with the first bit line BL0, and the second active area and third bit line BL2 connect
It connects；
(3) the first active area of MOSFET501 is connect with the second bit line BL1, and the second active area is connect with ground wire VSS；
(4) the first active area of MOSFET501 is connect with third bit line BL2, and the second active area and the first bit line BL0 connect
It connects.
From four kinds of above-mentioned situations it is found that the second of MOSFET501 has when the information stored in MOSFET501 is 00
Source region will likely be connect with ground wire VSS, the first bit line BL0, the second bit line BL1 or third bit line BL2.
Since the adjacent active regions between MOSFET501 and MOSFET502 share, the second active area of MOSFET502 is
For the first active area of MOSFET502, then, at this time what was certain was that: when the first active area of MOSFET502 will likely be with
Ground wire VSS, the first bit line BL0, the second bit line BL1 or the BL2 connection of third bit line.
When the first active area of MOSFET502 determines, then the information by being stored in MOSFET502, it can determine
The second active area of MOSFET502 connect pass with ground wire VSS, the first bit line BL0, the second bit line BL1 or third bit line BL2
System.Specifically, may include:
(1) when the information that the first active area of MOSFET502 connect with ground wire VSS, and stores in MOSFET502 is 00
When, the second active area of MOSFET502 can be connect with the second bit line BL1.
(2) when the information that the first active area of MOSFET502 connect with ground wire VSS, and stores in MOSFET502 is 01
When, the second active area of MOSFET502 can be connect with third bit line BL2；
(3) when the information that the first active area of MOSFET502 connect with ground wire VSS, and stores in MOSFET502 is 10
When, the second active area of MOSFET502 can be connect with the first bit line BL0；
(4) when the information that the first active area of MOSFET502 connect with ground wire VSS, and stores in MOSFET502 is 11
When, the second active area of MOSFET502 can be connect with ground wire VSS；
(5) when the first active area of MOSFET502 is connect with the first bit line BL0, and the information stored in MOSFET502 is
When 00, the second active area of MOSFET502 can be connect with third bit line BL2；
(6) when the first active area of MOSFET502 is connect with the first bit line BL0, and the information stored in MOSFET502 is
When 01, the second active area of MOSFET502 can be connect with the second bit line BL1；
(7) when the first active area of MOSFET502 is connect with the first bit line BL0, and the information stored in MOSFET502 is
When 10, the second active area of MOSFET502 can be connect with ground wire VSS；
(8) when the first active area of MOSFET502 is connect with the first bit line BL0, and the information stored in MOSFET502 is
When 11, the second active area of MOSFET502 can be connect with the first bit line BL0；
(9) when the first active area of MOSFET502 is connect with the second bit line BL1, and the information stored in MOSFET502 is
When 00, the second active area of MOSFET502 can be connect with ground wire VSS；
(10) when the information that the first active area of MOSFET502 connect with the second bit line BL1, and stores in MOSFET502
When being 01, the second active area of MOSFET502 can be with the first bit line BL0 connection；
(11) when the information that the first active area of MOSFET502 connect with the second bit line BL1, and stores in MOSFET502
When being 10, the second active area of MOSFET502 can be connect with third bit line BL2；
(12) when the information that the first active area of MOSFET502 connect with the second bit line BL1, and stores in MOSFET502
When being 11, the second active area of MOSFET502 can be connect with the second bit line BL1；
(13) when the information that the first active area of MOSFET502 connect with third bit line BL2, and stores in MOSFET502
When being 00, the second active area of MOSFET502 can be connect with the first bit line BL0；
(14) when the information that the first active area of MOSFET502 connect with third bit line BL2, and stores in MOSFET502
When being 01, the second active area of MOSFET502 can be connect with ground wire VSS；
(15) when the information that the first active area of MOSFET502 connect with third bit line BL2, and stores in MOSFET502
When being 10, the second active area of MOSFET502 can be connect with the second bit line BL1；
(16) when the information that the first active area of MOSFET502 connect with third bit line BL2, and stores in MOSFET502
When being 11, the second active area of MOSFET502 can be connect with third bit line BL2.
Similarly, when the information stored in MOSFET501 (MOSFET501 of same row previous row) is 01, then,
The first active area and the second active area of MOSFET501 and ground wire VSS, the first bit line BL0, the second bit line BL1 or third position
Connection relationship between line BL2 may be following four:
(1) the first active area of MOSFET501 is connect with ground wire VSS, and the second active area is connect with third bit line BL2；
(2) the first active area of MOSFET501 is connect with the first bit line BL0, and the second active area and the second bit line BL1 connect
It connects；
(3) the first active area of MOSFET501 is connect with the second bit line BL1, and the second active area and third bit line BL2 connect
It connects；
(4) the first active area of MOSFET501 is connect with third bit line BL2, and the second active area and the second bit line BL1 connect
It connects.
So, the first active area of MOSFET502 will likely with ground wire VSS, the first bit line BL0, the second bit line BL1 or
The BL2 connection of third bit line.
At this point it is possible to continue through the information stored in MOSFET502, come determine the second active area of MOSFET502 with
Ground wire VSS, the first bit line BL0, the second bit line BL1 or third bit line BL2 connection relationship.Specifically, may include:
(1) when the information that the first active area of MOSFET502 connect with ground wire VSS, and stores in MOSFET502 is 00
When, the second active area of MOSFET502 can be connect with the second bit line BL1；
(2) when the information that the first active area of MOSFET502 connect with ground wire VSS, and stores in MOSFET502 is 01
When, the second active area of MOSFET502 can be connect with third bit line BL2；
(3) when the information that the first active area of MOSFET502 connect with ground wire VSS, and stores in MOSFET502 is 10
When, the second active area of MOSFET502 can be connect with the first bit line BL0；
(4) when the information that the first active area of MOSFET502 connect with ground wire VSS, and stores in MOSFET502 is 11
When, the second active area of MOSFET502 can be connect with ground wire VSS；
(5) when the first active area of MOSFET502 is connect with the first bit line BL0, and the information stored in MOSFET502 is
When 00, the second active area of MOSFET502 can be connect with third bit line BL2；
(6) when the first active area of MOSFET502 is connect with the first bit line BL0, and the information stored in MOSFET502 is
When 01, the second active area of MOSFET502 can be connect with the second bit line BL1；
(7) when the first active area of MOSFET502 is connect with the first bit line BL0, and the information stored in MOSFET502 is
When 10, the second active area of MOSFET502 can be connect with ground wire VSS；
(8) when the first active area of MOSFET502 is connect with the first bit line BL0, and the information stored in MOSFET502 is
When 11, the second active area of MOSFET502 can be connect with the first bit line BL0；
(9) when the first active area of MOSFET502 is connect with the second bit line BL1, and the information stored in MOSFET502 is
When 00, the second active area of MOSFET502 can be connect with ground wire VSS；
(10) when the information that the first active area of MOSFET502 connect with the second bit line BL1, and stores in MOSFET502
When being 01, the second active area of MOSFET502 can be with the first bit line BL0 connection；
(11) when the information that the first active area of MOSFET502 connect with the second bit line BL1, and stores in MOSFET502
When being 10, the second active area of MOSFET502 can be connect with third bit line BL2；
(12) when the information that the first active area of MOSFET502 connect with the second bit line BL1, and stores in MOSFET502
When being 11, the second active area of MOSFET502 can be connect with the second bit line BL1；
(13) when the information that the first active area of MOSFET502 connect with third bit line BL2, and stores in MOSFET502
When being 00, the second active area of MOSFET502 can be connect with the first bit line BL0；
(14) when the information that the first active area of MOSFET502 connect with third bit line BL2, and stores in MOSFET502
When being 01, the second active area of MOSFET502 can be connect with ground wire VSS；
(15) when the information that the first active area of MOSFET502 connect with third bit line BL2, and stores in MOSFET502
When being 10, the second active area of MOSFET502 can be connect with the second bit line BL1；
(16) when the information that the first active area of MOSFET502 connect with third bit line BL2, and stores in MOSFET502
When being 11, the second active area of MOSFET502 can be connect with third bit line BL2.
Similarly, when the information stored in MOSFET501 is 10, then, the first active area of MOSFET501 and second has
Connection relationship between source region and ground wire VSS, the first bit line BL0, the second bit line BL1 or third bit line BL2 can also have four
Kind:
(1) the first active area of MOSFET501 is connect with ground wire VSS, and the second active area is connect with the first bit line BL1；
(2) the first active area of MOSFET501 is connect with the first bit line BL0, and the second active area is connect with ground wire VSS；
(3) the first active area of MOSFET501 is connect with the second bit line BL1, and the second active area and third bit line BL2 connect
It connects；
(4) the first active area of MOSFET501 is connect with third bit line BL2, and the second active area and the second bit line BL1 connect
It connects.
Therefore, when the information stored in MOSFET501 is 10, the second active area of MOSFET501 will likely be with ground wire
VSS, the first bit line BL0, the second bit line BL1 or the BL2 connection of third bit line.
At this point it is possible to continue through the information stored in MOSFET502, come determine the second active area of MOSFET502 with
Ground wire VSS, the first bit line BL0, the second bit line BL1 or third bit line BL2 connection relationship.Specifically, may include:
(1) when the information that the first active area of MOSFET502 connect with ground wire VSS, and stores in MOSFET502 is 00
When, the second active area of MOSFET502 can be connect with the second bit line BL1；
(2) when the information that the first active area of MOSFET502 connect with ground wire VSS, and stores in MOSFET502 is 01
When, the second active area of MOSFET502 can be connect with third bit line BL2；
(3) when the information that the first active area of MOSFET502 connect with ground wire VSS, and stores in MOSFET502 is 10
When, the second active area of MOSFET502 can be connect with the first bit line BL0；
(4) when the information that the first active area of MOSFET502 connect with ground wire VSS, and stores in MOSFET502 is 11
When, the second active area of MOSFET502 can be connect with ground wire VSS；
(5) when the first active area of MOSFET502 is connect with the first bit line BL0, and the information stored in MOSFET502 is
When 00, the second active area of MOSFET502 can be connect with third bit line BL2；
(6) when the first active area of MOSFET502 is connect with the first bit line BL0, and the information stored in MOSFET502 is
When 01, the second active area of MOSFET502 can be connect with the second bit line BL1；
(7) when the first active area of MOSFET502 is connect with the first bit line BL0, and the information stored in MOSFET502 is
When 10, the second active area of MOSFET502 can be connect with ground wire VSS；
(8) when the first active area of MOSFET502 is connect with the first bit line BL0, and the information stored in MOSFET502 is
When 11, the second active area of MOSFET502 can be connect with the first bit line BL0；
(9) when the first active area of MOSFET502 is connect with the second bit line BL1, and the information stored in MOSFET502 is
When 00, the second active area of MOSFET502 can be connect with ground wire VSS；
(10) when the information that the first active area of MOSFET502 connect with the second bit line BL1, and stores in MOSFET502
When being 01, the second active area of MOSFET502 can be with the first bit line BL0 connection；
(11) when the information that the first active area of MOSFET502 connect with the second bit line BL1, and stores in MOSFET502
When being 10, the second active area of MOSFET502 can be connect with third bit line BL2；
(12) when the information that the first active area of MOSFET502 connect with the second bit line BL1, and stores in MOSFET502
When being 11, the second active area of MOSFET502 can be connect with the second bit line BL1；
(13) when the information that the first active area of MOSFET502 connect with third bit line BL2, and stores in MOSFET502
When being 00, the second active area of MOSFET502 can be connect with the first bit line BL0；
(14) when the information that the first active area of MOSFET502 connect with third bit line BL2, and stores in MOSFET502
When being 01, the second active area of MOSFET502 can be connect with ground wire VSS；
(15) when the information that the first active area of MOSFET502 connect with third bit line BL2, and stores in MOSFET502
When being 10, the second active area of MOSFET502 can be connect with the second bit line BL1；
(16) when the information that the first active area of MOSFET502 connect with third bit line BL2, and stores in MOSFET502
When being 11, the second active area of MOSFET502 can be connect with third bit line BL2.
Similarly, when the information stored in MOSFET501 is 11, then, the first active area of MOSFET501 and second has
Connection relationship between source region and ground wire VSS, the first bit line BL0, the second bit line BL1 or third bit line BL2 can have following
Four kinds:
(1) the first active area of MOSFET501 is connect with ground wire VSS, and the second active area is connect with the first bit line BL1；
(2) the first active area of MOSFET501 is connect with the first bit line BL0, and the second active area is connect with ground wire VSS；
(3) the first active area of MOSFET501 is connect with the second bit line BL1, and the second active area and third bit line BL2 connect
It connects；
(4) the first active area of MOSFET501 is connect with third bit line BL2, and the second active area and the second bit line BL1 connect
It connects.
Therefore, when the information stored in MOSFET501 is 11, the second active area of MOSFET501 will likely be with ground wire
VSS, the first bit line BL0, the second bit line BL1 or the BL2 connection of third bit line.
At this point it is possible to continue through the information stored in MOSFET502, come determine the second active area of MOSFET502 with
Ground wire VSS, the first bit line BL0, the second bit line BL1 or third bit line BL2 connection relationship.Specifically, may include:
(1) when the information that the first active area of MOSFET502 connect with ground wire VSS, and stores in MOSFET502 is 00
When, the second active area of MOSFET502 can be connect with the second bit line BL1；
(2) when the information that the first active area of MOSFET502 connect with ground wire VSS, and stores in MOSFET502 is 01
When, the second active area of MOSFET502 can be connect with third bit line BL2；
(3) when the information that the first active area of MOSFET502 connect with ground wire VSS, and stores in MOSFET502 is 10
When, the second active area of MOSFET502 can be connect with the first bit line BL0；
(4) when the information that the first active area of MOSFET502 connect with ground wire VSS, and stores in MOSFET502 is 11
When, the second active area of MOSFET502 can be connect with ground wire VSS；
(5) when the first active area of MOSFET502 is connect with the first bit line BL0, and the information stored in MOSFET502 is
When 00, the second active area of MOSFET502 can be connect with third bit line BL2；
(6) when the first active area of MOSFET502 is connect with the first bit line BL0, and the information stored in MOSFET502 is
When 01, the second active area of MOSFET502 can be connect with the second bit line BL1；
(7) when the first active area of MOSFET502 is connect with the first bit line BL0, and the information stored in MOSFET502 is
When 10, the second active area of MOSFET502 can be connect with ground wire VSS；
(8) when the first active area of MOSFET502 is connect with the first bit line BL0, and the information stored in MOSFET502 is
When 11, the second active area of MOSFET502 can be connect with the first bit line BL0；
(9) when the first active area of MOSFET502 is connect with the second bit line BL1, and the information stored in MOSFET502 is
When 00, the second active area of MOSFET502 can be connect with ground wire VSS；
(10) when the information that the first active area of MOSFET502 connect with the second bit line BL1, and stores in MOSFET502
When being 01, the second active area of MOSFET502 can be with the first bit line BL0 connection；
(11) when the information that the first active area of MOSFET502 connect with the second bit line BL1, and stores in MOSFET502
When being 10, the second active area of MOSFET502 can be connect with third bit line BL2；
(12) when the information that the first active area of MOSFET502 connect with the second bit line BL1, and stores in MOSFET502
When being 11, the second active area of MOSFET502 can be connect with the second bit line BL1；
(13) when the information that the first active area of MOSFET502 connect with third bit line BL2, and stores in MOSFET502
When being 00, the second active area of MOSFET502 can be connect with the first bit line BL0；
(14) when the information that the first active area of MOSFET502 connect with third bit line BL2, and stores in MOSFET502
When being 01, the second active area of MOSFET502 can be connect with ground wire VSS；
(15) when the information that the first active area of MOSFET502 connect with third bit line BL2, and stores in MOSFET502
When being 10, the second active area of MOSFET502 can be connect with the second bit line BL1；
(16) when the information that the first active area of MOSFET502 connect with third bit line BL2, and stores in MOSFET502
When being 11, the second active area of MOSFET502 can be connect with third bit line BL2.
Fig. 6 shows the structure printing domain of one of embodiment of the present invention ROM cell.It is shown in Figure 6, wherein
Five-pointed star be used to indicate the programming hole on the common active regions of two adjacent MOSFET.
Wherein, the first active area of the corresponding MOSFET of the first wordline WL0 is connect with ground wire VSS, the second active area and
Two bit line BL1 connections.
When reading the information of the first bit, the first bit line BL0 and the second bit line BL1 are precharged to high level,
Third bit line BL2 is precharged to low level.At this point, the information of the first bit line BL0 and the second bit line BL1 are read simultaneously, wherein
Second bit line BL1 is pulled down to low level (close to ground wire VSS), and therefore, the information of read first bit is 0.
When reading the information of the second bit, the second bit line BL1 and third bit line BL2 are precharged to high level,
First bit line BL0 is precharged to low level.At this point, the information of the second bit line BL1 and third bit line BL2 are read simultaneously, wherein
Second bit line BL1 is pulled down to low level (close to ground wire VSS), and therefore, the information of read second bit is also 0.
Therefore, the information of two bits stored in the corresponding MOSFET of the first wordline WL0 is 00.
With continued reference to Fig. 6, the first active area of the corresponding MOSFET of the second wordline WL1 is connect with the second bit line BL1, and second
Active area is connect with the first bit line BL0.
When reading the information of the first bit, the first bit line BL0 and the second bit line BL1 are precharged to high level,
Third bit line BL2 is precharged to low level.At this point, the information of the first bit line BL0 and the second bit line BL1 are read simultaneously, wherein
First bit line BL0 and the second bit line BL1 are not pulled down to low level, and therefore, the information of read first bit is 1.
When reading the information of the second bit, the second bit line BL1 and third bit line BL2 are precharged to high level,
First bit line BL0 is precharged to low level.At this point, the information of the second bit line BL1 and third bit line BL2 are read simultaneously, due to
First bit line BL0 is precharged to low level, so that the second bit line BL1 is pulled down to low level, therefore, read second ratio
The information of special position is also 1.
Therefore, the information of two bits stored in the corresponding MOSFET of the second wordline WL1 is 01.
With continued reference to Fig. 6, the first active area of the corresponding MOSFET of third wordline WL2 is connect with the first bit line BL0, and second
Active area is connect with ground wire VSS.
When reading the information of the first bit, the first bit line BL0 and the second bit line BL1 are precharged to high level,
Third bit line BL2 is precharged to low level.At this point, the information of the first bit line BL0 and the second bit line BL1 are read simultaneously, wherein
First bit line BL0 is pulled down to low level by ground wire VSS, and therefore, the information of read first bit is 0.
When reading the information of the second bit, the second bit line BL1 and third bit line BL2 are precharged to high level,
First bit line BL0 is precharged to low level.At this point, the information of the second bit line BL1 and third bit line BL2 are read simultaneously, due to
First bit line BL0 is precharged to low level, so that the second bit line BL1 is pulled down to low level, therefore, read second ratio
The information of special position is also 1.
Therefore, the information of two bits stored in the corresponding MOSFET of third wordline WL2 is 10.
With continued reference to Fig. 6, the first active area and the second active area of the corresponding MOSFET of the 4th wordline WL3 is and ground wire
VSS connection.
When reading the information of the first bit, the first bit line BL0 and the second bit line BL1 are precharged to high level,
Third bit line BL2 is precharged to low level.At this point, when reading the information of the first bit line BL0 and the second bit line BL1 simultaneously, the
One bit line BL0 and the second bit line BL1 keep high level state, and therefore, the information of read first bit is 1.
When reading the information of the second bit, the second bit line BL1 and third bit line BL2 are precharged to high level,
First bit line BL0 is precharged to low level.At this point, the information of the second bit line BL1 and third bit line BL2 are read simultaneously, second
Bit line BL1 and third bit line BL2 keep high level state, and therefore, the information of read second bit is also 1.
Therefore, the information of two bits stored in the corresponding MOSFET of the 4th wordline WL3 is 11.
With continued reference to Fig. 6, the first active area of the corresponding MOSFET of the 5th wordline WL4 is connect with ground wire VSS, and second is active
Area is connect with third bit line BL2.
When reading the information of the first bit, the first bit line BL0 and the second bit line BL1 are precharged to high level,
Third bit line BL2 is precharged to low level.At this point, when reading the information of the first bit line BL0 and the second bit line BL1 simultaneously, the
One bit line BL0 and the second bit line BL1 keep high level state, and therefore, the information of read first bit is 1.
When reading the information of the second bit, the second bit line BL1 and third bit line BL2 are precharged to high level,
First bit line BL0 is precharged to low level.At this point, reading the information of the second bit line BL1 and third bit line BL2, third simultaneously
Bit line BL2 is pulled down to low level, and therefore, the information of read second bit is also 0.
Therefore, the information of two bits stored in the corresponding MOSFET of the 5th wordline WL4 is 01.
With continued reference to Fig. 6, the first active area of the corresponding MOSFET of the 6th wordline WL5 is connect with third bit line BL2, and second
Active area is connect with the second bit line BL1.
When reading the information of the first bit, the first bit line BL0 and the second bit line BL1 are precharged to high level,
Third bit line BL2 is precharged to low level.At this point, when reading the information of the first bit line BL0 and the second bit line BL1 simultaneously, the
Two bit line BL1 are pulled down to low level by third bit line BL2, and therefore, the information of read first bit is 0.
When reading the information of the second bit, the second bit line BL1 and third bit line BL2 are precharged to high level,
First bit line BL0 is precharged to low level.At this point, the information of the second bit line BL1 and third bit line BL2 are read simultaneously, second
Bit line BL1 and third bit line BL2 keep high level state, and therefore, the information of read second bit is also 1.
Therefore, the information of two bits stored in the corresponding MOSFET of the 6th wordline WL5 is 10.
In specific implementation, described MOSFET, MOSFET can be metal-oxide half field effect transistor, or other classes
The transistor of type.
Those of ordinary skill in the art will appreciate that all or part of the steps in the various methods of above-described embodiment is can
It is completed with instructing relevant hardware by program, which can store in computer readable storage medium, and storage is situated between
Matter may include: ROM, RAM, disk or CD etc..
The method and system of the embodiment of the present invention are had been described in detail above, the present invention is not limited thereto.Any
Field technical staff can make various changes or modifications without departing from the spirit and scope of the present invention, therefore guarantor of the invention
Shield range should be defined by the scope defined by the claims..
Claims (6)
1. a kind of ROM cell, which is characterized in that include more than two successively couplings including at least one column MOSFET, each column MOSFET
The MOSFET connect, each MOSFET are respectively provided with grid end, the first active area and the second active area, and adjacent two
The adjacent active area of MOSFET shares, wherein
The first active area of the MOSFET is suitable for depositing in the MOSFET according to the same row previous row adjacent with the MOSFET
The information of storage selects to connect with ground wire, the first bit line, the second bit line or third bit line；
The second active area of the MOSFET is suitable for the first active area and ground wire, the first bit line, second according to the MOSFET
The information stored in connection relationship and the MOSFET between bit line or third bit line, with the ground wire, described first
Bit line, second bit line or third bit line selection connection.
2. ROM cell according to claim 1, which is characterized in that the first active area of the MOSFET be suitable for according to
The information stored in the MOSFET adjacent same row previous row MOSFET, with ground wire, the first bit line, the second bit line or
The selection connection of three bit lines, comprising:
It is described when the first active area of the MOSFET of the same row previous row, the second active area are connect with the ground wire
The first active area of MOSFET is suitable for connecting with the ground wire；
When the first active area of the MOSFET of the same row previous row, the second active area respectively with the ground wire, described first
When bit line connects, the first active area of the MOSFET is suitable for connecting with the ground wire；
When the first active area of the MOSFET of the same row previous row, the second active area respectively with the ground wire, described second
When bit line is separately connected, the first active area of the MOSFET is suitable for connecting with second bit line；
When the first active area of the MOSFET of the same row previous row, the second active area respectively with the ground wire, the third
When bit line is separately connected, the first active area of the MOSFET is suitable for connecting with the third bit line；
When the first active area of the MOSFET of the same row previous row, the second active area respectively with first bit line, described
When ground wire is separately connected, the first active area of the MOSFET is suitable for connecting with the ground wire；
When the first active area of the MOSFET of the same row previous row, the second active area are connect with first bit line,
The first active area of the MOSFET is suitable for connecting with first bit line；
When the first active area of the MOSFET of the same row previous row, the second active area respectively with first bit line, described
When second bit line is separately connected, the first active area of the MOSFET is suitable for connecting with second bit line；
When the first active area of the MOSFET of the same row previous row, the second active area respectively with first bit line, described
When third bit line is separately connected, the first active area of the MOSFET is suitable for connecting with the third bit line；
When the first active area of the MOSFET of the same row previous row, the second active area respectively with second bit line, described
When ground wire is separately connected, the first active area of the MOSFET is suitable for connecting with the ground wire；
When the first active area of the MOSFET of the same row previous row, the second active area respectively with second bit line, described
When first bit line is separately connected, the first active area of the MOSFET is suitable for connecting with first bit line；
When the first active area of the MOSFET of the same row previous row, the second active area are connect with second bit line,
The first active area of the MOSFET is suitable for connecting with the ground wire；
When the first active area of the MOSFET of the same row previous row, the second active area respectively with second bit line, described
When third bit line is separately connected, the first active area of the MOSFET is suitable for connecting with the third bit line；
When the first active area of the MOSFET of the same row previous row, the second active area respectively with the third bit line, described
When ground wire is separately connected, the first active area of the MOSFET is suitable for connecting with the ground wire；
When the first active area of the MOSFET of the same row previous row, the second active area respectively with the third bit line, described
When first bit line is separately connected, the first active area of the MOSFET is suitable for connecting with first bit line；
When the first active area of the MOSFET of the same row previous row, the second active area respectively with the third bit line, described
When second bit line is separately connected, the first active area of the MOSFET is suitable for connecting with second bit line；
When the first active area of the MOSFET of the same row previous row, the second active area are connect with the third bit line,
The first active area of the MOSFET is suitable for connecting with the third bit line.
3. ROM cell according to claim 1, which is characterized in that the second active area of the MOSFET is suitable for according to institute
State the connection relationship between the first active area of MOSFET and ground wire, the first bit line, the second bit line or third bit line, Yi Jisuo
The information stored in MOSFET is stated, is connected with the ground wire, first bit line, second bit line or the third bit line
It connects, comprising:
The information that the second active area of the MOSFET is suitable for storing in the MOSFET is 00, and the first of the MOSFET
When active area is connect with the ground wire, it is connect with second bit line；
The information that the second active area of the MOSFET is suitable for storing in the MOSFET is 00, and the first of the MOSFET
When active area is connect with first bit line, it is connect with the third bit line；
The information that the second active area of the MOSFET is suitable for storing in the MOSFET is 00, and the first of the MOSFET
When active area is connect with first bit line, it is connect with the ground wire；
The information that the second active area of the MOSFET is suitable for storing in the MOSFET is 00, and the first of the MOSFET
When active area is connect with the third bit line, it is connect with first bit line；
The information that the second active area of the MOSFET is suitable for storing in the MOSFET is 01, and the first of the MOSFET
When active area is connect with the ground wire, it is connect with the third bit line；
The information that the second active area of the MOSFET is suitable for storing in the MOSFET is 01, and the first of the MOSFET
When active area is connect with first bit line, it is connect with the third bit line；
The information that the second active area of the MOSFET is suitable for storing in the MOSFET is 01, and the first of the MOSFET
When active area is connect with second bit line, it is connect with first bit line；
The information that the second active area of the MOSFET is suitable for storing in the MOSFET is 01, and the first of the MOSFET
When active area is connect with the third bit line, it is connect with the ground wire；
The information that the second active area of the MOSFET is suitable for storing in the MOSFET is 10, and the first of the MOSFET
When active area is connect with the ground wire, it is connect with first bit line；
The information that the second active area of the MOSFET is suitable for storing in the MOSFET is 10, and the first of the MOSFET
When active area is connect with first bit line, it is connect with the ground wire；
The information that the second active area of the MOSFET is suitable for storing in the MOSFET is 10, and the first of the MOSFET
When active area is connect with second bit line, it is connect with the third bit line；
The information that the second active area of the MOSFET is suitable for storing in the MOSFET is 10, and the first of the MOSFET
When active area is connect with the third bit line, it is connect with second bit line；
The information that the second active area of the MOSFET is suitable for storing in the MOSFET is 11, and the first of the MOSFET
When active area is connect with the ground wire, it is connect with the ground wire；
The information that the second active area of the MOSFET is suitable for storing in the MOSFET is 11, and the first of the MOSFET
When active area is connect with first bit line, it is connect with first bit line；
The information that the second active area of the MOSFET is suitable for storing in the MOSFET is 11, and the first of the MOSFET
When active area is connect with second bit line, first it is connect with the second；
The information that the second active area of the MOSFET is suitable for storing in the MOSFET is 11, and the first of the MOSFET
When active area is connect with the third bit line, it is connect with the third bit line.
4. a kind of memory, which is characterized in that including the described in any item ROM cells of claim 1-3.
5. a kind of read method of ROM cell, which is characterized in that the ROM cell includes that two or more successively couples
The information of two bits, respectively the first bit and the second bit, packet are stored in MOSFET, each MOSFET
It includes:
When reading the information of first bit, the first bit line and the second bit line are precharged to high level, and by the
Three bit lines are precharged to low level, while reading the information of first bit line and second bit line, when first bit line
There are the information that when high level to low level access, then read first bit stores in second bit line
It is 0；It is read described when in first bit line and second bit line there is no from high level to low level access
The information of first bit is 1；
When reading the information of second bit, second bit line and the third bit line are pre-charged supreme electricity
It is flat, and first bit line is precharged to low level, while reading the information of second bit line and the third bit line, when
There are when high level to low level access in second bit line and the third bit line, then read second bit
The information of position storage is 0；When in second bit line and the third bit line there is no from high level to low level access,
The information of read second bit is 1.
6. a kind of reading device of ROM cell, which is characterized in that ROM cell includes the MOSFET of more than two series connections,
The information of two bits, respectively the first bit and the second bit are stored in each MOSFET, comprising:
First reading unit, suitable for when reading the information of first bit, by the first bit line and the equal preliminary filling of the second bit line
Third bit line is precharged to low level, while reading the letter of first bit line and second bit line to high level by electricity
Breath, when in first bit line and second bit line there are when high level to low level access, then read described the
The information of one bit storage is 0；When there is no from high level to low level with second bit line for first bit line
When access, the information of read first bit is 1；
Second reading unit, suitable for when reading the information of second bit, by second bit line and the third position
Line is precharged to high level, and first bit line is precharged to low level, while reading second bit line and described
The information of third bit line, when there are when high level to low level access, then being read in second line and the third bit line
The information of second bit storage taken is 0；When second bit line is not present with the third bit line from high level
When to low level access, the information of read first bit is 1.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410821883.2A CN105788643B (en) | 2014-12-19 | 2014-12-19 | ROM cell and its read method and device, memory |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410821883.2A CN105788643B (en) | 2014-12-19 | 2014-12-19 | ROM cell and its read method and device, memory |
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| Publication Number | Publication Date |
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| CN105788643A CN105788643A (en) | 2016-07-20 |
| CN105788643B true CN105788643B (en) | 2019-07-02 |
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| CN103093823A (en) * | 2013-01-21 | 2013-05-08 | 苏州兆芯半导体科技有限公司 | ROM (Read Only Memory) and layout thereof |
| CN103106925A (en) * | 2013-01-04 | 2013-05-15 | 苏州兆芯半导体科技有限公司 | Serial read only memory (ROM) unit and reading method thereof |
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| CN103106925A (en) * | 2013-01-04 | 2013-05-15 | 苏州兆芯半导体科技有限公司 | Serial read only memory (ROM) unit and reading method thereof |
| CN103093823A (en) * | 2013-01-21 | 2013-05-08 | 苏州兆芯半导体科技有限公司 | ROM (Read Only Memory) and layout thereof |
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